Gate Sheet Resistance Research Articles

Titanium Silicide/Titanium Nitride Full Metal Gates for Dual-Channel Gate-First CMOS

We demonstrate a thermally stable titanium silicide/titanium nitride (TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> /TiN) full metal gate (FMG) for dual-channel gate-first high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> /metal gate complementary metal–oxide–semiconductor technology. Unlike prior tungsten-based FMG, the simple TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> /TiN gate electrode does not require any additional barrier layer preventing oxygen down-diffusion during high-temperature processing, as the TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> itself blocks oxygen. With HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based gate dielectrics and without any oxygen scavenging scheme, we thus demonstrate a capacitance-equivalent thickness in inversion ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\mathrm {inv}})$ </tex-math></inline-formula> of 1.11 nm, corresponding to an equivalent oxide thickness of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 0.7$ </tex-math></inline-formula> nm. Silicon channel nFET and silicon germanium channel pFET parametrics are similar to those of control devices utilizing a conventional a-Si/TiN metal-inserted poly-Si stack (MIPS) gate, while providing superior gate sheet resistance. By supplanting MIPS with such an FMG, we anticipate that contacted gate pitch can be scaled aggressively via reduced gate height and borderless source/drain contacts.

Optimization of Tungsten Dual Poly-Metal Gates in Memory Devices with Ti/WN/WSiN Barrier Metal

Due to the demand of high-speed/high-density and low power application of memory devices, tungsten dual poly gate (W-DPG; W/barrier metals/n+ and p+ poly-Si) electrode could be a good solution in order to reduce gate sheet resistance (Rs). Process optimization is completed for a diffusion barrier metal in a W-DPG. A new noble WSiN layer is inserted between the Ti/WN barrier metal and the tungsten gate electrode to maintain large grain size of W deposited by physical vapor deposition. The annealed WSiN during post-processing changes into crystallized WSi(x) mixed with SiN, which can make vertical conductive path between top and bottom interface, contributing to low vertical contact resistance (Rc) and low gate Rs adequate for high speed requirement of memory device. The Ti/WN/WSiN barrier is found to have the same electrical performance, ring oscillator singal delay as complicated multi-layes barrier metal, Ti/WN/TiN/WSi(x)/WN reported earlier. Therefore, the gate stack can be optimized by introducing a simpler diffusion barrier metal.

Low resistive tungsten dual poly-metal gates with multi-diffusion barrier metals in high performance memory devices

Ideal barrier metal arrangements in tungsten dual poly-metal (W/barrier metals/dual poly-Si) gates were developed for high performance, low-power and high density-memory devices. An additional metallic amorphous layer, such as TiN/WSix/WN, inserted at the diffusion barrier metals of Ti/WN resulted in both a low gate contact (Rc) and sheet resistance (Rs), which may result in superior improvement of the ring oscillator delay characteristics.

Investigation of Sidewall Oxidation on WSix Gates for Nano-Scale NAND Flash Memory Cells

Extrusions on W–polycide (WSix) gate sidewalls, sheet resistance (Rs), and device characteristics as well as memory cell performance for 70 nm NAND flash memory cells are investigated. To prevent the formation of unstable W–Si–O compounds, oxidation of WSix gate sidewalls prior to oxygen plasma ashing for source/drain photo resist removal is implemented, and then WSix extrusion can be absolutely suppressed. Moreover, the sheet resistance of a WSix gate can be improved near 40% by additional sidewall oxidation due to enlarged grain size and reduction in surface roughness; thus, the program voltage of memory cells can be significantly improved more than 1 V. Simultaneously, the saturation current of n-type metal–oxide–semicondutor field effect transistor (NMOSFET) shifts less than 4%, and cell threshold voltage fluctuations resulting from floating gate coupling are not obviously changed.

Transient Characterization of the Planar DMOS With a Metal/Poly-Si Replacement Gate

In this brief, transient characterization of a novel self-aligned metal/poly-Si gate planar double-diffused MOS (DMOS) transistor for high switching speed and high-efficiency dc/dc converter applications are reported. The breakdown voltage and the threshold voltage of the fabricated metal/poly-Si gate planar DMOS are 36 and 2.1 V, respectively. The gate sheet resistance of the metal/poly-Si gate is around 0.2 O/? , which is 50 times lower than that of the polysilicon gate. The low sheet resistance reduces the switching time, as well as the power loss of the device during the clamped inductive load switching. For a device with a drain current of 69 A/cm2, the turn-on and turn-off times are reduced from 29 to 25 ns and from 36 to 31 ns, respectively. The turn-on and turn-off switching energy losses are reduced by 22% and 15%, respectively.

A 30 V Self-Aligned Metal/Poly-Si Replacement Gate Planar DMOS for DC/DC Converters

In this letter, a novel self-aligned metal/poly-Si gate planar double-diffused MOS (DMOS) is proposed and demonstrated for high-switching-speed and high-efficiency dc/dc converter applications. The self-aligned metal/poly-Si gate is realized by a replacement gate technology. The fabricated metal/poly-Si gate planar DMOS has a breakdown voltage of 36 V and a threshold voltage of 2.1 V. The gate sheet resistance of the metal/poly-Si gate is around 0.2 Omega/square, which is 50 times lower than that of the polysilicon gate. The low sheet resistance reduces the switching time as well as the power loss of the device during switching. For a device with a drain current of 69 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the turn-on and turn-off times are reduced from 29 to 25 ns and from 36 to 31 ns, respectively. The turn-on and turn-off switching energy losses are reduced by 22% and 15%, respectively

열적으로 강인한 Molybdenium 게이트-PMOS Capacitor의 분석

In this paper, we report the properties of Mo metal employed as PMOS gate electrode. Mo on <TEX>$SiO_2$</TEX> was observed to be stable up to <TEX>$900^{\circ}C$</TEX> by analyzing the Interface with XRD. C-V measurement was performed on the fabricated MOS capacitor with Mo Bate on <TEX>$SiO_2$</TEX>. The stability of EOT and work-function was verified by comparing the C-V curves measured before and after annealing at 600, 700, 800, and <TEX>$900^{\circ}C$</TEX>. C-V hysteresis curve was performed to identify the effect of fired charge. Gate-injection and substrate-injection of carrier were performed to study the characteristics of <TEX>$Mo-SiO_2$</TEX> and <TEX>$SiO_2-Si$</TEX> interface. Sheet resistance of Mo metal gate obtained from 4-point probe was less than <TEX>$10\;\Omega\Box$</TEX> that was much lower than that of polysilicon.

Metal gate technology for nanoscale transistors—material selection and process integration issues

Reduction of the gate length and gate dielectric thickness in complementary metal oxide semiconductor (CMOS) transistors for higher performance and circuit density aggravates problems such as poly-silicon (poly-Si) gate depletion, high gate resistance, and dopant penetration from doped poly-Si gate. To alleviate these problems in nanoscale transistors, there is immense interest in the replacement of the conventional poly-Si gate material with metal gate materials. A metal gate material not only eliminates the gate depletion and dopant penetration problems but also greatly reduces the gate sheet resistance. In this paper, we discuss the material requirements for metal gate CMOS technology and the challenges involved in the integration of metal gate electrodes in a nanoscale transistor. Issues addressed include the choice of metal gate materials for conventional bulk and advanced transistor structures, the physics of the metal–dielectric interface, and the process integration of these materials in a CMOS process.

A metal/polysilicon damascene gate technology for RF power LDMOSFETs

This letter describes a metal/polysilicon damascene gate technology for RF power LDMOSFETs. We compare the performance of SOI LDMOSFETs with metal/polysilicon damascene gates to that of identical devices with n/sup +/ polysilicon gates. The gate sheet resistance of the metal/polysilicon gate was 0.2 /spl Omega//sq. This very low sheet resistance greatly improved f/sub max/ and peak PAE, especially for the wide gate fingers that are critical in RF power applications. With a 140 /spl mu/m gate finger width, f/sub max/ was improved from 5 GHz to 25 GHz, and peak PAE at 1.9 GHz was improved from 12% to 52%.

Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors

It has been known that using selective epitaxial growth (SEG) of silicon, to elevate source/drain regions, is beneficial to digital CMOS by reducing the junction leakage. In addition, this architecture also reduces the gate resistance by enabling a T-shape gate and allowing thicker silicides, which is beneficial for RF-CMOS regarding increased maximum oscillation frequency (f/sub max/) and lowering of the noise figure (NF). In this paper, we report the impact of the SEG-deep source/drain implant (DSDI) process sequence and Co silicide thickness on DC and RF performance of NMOS transistors. Up to a 28%-45% improvement in f/sub max/ is achievable due to a T-shaped gate and thicker Co, made possible by an elevated source/drain (/sup E/S/D) architecture. The maximum transconductance (g/sub m/) of the /sup E/S/D device reaches a value of 1100 mS/mm, which in turn gives a very high f/sub T/ of 150 GHz. The low gate sheet resistance obtained with this architecture is also very beneficial for suppressing noise figure in the low-noise amplifier (LNA) circuit demonstrated in this paper. Furthermore, it is shown by simulation that the noise performance of an RF LNA improves due to the SEG and the Co thickness in the T-shaped gate of the NMOS transistor.

Frequency-dependent resistive and capacitive components in RF MOSFETs

It is found from measured high frequency (HF) S-parameter data that the extracted effective gate sheet resistance (R/sub gsh/), effective gate unit-area capacitance (C/sub gg, unit/), and transconductance (G/sub m/) in radio-frequency (RF) MOSFETs show strong frequency dependency when the device operates at frequencies higher than some critical frequency. As frequency increases, R/sub gsh/ increases but C/sub gg, unit/ and G/sub m/ decrease. This behavior is different from what we have observed at low or medium frequencies, at which these components are constant over a frequency range. This phenomenon has been observed in MOSFETs with L/sub f/ longer than 0.35 μm at frequencies higher than 1 GHz, and becomes more serious as L/sub f/ becomes longer and the frequency higher. This behavior can be explained by a MOSFET model considering the Non-Quasi-Static (NQS) effect. Simulation results show that an RF model based on BSIM3v3 with the NQS effect describes well the behaviors of both real and imaginary parts of Y/sub 21/ of the device with strong NQS effect even though its fitting to Y/sub 11/ needs to be improved further.

Two-step rapid thermal annealing (TS-RTA) to suppress out-diffusion of dopants without degrading short channel effect of transistor

We examined the effects of source/drain annealing condition on the gate sheet resistance and short channel effect. We found that two-step rapid thermal annealing (TS-RTA) technology, where 700/spl deg/C, 3 min pre-annealing in O/sub 2/ is introduced before 1000/spl deg/C anneal in N/sub 2/, suppressed dopant out-diffusion without degrading short channel effect of transistor.

Elevated source drain devices using silicon selective epitaxial growth

Elevated source drain (ESD) structure in deep submicron metal oxide semiconductor field effect transistors (MOSFETs) can help reduce parasitic series resistance and simultaneously achieve shallow contacting junctions to minimize short channel effects. A self-aligned ESD structure in conventional complimentary metal–oxide–semiconductor processing can be achieved using silicon selective epitaxial growth (SEG). A robust low thermal budget high quality SEG process using a commercial rapid thermal chemical vapor deposition reactor for ESD formation has been demonstrated. The preclean sequence prior to SEG is the key to achieve facet-free epitaxy. Low line-to-line leakage confirms the high selectivity to nitride and oxide. The growth on exposed polysilicon (poly) gates leads to gate linewidth widening and lower gate sheet resistance. ESD parametric data suggest that the well doping needs to be optimized to counter the slight increase in n+-p diode leakage. Capacitance–voltage simulations indicate that the gate to drain capacitance initially decreases and then increases with SEG thickness.

Characterization of channel width dependence of gate delay in 0.18-μm CMOS technology

The channel width dependence of gate delay in 0.18-/spl mu/m CMOSFET has been characterized. Substantial increase of gate delay observed in the narrow channel width region is found due to channel width independent capacitance components, which is inherent to transistors. An expression for gate delay considering the channel width independent capacitance components and gate sheet resistance is derived and compared with experimental data. The minimum gate delay is shown to result from the compromise between delay components proportional to channel width and proportional to inverse of channel width. Although the channel width independent capacitance is negligible in the wide channel width region, the gate delay of the 1-/spl mu/m channel width ring oscillator increased more than 20% compared with the 5-/spl mu/m channel width ring oscillator.

Effects of thermal processes after silicidation on the performance of TiSi/sub 2//polysilicon gate device

The effects of thermal processes after silicidation on the gate depletion, threshold voltage (V/sub th/) shift, drive current, and sheet resistance of TiSi/sub 2//polysilicon (Ti-polycide) gate devices are evaluated. The dopant depletion of the polysilicon film, which is known to increase the V/sub th/ and to degrade the drive-current, increases with increasing temperature of the post-thermal process. However, the V/sub th/ roll-off characteristic in nMOSFETs is enhanced with increasing temperature. Furthermore, the drive-current is significantly degraded by the gate reoxidation process. The sheet resistance of the Ti-polycide gate increases with gate reoxidation as well as with increased post-thermal processes.

Advanced salicides for 0.10 μm CMOS: Co salicide processes with low diode leakage and Ti salicide processes with direct formation of low resistivity C54 TiSi2

The scaling of CMOS technologies to 0.10 μm and beyond imposes increasingly demanding constraints to self-aligned silicide (salicide) processes. For high performance devices, it is essential that salicide processes achieve low gate and source-drain sheet resistance as well as low silicide to source-drain diffusion contact resistance, and maintain low junction leakage. This becomes increasingly difficult as junction depths and linewidths are scaled. In this paper we present an overview of the development of advanced Ti and Co salicide processes, with implementations into a high performance 0.10 μm complementary metal-oxide-semiconductor (CMOS) technology. For Co salicide, the main scaling issue is diode leakage on shallow junctions. We show that the use of pre-amorphization implants or a pre-Co deposition sputter etch improves diode leakage distributions, but fails to eliminate high leakage outliers. Co deposition temperature and rapid thermal processing (RTP) variables were found to have a strong effect on diode leakage, with optimization of either one resulting in tight low leakage distributions on shallow junctions. For conventional Ti salicide processes, the main scaling issue is sheet resistance on narrow lines due to incomplete high resistivity C49 TiSi2 to low resistivity C54 TiSi2 transformation. We present X-ray diffraction (XRD) and high resolution transmission electron microscopy (HRTEM) studies that indicate that direct growth of C54 TiSi2 bypassing the C49 phase is achieved at low temperatures on polycrystalline or amorphous Si with the addition of Mo impurities, eliminating the narrow line effect. The mechanism is demonstrated to be nucleation of MoSi2 and an unidentified phase at the Ti/Si interface, followed by epitaxial growth of C54 TiSi2 on these templates. Ti salicide processes with Mo impurities were evaluated, demonstrating an optimized one-step RTP process combining Mo and pre-amorphization implants that maintains low sheet resistance to 0.06 μm gate lengths. Successful implementations into a 0.10 μm flow were achieved both for optimized Co salicide or Ti salicide processes.

Gate engineering for deep-submicron CMOS transistors

Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET's. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET's is investigated. The suppression of boron penetration is confirmed by the SIMS profiles, and is attributed mainly to the diffusion retardation effect in bulk polysilicon by the presence of nitrogen. The MOSFET' I-V characteristics, MOS capacitor quasi-static C-V curves, SIMS profiles, gate sheet resistance, and oxide Q/sub bd/ are compared for different nitrogen implant conditions. A nitrogen dose of 5/spl times/10/sup 15/ cm/sup -2/ is found to be the optimum choice at an implant energy of 40 keV in terms of the overall electrical behavior of CMOSFET's. Under optimum design, gate nitrogen implantation is found to be effective in eliminating boron penetration without degrading performance of either p/sup +/ gate p-MOSFET and n/sup +/ gate n-MOSFET. Secondly, the impact of gate microstructure on the performance of deep-submicron CMOSFET's is discussed by comparing poly and amorphous silicon gate deposition technologies. Thirdly, poly-Si/sub 1-x/Ge/sub x/ is presented as a superior alternative gate material. Higher dopant activation efficiently results in higher active-dopant concentration near the gate/SiO/sub 2/ interface without increasing the gross dopant concentration. This plus the lower annealing temperature suppress the dopant penetration. Phosphorus-implanted poly-Si/sub 1-x/Ge/sub x/ is gate is compared with polysilicon gate in this study.

A transistor performance figure-of-merit including the effect of gate resistance and its application to scaling to sub-0.25-μm CMOS logic technologies

This paper presents an improved figure-of-merit (FOM) for CMOS performance which includes the effect of gate resistance. Performance degradation due to resistive polysilicon gates is modeled as an additional delay proportional to the RC product of a polysilicon line. The new FOM is verified from delay measurements on inverter chains fabricated using a 0.25-/spl mu/m CMOS process. A furnace TiSi/sub 2/ process is used to underscore the effect of increased sheet resistance of narrow polysilicon lines. Excellent correlation between measured and predicted inverter chain delays is obtained over a variety of design, process and bias conditions. An expression for the gate sheet resistance requirement is derived from the new FOM. Using this expression, requirements on the gate sheet resistance are calculated corresponding to a technology roadmap for performance and oxide thickness.

Thin silicide development for fully-depleted SOI CMOS technology

Ultrathin silicide with thickness less than 30 nm and specific contact resistivity to silicon less than mid-10/sup -7//spl Omega/-cm/sup 2/ is necessary for achieving low contact resistance in a sub-0.25-/spl mu/m fully-depleted (FD) silicon-on-insulator (SOI) CMOS technology. This contact problem becomes even more severe as one continues to scale down the device dimensions. We first studied the effects of source/drain series resistance and gate sheet resistance on the device speed performance and obtained a set of desired design criteria. These were used along with a transmission line model to yield a silicide design space, which was then used to evaluate the experimental results. Both cobalt and titanium silicide processes were implemented and found to satisfy the design criteria. Final device characteristics were also measured. Several process integration issues related to contact dielectric deposition and contact barrier integrity were found to greatly impact the final contact properties. These along with the detailed fabrication process are discussed.

Self-aligned Ti and Co silicides for high performance sub-0.18 μm CMOS technologies

An overview of the development of advanced Ti and Co self-aligned silicide (SALICIDE) processes for deep-sub micron high performance CMOS technologies at Texas Instruments is presented. SALICIDES are a key factor for scaling of high-performance CMOS devices. They are used to lower sheet resistance of gate and source/drain regions, contact resistance and source/drain series resistance, increasing device performance and lowering RC delays to allow faster operation. Their applicability to deep-sub-micron technologies is determined by the fundamental materials aspects controlling silicide phase formation and evolution, as well as process integration issues such as effect of subsequent processing steps on the silicide films or effects of silicide related process steps on transistor characteristics. The main scaling issues for conventional processes, high resistivity on narrow lines for Ti SALICIDE and high diode leakage on shallow junctions for Co SALICIDE, are addressed. Detailed kinetic studies of the high resistivity to low resistivity phase transformations (TiSi 2 C49 to C54 and CoSi to CoSi 2) and their dependence on linewidth and film thickness are presented. A nucleation density model is shown to account for the measured linewidth dependence and effect of pre-amorphization implants on the TiSi 2 C49 to C54 transformation and explain, as a result, narrow line sheet resistance. This overview covers studies on rapid thermal processing (RTP) for Ti and for Co SALICIDE, pre-amorphization implants and Mo impurities which allowed the first demonstration of low resistivity Ti SALICIDE at 0.10 μm gate lengths, as well as applications to sub-0.18 μm CMOS technologies and integration issues.