The limits for overcoming shrinking localized oxidation of silicon type isolation in the subhalfmicron design rules area are considered: geometric limitations and field implant defect generation are investigated. A super sealed interface local oxidation (SUPERSILO) field isolation process using rapid thermal nitridation of silicon is characterized in terms of morphology, defect density, and electrical performance. With this isolation an encroachment lower than 100 nm is obtained in a large field area of 400 nm finished field oxide. Field oxide thinning and corner encroachment are minimized compared to other conventional isolations and make this process a better candidate for scaling down to 0.7 μm active area pitch design rules. The compatibility with low gate oxide defect density for a thickness as low as 7 nm is demonstrated. Several boron p+ field channel stop implant processes are investigated by characterizing three different scenarios: implanting before field oxidation (classical), through field oxide after the oxidation mask removal (field‐retro), and through the poly gate material (poly‐retro). In order to avoid defect generation, the retrograde scenarios will be the solution in the future. The poly‐retro scenario is the one that reduces boron segregation by a factor of about 10 with respect to the classical scenario and allows high performance without affecting the sustaining voltage. The use of a 0° tilt boron implant at 350 keV through the field oxide and poly gate material stack is shown to be practicable and reproducible.