Gate Oxide Capacitance Research Articles

Experimentally verified organic electrochemical transistor model

The Bernards–Malliaras model, published in 2007, is the primary reference for the operation of organic electrochemical transistors (OECTs). It assumes that, as in most transistors, the electronic transport is drift only. However, in other electrochemical devices, such as batteries, the charge neutrality is accompanied by diffusion-only transport. Using detailed 2D device simulations of the entire structure while accounting for ionic and electronic conduction, we show that high ion density (>1019 cm−3) results in Debye screening of the drain–source bias at the electrodes’ interface. Hence, unlike the drift-only current in standard FETs or low ion density OECTs, the current in high ion density OECTs is diffusion only. Also, we show that since in OECTs, the volumetric capacitor and the semiconductor are one, the threshold voltage has a different meaning than that in FETs, where the semiconductor and the gate-oxide capacitor are distinct entities. We use the above insights to derive a new model useful to experimentalists. Lastly, we fabricated PEDOT:PSS fiber-OECTs and used the results to verify the model.

Investigations of 4H‐SiC trench MOSFET with integrated high‐K deep trench and gate dielectric

AbstractThis paper proposes and investigates a novel 4H‐SiC trench MOSFET (TMOS) with integrated high‐K deep trench and gate dielectric (INHK‐TMOS). The integrated high‐K (INHK) consists of a high‐K gate dielectric and an extended high‐K deep trench dielectric in the drift region. Firstly, the high‐K gate dielectric together with the metal‐forming high‐K metal gate structure, which increases the gate oxide capacitance (COX), reduces the threshold voltage (VTH) and the specific on‐resistance (Ron,sp). Secondly, the extended high‐K deep trench dielectric not only modulates the electric field in the drift region by introducing a new electric field peak at the bottom of the high‐K deep trench dielectric, thereby enhancing the breakdown voltage (BV), but also improves the doping concentration (ND) of the drift region by the assist depletion effect of the high‐K dielectric, further optimizing the forward conduction characteristics. Simulation results demonstrate that when compared to the conventional TMOS, the INHK‐TMOS using HfO2 exhibits a 52.6% reduction in VTH, a 52.1% reduction in Ron,sp, a 20.3% increasement in BV and a 202.3% improvement in figure of merit.

Toward Low‐Power Cryogenic Metal‐Oxide Semiconductor Field‐Effect Transistors

Herein, cryogenic field‐effect transistors (FETs) are discussed. In particular, the saturation of the subthreshold swing due to band tailing is studied. It is shown with simulations and experiments that engineering of the oxide‐channel interfaces and a strong increase of the gate oxide capacitance are effective in improving the switching behavior of the device. The implication of scaling the oxide capacitance on the power consumption of cryogenic devices is investigated, too. Furthermore, an alternative for conventional doping in cryogenic transistors is discussed. Based on synchrotron X‐Ray absorption spectroscopy at total fluorescence (XAS‐TFY) and ultraviolet photoemission spectroscopy (UPS) measurements, it is shown experimentally that in true nanoscale devices, a simple coating yields a shift of the conduction band that is equivalent to a very high dopant concentration. As a result, nanoscale cryogenic steep slope FETs with strongly improved electrical characteristics become feasible.

High-threshold-voltage and low-leakage-current of normally-off H-diamond FET with self-aligned Zr/ZrO2 gate

Normally-off field effect transistor (FET) is highly required for the safe and energy-efficient operation of power switching system. The hydrogen-terminated diamond (H-diamond) FET possesses outstanding properties whereas it usually shows normally on operation. In this paper, high-threshold-voltage and low-leakage-current of normally-off H-diamond FET was achieved via ZrO2/Zr gate fabricated by thermal oxidation (TO) with merits of non-pollution and simple process. The normally-off operation owed to the work function difference between Zr and H-diamond and the positive fixed charge of ZrO2. The X-ray photoelectron spectroscopy results reveal the ZrO2/Zr gate structure and the stoichiometric composition of Zr to O (1:2). The high threshold voltage (−2.7 V) and low drain-source leakage current (10−8 mA/mm) may be attributed to the Schottky barrier of Zr/H-diamond. Additionally, the gate leakage is suppressed by TO-ZrO2. The subthreshold swing, on-off current ratio and gate oxide capacitance per square centimeter are 161 mV/dec, 108 and 0.37 μF/cm2, respectively. These performances demonstrate that the ZrO2/Zr/H-diamond FET would provide an alternative approach for low power H-diamond FET.

Tunable Multilevel Gate Oxide Capacitance and Flat‐Band Voltage Shift Characteristics by Filament Formation in Double‐Floating‐Gate Metal–Oxide–Semiconductor Capacitors (Adv. Electron. Mater. 4/2023)

Metal–Oxide–Semiconductors In article number 2201110 by Tae-Sik Yoon and coworkers, a tunable multilevel gate oxide capacitance and flat-band voltage shift characteristics in double-floating-gate metal-oxidesemiconductor capacitors are demonstrated as operating with both conducting filament formation and electrical charging in the gate stack, depending on the constituent materials and device geometries. It paves the way for the potential application to non-volatile memory and programmable logic devices.

Tunable Multilevel Gate Oxide Capacitance and Flat‐Band Voltage Shift Characteristics by Filament Formation in Double‐Floating‐Gate Metal–Oxide–Semiconductor Capacitors

AbstractTunable multilevel gate oxide capacitance and flat‐band voltage shift characteristics in double‐floating‐gate metal–oxide–semiconductor (DFG‐MOS) capacitors are investigated for non‐volatile memory and programmable logic device applications. The DFG‐MOS capacitor with the structure of Ag(control gate)/CeO2(upper control oxide)/Al(upper FG)/CeO2(lower control oxide)/Pt(lower FG)/HfO2(tunneling oxide) on n‐Si substrate, that is Ag/CeO2/Al/CeO2/Pt/HfO2/n‐Si, exhibits three capacitance states as a result of reversible formation and rupture of conducting filaments at serially stacked Ag/CeO2/Al and Al/CeO2/Pt capacitors upon applying positive and negative gate voltages, respectively. In contrast, the DFG‐MOS capacitor with Ag/CeO2/Pt/HfO2/Pt/HfO2/n‐Si employing inert Pt upper and lower FGs exhibits two capacitance states via the formation and rupture of filament only at the upper Ag/CeO2/Pt stack. Instead, it accompanies a flat‐band voltage shift by electrical charging at the lower FG of Pt. The proposed devices operate with tunable multilevel gate oxide capacitance and flat‐band voltage shift associated with filament formation inside gate stacks and electrical charging with respect to the constituent materials of the FGs. These results pave the way for potential application to non‐volatile memory and programmable MOSFET logic device with tunable gate oxide capacitance, without relying solely on the electrical charging used in the current flash‐type memory.

Ferroelectric FETs With Separated Capacitor in the Back-End-of-Line: Role of the Capacitance Ratio

Hafnium oxide based ferroelectric (FE) memory concepts like FE field effect transistors (FeFETs) will become increasingly important. They are highly scalable, provide high operation speed, and consume low power. Just recently, an 1T1C FeFET concept with one transistor (1T) and one separated FE capacitor (1C) was demonstrated. This alternative approach is promising to overcome the drawbacks usually observed for the classic 1T concept like limited endurance, reduced retention, and high device-to-device variability. Electrically, the 1T1C FeFET consists of a series connection of the FE capacitor and the gate oxide capacitance. To operate at low voltages, a large fraction of the applied voltage must drop across the FE, which can be achieved by optimizing the capacitance ratio. Herein, 1T1C FeFETs with various capacitance ratios are fabricated and its impact on the electrical performance is discussed. Furthermore, the observed endurance of up to 10 8 field cycles illustrates the great potential of the new concept.

A Threshold Voltage Definition Based on a Standardized Charge Versus Voltage Relationship

Threshold voltage defined by a band bending of twice the substrate intrinsic-to-Fermi level difference has been widely accepted. However, there are shortcomings with this analytical definition. Since the inversion condition is governed by the substrate Fermi level (i.e., majority carrier density per volume), inversion carrier density per area at threshold inadequately depends on substrate doping and temperature. Another problem is that the definition is not applicable to fully depleted thin body devices, such as FinFETs and silicon-on-insulator FETs, widely used today. To solve these problems, a new definition of threshold voltage is proposed, which is based on a standardized charge versus voltage relationship of ideal metal-oxide-semiconductor capacitors. Threshold voltage is specified by a threshold inversion carrier density per area, which is a simple function of gate oxide capacitance and thermal voltage. Dependence of the proposed threshold voltage on substrate doping, body thickness, and temperature for both bulk and double-gate FETs is discussed using semi-classical analytical equations.

Analytical modeling and TCAD simulation for subthreshold characteristics of asymmetric Tunnel FET

In this paper, a 2-D analytical model has been developed for asymmetric Tunnel FET known as Non-Uniform Body with Dual Material Source TFET (NUTFET-DMS) Device. The proposed model formulation is based on the solution of Poisson’s equation using suitable boundary conditions. The derived model for subthreshold characteristics is proposed for numerous device parameters such as surface potential, lateral, vertical electric fields, drain current and threshold voltage. In this work, for the first time the model accounts the prodigious non-uniform nature of the Channel, Gate Dielectric Thickness, Dielectric Constants and Oxide Capacitance, at different portions of the device. Next, to validate the accuracy of the model, device simulation using Sentaurus TCAD with calibrated models is reported and a close agreement with 85–95% accuracy is observed. The detailed and systematic device analysis is presented by studying different cases of applied biases, variation of device dimensions, oxide materials etc. It is reported that the proposed TFET device is able to obtain a vertical and lateral electric field of ± 5 MV/cm near the tunneling junction, implying a drain current in the order of 10−5A/μm. The present study highlights that the proposed TFET offers great potential for low standby power logic and low power applications.

Process Corresponding Implications Associated with a Conclusive Model-Fit Current-Voltage Characteristic Curves

NFinFET transistors with various fin widths (110 nm, 115 nm, and 120 nm) are put into measurements, and the data are collected. By using the modified model, the measure data is fitted. Several parameters in the formula of modified model are determined to make both the measured data and the fitting data almost as close as possible. Those parameters are listed and analyzed, including kN (proportional to channel width and gate oxide capacitor, and inversely proportional to the channel length) λ (the inverse of Early Voltage), and sometimes Vth (Threshold Voltage). By kN, the appropriate process control can be high lighted, the corresponding channel concentration can be calculated and thus many implicit physical quantities may be exploited.

Enhancing the electrical performance of InAs nanowire field-effect transistors by improving the surface and interface properties by coating with thermally oxidized Y2O3.

Due to their excellent electrical characteristics, InAs nanowires (NWs) have great potential as conducting channels in integrated circuits. However, the surface effect and loose native oxide coverage can deteriorate the performance of InAs NW transistors. Y2O3, a high-k dielectric with low Gibbs free energy, has been proposed to modify the InAs NW surface. Here, we systematically investigate the effect of Y2O3 coating on the performance of InAs NW field-effect transistors (FETs). We first explore the influence of the thermal oxidation process of Y2O3 on the performance of back-gated FETs. We then observe that the coverage of Y2O3/HfO2 bilayers on the NW decreases the hysteresis (the smallest value reaches 0.1 V), subthreshold swing (SS, down to 169 mV dec-1) and on-state resistance Ron, and increases the field-effect mobility μFE (up to 4876.1 cm2 V-1 s-1) and the on-off ratio, mainly owing to the passivation effect on the NW surface. Finally, paired top-gated NW FETs with a Y2O3/HfO2 bilayer and a single layer of HfO2 dielectric are fabricated and compared. The Y2O3/HfO2 bilayer provides better gate control (SSmin = 113 mV dec-1) under a smaller gate oxide capacitance, with an interface trap density as low as 1.93 × 1012 eV-1 cm-2. The use of the Y2O3/HfO2 stack provides an effective strategy to enhance the performance of III-V-based transistors for future applications.

Memoryless linearity in undoped and B-doped graphene FETs: A relative investigation to report improved reliability

In this work, reliability of boron-doped graphene field effect transistor (GFET) is examined by modeling the effect of doping in terms of linearity performance metrics. The key potential (VN) induced in B doped GFET is analytically modeled for various B doping concentrations. An accurate compact equivalent circuit model integrated with VN for B doped GFET is proposed to investigate the effects of memoryless nonlinearity on transconductance. The proposed equivalent circuit model is verified with the simulated results of an industry standard circuit simulation tool. The fundamental figures of merit (FOMs) such as second and third order harmonic distortion terms (HD2 and HD3), gain compression point (Ain, 1dB), second and third order intermodulation distortion terms (IM2 and IM3), second and third order input intercept points (AIIP2 and AIIP3) are mathematically modeled for doped GFET to examine the linear behaviour of the device. In addition to that, these FOMs are investigated with respect to various B doping concentrations, applied small signal amplitude, and gate-oxide capacitance. The proposed model is compatible and predicting accurate results for both B doped and undoped GFET. The simulation results are having excellent agreement with the mathematical model, which are also compared with undoped GFET and conventional MOSFET. It is also noticed that by doping the graphene sheet with boron significantly induces bandgap in it and hence enhances the linear behaviour of the B doped GFET. Hence, reliability of doped GFET is improved while comparing with undoped GFET and promises highly desirable linearity requirement in analog/RF applications.

An Extended-Gate Ion-Sensitive Field-Effect Transistor with CMOS Technology-Intrinsic TiN Sensing Layer

The extended-gate ion-sensitive field-effect transistor (EGISFET) has promising potentials in chemical and biological sensing due to flexibility for array arrangement, less light-sensitivity, and compatibility with CMOS standard fabrication process [1-2]. An EGISFET is consisted of a MOSFET and a floating-gate structure separated from analyte solutions by a sensing layer. Because charges adjacent to the sensing layer change the floating-gate potential, the channel current of the EGISFET can be modulated through the electrical field effect. In a general CMOS process, the EGISFET can be achieved by using metal/VIA/polysilicon layers as the extended gate material and the passivation nitride layer on top of the metal as the sensing layer. For the EGISFET operation, a solution gate voltage is provided in the analyte solution and a capacitive voltage divider can be obtained based on a series connection of the electrical double layer capacitance (CEDL), the sensing layer capacitance (CS) and the gate oxide capacitance (COX). Due to the capacitive coupling nature, a higher CS/(CS+COX) ratio can have a larger part of solution gate voltage transferred to COX, and thus can have a higher EGISFET transconductance [3], which promises a better sensing response, e.g. channel-current change for a given charge change. However, CS is decreasing because of scaling down for realizing high spatial resolution sensing array. Then EGISFETs become less sensitive due to a weaker capacitive coupling.In order to ameliorate this scaling effect, we developed a TiN-EGISFET based on a CMOS 0.35 mm standard fabrication process. Instead of using the 1-2 mm thick passivation/intermediate dielectric layer as the sensing layer, we took advantage of an intrinsic extra-thin TiN layer within the VIA structure as the sensing layer. To expose the TiN layer, the metal/VIA layout was placed in a special manner to form a hanging micro-structure after a one-step wet etching. Followed by sonication, the micro-structure was broken at a mechanical weak point, e.g. the metal/VIA interface, and the ultra-thin TiN was successfully exposed. To have a control group, a traditional EGISFET was also implemented on the same chip. In the EGISFET measurement, a Ag/AgCl electrode was used to provide solution gate voltage, and the electric characteristic curve for each device was measured in pH solutions with different values.Compared to the traditional EGISFET occupying the same chip area, transconductance for the TiN-exposed EGISFET was improved up to 240%. This enhancement is possibly attributed to the conductivity and chemical stability of TiN, which make CS in the TiN-exposed region disappeared, only left CEDL and COX in series. As a result, a larger portion of solution gate voltage is dropped across COX because CEDL>>COX. Furthermore, the pH sensitivity of TiN-exposed EGISFET reaches 51 mV/pH without obvious hysteresis and drift (Figure 1). This is also supported by the previous literatures [4-5]. At 0.5V overdrive voltage, the current variation of TiN-exposed EGISFET is -9.12 mA/pH, which is 275% as high as that of the traditional EGISFET (Figure 2). These results suggest that a TiN-exposed EGISFET with a smaller footprint can possess the same sensitivity of a traditional EGISFET with a larger footprint.In conclusion, we developed a method to fabricate EGISFETs with TiN sensing layers in a commercialized CMOS process. This is the first time to have the in-situ TiN EGISFET in the CMOS process without extrinsic TiN deposition. This method can be employed to realize EGISFETs with higher density in a given area without sacrificing sensitivity, thus potentially beneficial to the development of high performance and high spatial resolution ISFET sensing array.

CMOS RF Switch With Fast Discharge Feature

A radio-frequency (RF) switch featuring a circuit for fast discharge of the gate oxide capacitance is presented in this letter. Two auxiliary transistors are added between the gate and source/drain terminals of the main switch. They are brought into the ON state for a short time at the beginning of the switching transient, discharging the gate of the main transistor, and speeding up the switching process. An integrated circuit implementing the proposed concept based on a large shunt switch has been designed and fabricated in Infineon 130-nm bulk-CMOS RF-switch technology. The measurements have demonstrated improvement in switching time (defined as the time between the control signal trigger edge and 90% of the target RF amplitude) of above 50% with no penalty in RF performance comparing to the conventional switch without discharge feature. The measured OFF-state insertion loss and ON-state isolation at 824 MHz were 0.12 and 27.2 dB, respectively.

Graphene Mobility Dependence on the Resistivity of Si Wafer

Graphene field effect transistors (GFETs) are typically benchmarked based on their field effect mobility. Constant mobility model proposed by Kim1 et.al is extensively used to derive this mobility parameter by directly fitting the transfer curves of graphene devices. Various methodologies were suggested to supplant and improve this existing mobility model. Among them Zhang2 et.al suggested the need for using measured gate oxide capacitance in order to extract mobility for top-gated GFETs. One of the commonly overlooked features, in the case of back gated GEFTs is the dopant concentration or the resistivity of Si substrate used. Herein, we explore the dependence of graphene carrier mobility on the induced carrier concentration and depletion capacitance of underlying Si substrate. Si with resistivities 0.01-0.02 Ω-cm and 0.001-0.005 Ω-cm were used to grow 10 nm thermal SiO2. GFETs were fabricated using CVD graphene on top of this thermal oxide substrate and the corresponding transfer curves are co-related with the capacitance density measured from corresponding MOSCAP structure. Detailed carrier mobility extraction and results are presented.(1) Kim, S.; Nah, J.; Jo, I.; Shahrjerdi, D.; Colombo, L.; Yao, Z.; Tutuc, E.; Banerjee, S. K. Realization of a High Mobility Dual-Gated Graphene Field-Effect Transistor with Al2O3 Dielectric. Appl. Phys. Lett. 2009, 94 (6). https://doi.org/10.1063/1.3077021.(2) Zhang, Z.; Xu, H.; Zhong, H.; Peng, L. M. Direct Extraction of Carrier Mobility in Graphene Field-Effect Transistor Using Current-Voltage and Capacitance-Voltage Measurements. Appl. Phys. Lett. 2012, 101 (21). https://doi.org/10.1063/1.4768690.

Extraction Technique for Flat Band Voltage Using Multi-Frequency C – V Characteristics in Amorphous InGaZnO Thin-Film-Transistors

An extraction technique for flat band voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> ) in an amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) using the frequency-independent C - V relationship which is taken from the measured multi-frequency C - V characteristics, is proposed. The proposed method comprises the consideration of multiple physical parameters for accurate VFB extraction, including the sub-gap density of states, doping concentration, gate oxide capacitance, and series resistance. The method was verified by comparing both the measured current-voltage characteristics and the extracted V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> value with the technology computer-aided design simulation results. Moreover, we confirmed the versatility of the method by extracting VFB from devices with different oxygen contents. The proposed physical-based technique showed better accuracy and compatibility with amorphous oxide semiconductor (AOS) TFTs compared with classical empirically based methods. We believe that our technique is useful for the experimental design and optimization of the gate metal-dielectric-AOS stack for highperformance AOS TFTs.

Uniformity of Gate Dielectric for I/O and Core HK/MG pMOSFETs with Nitridation Treatments

Uniformity consideration in integrated-circuit manufacturing is an impressive task, especially in the field of nano-node semiconductors. The use of high-dielectric-constant (high-K) materials to promote drive current in deep nano-node devices is also increasing. One solution involves enhancing the quality of the high-K dielectric layer as a gate dielectric with nitridation treatment. This study combines the aforementioned concerns in deep nano-node manufacturing and demonstrates their relationship. Given the electrical measurement of the wafers treated with decoupled plasma nitridation (DPN), a few desired key parameters, including drive current (IDS), threshold voltage (Vth), gate oxide capacitance per area (Cox), subthreshold swing (SS), and interface state density, in the design of p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) are observed. A uniformity comparison with different DPN processes is also performed, and the uniformity of the gate dielectric in input/output and core zones is discussed. Based on the uniformity distribution, lower SS values are obtained by adopting the low-temperature nitridation treatment after high-K dielectric deposition. The increased nitrogen concentration decreases the deviation, thereby indicating improved uniformity of SS values.

An Extended-Gate Ion-Sensitive Field-Effect Transistor with CMOS Technology-Intrinsic TiN Sensing Layer

The extended-gate ion-sensitive field-effect transistor (EGISFET) has promising potentials in chemical and biological sensing due to flexibility for array arrangement, less light-sensitivity, and compatibility with CMOS standard fabrication process [1-2]. An EGISFET is consisted of a MOSFET and a floating-gate structure separated from analyte solutions by a sensing layer. Because charges adjacent to the sensing layer change the floating-gate potential, the channel current of the EGISFET can be modulated through the electrical field effect. In a general CMOS process, the EGISFET can be achieved by using metal/VIA/polysilicon layers as the extended gate material and the passivation nitride layer on top of the metal as the sensing layer. For the EGISFET operation, a solution gate voltage is provided in the analyte solution and a capacitive voltage divider can be obtained based on a series connection of the electrical double layer capacitance (CEDL), the sensing layer capacitance (CS) and the gate oxide capacitance (COX). Due to the capacitive coupling nature, a higher CS/(CS+COX) ratio can have a larger part of solution gate voltage transferred to COX, and thus can have a higher EGISFET transconductance [3], which promises a better sensing response, e.g. channel-current change for a given charge change. However, CS is decreasing because of scaling down for realizing high spatial resolution sensing array. Then EGISFETs become less sensitive due to a weaker capacitive coupling.In order to ameliorate this scaling effect, we developed a TiN-EGISFET based on a CMOS 0.35 μm standard fabrication process. Instead of using the 1-2 μm thick passivation/intermediate dielectric layer as the sensing layer, we took advantage of an intrinsic extra-thin TiN layer within the VIA structure as the sensing layer. To expose the TiN layer, the metal/VIA layout was placed in a special manner to form a hanging micro-structure after a one-step wet etching. Followed by sonication, the micro-structure was broken at a mechanical weak point, e.g. the metal/VIA interface, and the ultra-thin TiN was successfully exposed. To have a control group, a traditional EGISFET was also implemented on the same chip. In the EGISFET measurement, a Ag/AgCl electrode was used to provide solution gate voltage, and the electric characteristic curve for each device was measured in pH solutions with different values.Compared to the traditional EGISFET occupying the same chip area, transconductance for the TiN-exposed EGISFET was improved up to 240%. This enhancement is possibly attributed to the conductivity and chemical stability of TiN, which make CS in the TiN-exposed region disappeared, only left CEDL and COX in series. As a result, a larger portion of solution gate voltage is dropped across COX because CEDL>>COX. Furthermore, the pH sensitivity of TiN-exposed EGISFET reaches 51 mV/pH without obvious hysteresis and drift (Figure 1). This is also supported by the previous literatures [4-5]. At 0.5V overdrive voltage, the current variation of TiN-exposed EGISFET is -9.12 mA/pH, which is 275% as high as that of the traditional EGISFET (Figure 2). These results suggest that a TiN-exposed EGISFET with a smaller footprint can possess the same sensitivity of a traditional EGISFET with a larger footprint.In conclusion, we developed a method to fabricate EGISFETs with TiN sensing layers in a commercialized CMOS process. This is the first time to have the in-situ TiN EGISFET in the CMOS process without extrinsic TiN deposition. This method can be employed to realize EGISFETs with higher density in a given area without sacrificing sensitivity, thus potentially beneficial to the development of high performance and high spatial resolution ISFET sensing array.

Compact device modelling of interface trap charges with quantum capacitance in MoS2-based field-effect transistors

An effective way to obtain interface trap density in transition metal dichalcogenide field-effect transistors (FETs) via compact device modelling is presented in this study. A computationally efficient model is utilised to evaluate the interface trap charges in a MoS2-based FET device. This model improves the accuracy of the computed surface potential, which is affected by trap charges. The existence of trap states on the interface level can be confirmed by studying the capacitance versus gate voltage () relationship. Most of the previously proposed models ignore the effect of the quantum capacitance when predicting the electrical performance of MoS2-FETs. The electrical performance of a metal-oxide-semiconductor FET with a two-dimensional (2D) molybdenum disulphide (MoS2) channel that introduces a quantum capacitance by including a gate is evaluated. The gate quantum capacitance in parallel with the interface trap capacitance is a second capacitance in series with the gate oxide capacitance and MoS2 capacitance This research explores the process of evaluating the interface trap density from published experimental data of MoS2-based FETs. Using the evaluated trap density values, the device parameters are calculated by considering the relative permittivity of the dielectric hafnium oxide (HfO2) layer, surface potential, interface trap charge and interface trap capacitance Finally, the calculated and experimental data are compared through the normalised root-mean-square deviations (RMSD) to validate the accuracy of the model.

Modeling of Fringing Capacitances of Ion-Implanted Double-Gate Junctionless FETs Using Conformal Mapping

This article reports an analysis of the fringing capacitances of an ion-implanted double-gate (DG) junctionless (JL) field-effect transistors (FETs). The actual nonintegrable Gaussian function of the ion-implanted channel has been replaced by an integrable Gaussian-like vertical channel doping profile to model the fringing capacitances of the DG JLFET. The boundary conditions for the source and drain depletion regions of the uniformly doped channel has been modified according to the nonuniformly doped channel using the conformal mapping technique. In this method, the gate-oxide capacitance is transformed to the source and drain fringing capacitances using an empirical multiple coefficient ${m}$ whose value is determined by matching the model result with the ATLAS TCAD simulation data for their best fitting. It is shown that unlike the uniformly doped device, the fringing capacitances are different for the front and back gates. Furthermore, the nonlinear bias-dependent potential profile along the channel leads to different fringing capacitances at the source and drain of the proposed device. The dependence of the fringing capacitances (and ${m}$ ) on the doping profile and bias conditions are investigated in detail. Accordingly, analytical expressions for the fringing capacitances are extracted. The model results are verified by the TCAD simulations.