Gate Noise Research Articles

Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier

Taking a velocity saturation effect and a carrier heating effect in the gradual channel region, complete thermal noise modeling of short-channel MOSFETs including the induced gate noise and its correlation coefficients is presented and verified extensively with experimentally measured data. All of the four noise models have excellently predicted experimental data with maximal error less than 10% for the deep-submicron MOSFETs. Using these models and a simultaneous matching technique for both optimal noise and power, a low noise CMOS amplifier optimized for 5.2-GHz operation has been designed and fabricated. Experiments using an external tuner show that both NF/sub 50/ and NF/sub min/ are very close to 1.1 dB, which is an excellent figure of merit among reported LNAs.

Effect of Induced Gate Noise at Zero Drain Bias in Field-Effect Transistors

According to classical theories, a MOS transistor with zero source-to-drain voltage behaves like a passive resistor exhibiting channel thermal noise and the effect of induced gate noise vanishes. Here, we show that the effect of induced gate noise persists as conductance fluctuations even under these "equilibrium" conditions without disturbing the Nyquist relationship governing the channel thermal noise.

Controlled phase gate for solid-state charge-qubit architectures

We describe a mechanism for realizing a controlled phase gate for solid-state charge qubits. By augmenting the positionally defined qubit with an auxiliary state, and changing the charge distribution in the three-dot system, we are able to effectively switch the Coulombic interaction, effecting an entangling gate. We consider two architectures, and numerically investigate their robustness to gate noise.

Reduced Impact of Induced Gate Noise on Inductively Degenerated LNAs in Deep Submicron CMOS Technologies

Reduced Impact of Induced Gate Noise on Inductively Degenerated LNAs in Deep Submicron CMOS Technologies

Analytical Modeling of MOSFETs Channel Noise and Noise Parameters

Simple analytical expressions for MOSFETs noise parameters are developed and experimentally verified. The expressions are based on analytical modeling of MOSFETs channel noise, are explicit functions of MOSFETs geometry and biasing conditions, and hence are useful for circuit design purposes. Good agreement between calculated and measured data is demonstrated. Moreover, it is shown that including induced gate noise in the modeling of MOSFETs noise parameters causes /spl sim/5% improvement in the accuracy of the simple expressions presented here, but at the expense of complicating the expressions.

ON THE INFLUENCE OF SPACE-QUANTIZATION EFFECTS ON THE RF NOISE BEHAVIOUR OF DG MOSFETS

We present a particle-based Monte Carlo investigation of the high frequency noise behavior of a double gate MOSFET. The effective potential approach has been considered for the description of vertical quantum confinement of carriers within the channel. The intrinsic noise sources and the main circuital noise parameters are studied, together with the static and dynamic parameters, thus allowing to provide a full comprehension of the inner physics of the device and elucidating the consequences of quantum mechanical space-quantization effects (like charge repulsion from the gate-oxide boundaries). Results show that neglecting quantum phenomena leads to an important overestimation of gate capacitance and device transconductance and an underestimation of the final influence of induced gate noise (via the normalized parameter R) on the circuital noise parameters at RF and microwave frequency ranges.

2D ensemble Monte Carlo modelling of bulk and FD SOI MOSFETs: active layer thickness and noise performance

In this work, the RF and microwave noise performance of bulk and fully-depleted silicon-on-insulator (FD SOI) transistors with directly comparable topologies is investigated by means of an ensemble Monte Carlo simulator, and in the case of FD SOI devices, the influence of varying the active layer thickness is also studied. Intrinsic noise sources are calculated and analysed, and important figures of merit such as NFmin or Rn are also determined and evaluated. Moreover, a microscopic understanding of the noise phenomena is achieved, which is essential for the optimization of the transistors. FD SOI devices show a reduced influence of induced gate noise and drain noise as compared to the bulk transistor due to the minor influence of phonon scattering and energetic carriers at the pinch-off region. Whereas reducing the active layer thickness minimizes the effect of hot carriers in the noise parameters, it can lead to a degradation of other important high-frequency figures of merit such as gm or fT.

Non-quasi-static (NQS) thermal noise modelling of the MOS transistor

A non-quasi-static (NQS) thermal noise model of the MOS transistor is presented that is valid in all modes of operation, from weak to strong inversion, and up to frequencies which are near or above the NQS cut-off frequency. It is shown that in addition to the well known induced gate noise (IGN) there is also an induced substrate noise that is generated and that the source and drain noises are also affected. All prior publications on the subject only deal with IGN in the strong inversion regime. It is shown that significant differences are obtained for moderate and weak inversion operation. A brief review is given of the NQS model valid in all modes of operation. The general thermal noise model using four noisy current sources is described. The power spectral and cross-power spectral densities of these noise sources are computed. A first-order approximation is then derived and compared to the complete model. It is shown that the correlation coefficient between the drain and the gate noise is always null in triode (VD=VS), and varies in saturation between j 0.6 in weak inversion to j 0.4 in strong inversion. To the authors' knowledge, it is the first time that a complete HF thermal noise model of the MOST is presented, that is valid in all modes of inversion and up to and above the NQS cut-off frequency. The impact of this complete NQS noise model on RF-CMOS circuit design is illustrated by two examples.

Overview of the impact of downscaling technology on 1∕f noise in p-MOSFETs to 90 nm

An overview of theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependencies of 1/f noise in all conduction regimes are summarised. Novel experimental studies on 1/f noise in MOS transistors are presented with special emphasis on p-channel transistors from 90 nm CMOS technology. In addition to the noise in the drain terminal, the gate current noise is investigated because the gate insulator is very thin and significant gate leakage current appears at high gate biases. In the subthreshold regime, the drain current noise agrees with the ΔN model, whereas in strong inversion the evolutions of the noise level can be described by Hooge's empirical relation. The gate current noise shows 1/f and white noise components. The white noise is very close to shot noise and the 1/f noise component is almost a quadratic function of the gate leakage current. Coherence measurements reveal that the increase of drain noise at high gate biases can be attributed to tunnelling effects in the gate insulator. Both the input-referred (gate) noise and the slow oxide trap density can be used as a figure of merit of the low-frequency noise in MOSFETs.

Reduced Impact of Induced Gate Noise on Inductively Degenerated LNAs in Deep Submicron CMOS Technologies

Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the-art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used.

Low-frequency noise and radiation response of buried oxides in SOI nMOS transistors

The back channel low-frequency noise of 1.2 /spl mu/m/spl times/2.3 /spl mu/m SOI nMOS transistors with a buried oxide thickness of 170 nm was measured as a function of frequency, back gate bias V/sub bg/ and temperature T. For a temperature range of 85/spl les/T/spl les/320 K, noise measurements were performed at frequencies of 0.3/spl les/f/spl les/1 kHz with top gate bias V/sub bg/=0 V and V/sub bg/-V/sub bg-th/=4 V, where V/sub bg-th/ is the back gate threshold voltage. The temperature and frequency dependences of the 1/f noise of back channel SOI nMOS transistors show thermally activated charge exchange between the Si channel and defects in the buried oxide. Comparison is made with the Dutta and Horn model of 1/f noise. Devices on one particular wafer appear to show a mixture of 1/f noise and noise with a higher frequency exponent at low temperatures. Little change is observed in back gate noise with irradiation for the devices and irradiation conditions studied. This is probably due to large preirradiation defect densities in the buried oxides.

Submillisecond Precision of the Input-Output Transformation Function Mediated by Fast Sodium Dendritic Spikes in Basal Dendrites of CA1 Pyramidal Neurons

The ability of cortical neurons to perform temporally accurate computations has been shown to be important for encoding of information in the cortex; however, cortical neurons are expected to be imprecise temporal encoders because of the stochastic nature of synaptic transmission and ion channel gating, dendritic filtering, and background synaptic noise. Here we show for the first time that fast local spikes in basal dendrites can serve to improve the temporal precision of neuronal output. Integration of coactivated, spatially distributed synaptic inputs produces temporally imprecise output action potentials within a time window of several milliseconds. In contrast, integration of closely spaced basal inputs initiates local dendritic spikes that amplify and sharpen the summed somatic potential. In turn, these fast basal spikes allow precise timing of output action potentials with submillisecond temporal jitter over a wide range of activation intensities and background synaptic noise. Our findings indicate that fast spikes initiated in individual basal dendrites can serve as precise "timers" of output action potentials in various network activity states and thus may contribute to temporal coding in the cortex.

A unified model for high-frequency current noise of MOSFETs

At high frequency, the MOSFET drain current noise and induced gate noise are generally accepted as dominated by the thermal noise as the MOSFET is operating in strong inversion region. However, controversy exists about the high-frequency noise in subthreshold region. This paper proposes unified high-frequency drain current noise and induced gate noise models valid in strong-, moderate- and weak-inversion regions. These models are necessary for the completeness of device noise model and helpful for low-noise high-frequency amplifier design with deep submicrometer technologies with MOSFETs operating in moderate inversion region.

Intrinsic noise equivalent-circuit parameters for AlGaN/GaN HEMTs

Intrinsic noise sources and their correlation in gallium-nitride high electron-mobility transistors (HEMTs) are extracted and studied. Microwave noise measurements have been performed over the frequency range of 0.8-5.8 GHz. Using measured noise and scattering parameter data, the gate and drain noise sources and their correlation are determined using an equivalent-circuit representation. This model correctly predicts the frequency-dependent noise for two devices having different gate length. Three noise mechanisms are identified in these devices, namely, those due to velocity fluctuation, gate leakage, and traps.

High frequency noise in fully overlapped lightly doped drain MOSFETs

The high frequency noise of fully overlapped lightly doped drain ( FOLD) MOSFETs incorporating the field dependent mobility and the bias dependent series resistance is predicted. This includes the thermal noise and the induced gate noise. The results so obtained for effective current noise gain are compared with the simulated data of short channel LDD MOSFETs and are in good agreement. At frequencies much below the cut-off frequency, the induced gate noise is just 1% or even less of the drain noise. The effective current noise gain in FOLD and LDD MOSFETs is compared and shows that thermal noise increases while gate induced noise decreases with the decrease in channel length.

Low-frequency noise in III–V high-speed devices

Low-frequency noise results obtained for III-V pseudomorphic high electron mobility transistors (PHEMTs) and heterojunction bipolar transistors (HBTs) are reviewed. The experimental noise set-up is presented and the equivalent circuits of devices including noise sources are established. Excess low-frequency noise comprises 1/f and Lorentzian-type components. An overview of gate and drain low-frequency noise of heterostructure field-effect transistors is provided in the paper. Different activation energy values attributed to traps are also reported. The authors concentrate on the 1/f noise of GaAs-based PHEMTs. The results are analysed with the help of an equivalent circuit deduced from a study of the conduction. The fundamental 1/f noise sources are analysed and modelled according to the different bias range. With regard to HBTs, results for AlGaAs/GaAs, GaInP/GaAs and InP/InGaAs are used for comparison. The effect of the DX centre on the different materials is investigated. The analysis against the bias of the 1/f noise level of the current spectral density referred to the input Si/sub n/ gives information on the origin of the noise. The experimental bias dependencies of Si/sub n/ are compared to those available in the literature and are discussed. The importance of electrical passivation for the improvement of noise is investigated. An analysis of noise against emitter area and emitter perimeter is undertaken for an accurate location of noise sources.

Flicker noise in gate overlapped polycrystalline silicon thin-film transistors

A study of the noise performance of gate overlapped polycrystalline silicon thin-film transistors (TFTs) is presented. Low-frequency noise measurements were carried out on n- and p-type samples fabricated by excimer laser crystallization. It is shown that the carrier number fluctuation model applies not only to n-type but also to p-type devices. The density of oxide traps was extracted from the noise measurements and was of the order of 10/sup 18/-10/sup 19/ eV/sup -1/ cm/sup -3/.

RF Noise in a Short-Channel n-MOSFET: A Monte Carlo Study

We present a complete Monte Carlo analysis of transport and RF noise in a short-gate n-MOSFET. Short-channel effects are observed in the static characteristics. Velocity overshoot of electrons in the channel, as well as the appearance of hot carriers are detected. P, R and C noise parameters show an important increase in their values with respect to the long-channel theory predictions due to the presence of hot electrons. NF min is also calculated; results confirm the importance of induced gate noise on the behaviour of this parameter.

MOSFET MODELING FOR RF IC DESIGN

High frequency (HF) AC and noise modeling of MOSFETs for radio frequency (RF) integrated circuit (IC) design is discussed. Equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model. Modeling of the intrinsic device and the extrinsic components is disussed by accounting for the important physical effects at both DC and HF. Based on the Y-parameter analysis of the equivalent circuit model, procedures of the HF model parameter extraction are also developed. With the discussed approaches, a sub-circuit RF model incorporating the modeling of parasitics is presented. This model is compared with the measured data for both y parameter and fr characteristics. Good model accuracy is achieved against the measurements for a 0.25μm RF CMOS technology. The non-quasi-static (NQS) modeling issue has also been discussed by using the BSIM3v3 based RF model to predict the HF characteristics of devices with serious NQS effects. Further, noise modeling issues are discussed by analyzing the theoretical and experimental results in both the flicker noise and thermal noise modeling. Modeling efforts to in corporate new physical effects are needed to predict better the flicker noise characteristics in today's MOSFETs. A detailed analysis of the HF noise parameters has been conducted to establish the relationship between the noise parameters preferred by circuit designers and obtained by HF noise measurement. Analytical calcultion of the noise parameters has also been discussed to understand the noise characteristics with/without some parasitic components such as gate and substrate resistances as well as the influence of the induced gate noise. The HF noise predictivities of several HF noise models are also examined with the measured data. The results show that the BSIM3v3 based RF model can predict the channel thermal noise better than the other models.

RF CMOS Noise Characterization and Modeling

This paper presents a through description of radio frequency (RF) noise characterization and modeling of CMOS transistors. It begins with the definition of the four noise parameter of a two-port network - minimum noise figure (NFmin), equivalent noise resistance (Rn), optimized source impedance (Ropt) and optimized source reactance (Xopt). These four parameters are used in device characterization and it is shown how they can be calculated by using the noise two-port network theory and a circuit simulator. Then two de-embedding procedures are discussed in detail for noise and scattering parameter de-embedding to get rid of the parasitic effects from the probe pads and interconnections in the device-under-test (DUT). Ideally there is no frequency and geometry limitation for the method based on a cascade configuration. Methods to directly extract the channel noise, induced gate noise and their correlation from the RF and noise measurements are developed and the extracted noise sources as a function of frequency and bias condition for different channel lengths a presented. Some design consideration for the design of low noise circuits - how to select the device size, choice of DC bias conditions and design device layout, are presented. Finally, some published noise models for the channel noise, induced gate noise and their correlation are discussed.