Gate Length CMOS Devices Research Articles

Physical and technological limitations of NanoCMOS devices to the end of the roadmap and beyond

Since the end of the last millenium, the microelectronics industry has been facing new issues as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS device structures or if new device architectures are implemented. Innovations in the electronics history have been possible because of the strong association between devices and materials research. The demand for low voltage, low power and high performance are the great challenges for the engineering of sub 50 nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power consumption are reviewed. The issues in the field of gate stack, channel, substrate, as well as source and drain engineering are addressed. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. By introducing new materials (Ge, diamond/graphite carbon, HiK, ...), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating also new disruptive devices. For example, the association of C-diamond with HiK, as a combination for new functionalized Buried Insulators, will bring new ways of improving short channel effects and suppress self-heating. Because of the low parasitics required to obtain high performance circuits, alternative devices will hardly compete against logic CMOS.

CMOS DEVICES ARCHITECTURES AND TECHNOLOGY INNOVATIONS FOR THE NANOELECTRONICS ERA

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials ( Ge , diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

Devices architectures and materials for nanoCMOS at the end of the roadmap and beyond

Historically, innovations have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub-50 nm gate length CMOS devices. We point out the main issues to address in order to investigate and push the limits of CMOS technology. The alternative architectures allowing one to increase device drivability and reduce power are reviewed. Among the materials options to be integrated, high- k gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. New architectures and options are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials (Ge, diamond/graphite Carbon, high- k, etc.), Si-based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. Functionality of devices in the range of 5 nm channel length has been demonstrated showing that CMOS technology could still be used in the future. We will have to manage the implementation of new materials and device architecture options compatible with the control of low power dissipation and short channel effects together with high performance.

Characterization of 1.9- and 1.4-nm Ultrathin Gate Oxynitride by Oxidation of Nitrogen-implanted Silicon Substrate

For gate oxide thinned down to 1.9 and 1.4 nm, conventional methods of incorporating nitrogen (N) in the gate oxide might become insufficient in stopping boron penetration and obtaining lower tunneling leakage. In this paper, oxynitride gate dielectric grown by oxidation of N-implanted silicon substrate has been studied. The characteristics of ultrathin gate oxynitride with equivalent oxide thickness (EOT) of 1.9 and 1.4 nm grown by this method were analyzed with MOS capacitors under the accumulation conditions and compared with pure gate oxide and gate oxide nitrided by N/sub 2/O annealing. EOT of 1.9- and 1.4-nm oxynitride gate dielectrics grown by this method have strong boron penetration resistance, and reduce gate tunneling leakage current remarkably. High-performance 36-nm gate length CMOS devices and CMOS 32 frequency dividers embedded with 57-stage/201-stage CMOS ring oscillator, respectively, have been fabricated successfully, where the EOT of gate oxynitride grown by this method is 1.4 nm. At power supply voltage V/sub DD/ of 1.5 V drive current Ion of 802 /spl mu/A//spl mu/m for NMOS and -487 /spl mu/A//spl mu/m for PMOS are achieved at off-state leakage I/sub off/ of 3.5 nA//spl mu/m for NMOS and -3.0 nA//spl mu/m for PMOS.

First-principles Calculation of Electron Mobilities in Ultrathin SOI MOSFETs

ABSTRACTUltrathin silicon-on-insulator (UTSOI) technology1 has emerged as a key candidate for sub-100nm gate length CMOS devices. Recent experiments have characterized MOSFETs with silicon channels as thin as 1nm (four atomic layers of silicon),2,3 and found them to be well-behaved electrically. Quantum effects are important to the electron transport in such devices, and the penetration of the electron wavefunction into the gate oxide introduces new scattering mechanisms. We introduce here a novel method for first-principles calculation of electron mobilities in ultrathin SOI channels, including surface roughness and defect scattering. The electronic structure and scattering potentials are calculated with Density Functional Theory in the Local Density Approximation (DFT-LDA), and the mobility is calculated through Green's functions. The method requires little computational effort beyond that of the DFT-LDA calculations, and allows the calculation of temperature- and carrier concentration-dependent mobilities. Since the silicon-oxide interface is treated at the atomic-scale, the mobility contributions of different defects (e.g. suboxide bonds, oxide protrusions) and impurities (e.g. nitrogen, hydrogen) can be calculated separately, giving a precise physical picture of channel electron transport.

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I/sub g/ and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/=0.85 V (at I/sub off/=100 nA//spl mu/m) were achieved and they are the best values for 35 nm gate length CMOS reported to date.

0.25 μm gate length CMOS devices for cryogenic operation

Under cryogenic operation, a low V/sub th/ realizes a high speed performance at a greatly reduced power-supply voltage, which is the most attractive feature of Cryo-CMOS. It is very important in sub-0.25 /spl mu/m Cryo-CMOS devices to reconcile the miniaturization and the low V/sub th/. Double implanted MOSFET's technology was employed to achieve the low V/sub th/ while maintaining the short channel effects immunity. We have investigated both the DC characteristics and the speed performance of 0.25 /spl mu/m gate length CMOS devices for cryogenic operation. The measured transconductances in the saturation region were 600 mS/mm for 0.2 /spl mu/m gate length n-MOSFET's and 310 mS/mm for 0.25 /spl mu/m gate length p-MOSFET's at 80 K. The propagation delay time in the fastest CMOS ring oscillator was 22.8 ps at V/sub dd/=1 V at 80 K. The high speed performance at extremely low power-supply voltages has been experimentally demonstrated. The speed analysis suggests that the sub-l0 ps switching of Cryo-CMOS devices will be realized by reducing the parasitic capacitances and through further miniaturization down to 0.1 /spl mu/m gate length or below. >

High-performance 0.10- mu m CMOS devices operating at room temperature

The authors have fabricated 0.10- mu m gate-length CMOS devices that operate with high speed at room temperature. Electron-beam lithography was used to define 0.10- mu m polysilicon gate patterns. Surface-channel type p- and n-channel MOSFETs were fabricated using an LDD structure combined with a self-aligned TiSi/sub 2/ process. Channel doping was optimized so as to suppress punchthrough as well as to realize high transconductance and low drain junction capacitance. The fabricated 0.10- mu m CMOS devices have exhibited high transconductance as well as a well-suppressed band-to-band tunneling current, although the short-channel effect occurred somewhat. The operation of a 0.10- mu m gate-length CMOS ring oscillator has been demonstrated. The operation speed was 27.7 ps/gate for 2.5 V at room temperature, which is the fastest CMOS switching ever reported.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>