Work Function Of Gate Electrode Research Articles

Effect of nitrogen content in HfxTayN metal gate on work function and thermal stability of advanced metal-oxide-semiconductor devices

The effects of nitrogen composition in HfxTayN metal-gate electrodes and postmetal annealing (PMA) treatment on the electrical properties of metal-oxide-semiconductor (MOS) devices were investigated in this work. The work function of HfxTayN gate electrodes can be adjusted by incorporating various nitrogen contents. It is found that the HfxTayN metal gate with higher nitrogen content can achieve better electrical characteristics in terms of leakage current and reliability while with only a slight increase in equivalent-oxide-thickness value. The face that only slight variation on electrical characteristics of MOS device with HfxTayN gate electrodes is observed after various PMA temperatures designates the excellent thermal stability of HfxTayN gate electrodes. The present study indicates that HfxTayN is a promising metal-gate-electrode material for advanced MOS devices.

Tantalum carbonitride electrodes and the impact of interface chemistry on device characteristics

The intent of this research is to understand the role of interface chemistry on the effective work function and device characteristics of metal gate electrodes on hafnium dioxide (HfO2) gate dielectrics in metal oxide semiconductor field effect transistors. Since multiple factors, including crystal structure, preferred orientation, chemical composition, interface bonding, and reactions or interdiffusions, impact the effective work function, solid-solution carbonitrides of tantalum (TaCxN1−x) have been studied in an attempt to isolate the role of interface chemistry on the effective work function. Tantalum carbonitride films have been carefully deposited with similar Ta∕(C+N) ratios to understand how the substitution of N for C on the octahedral interstice in a face-centered-cubic tantalum lattice impacts device performance. Results indicate that the effective work function and device threshold voltage are reduced when the less electronegative carbon atom is substituted for the more electronegative nitrogen atom. This result is in qualitative agreement with the known relationship between metal electronegativity and effective work function and demonstrates the important role that sublattice elements in binary metal compounds have on the effective work function of the gate electrode.

Temperature dependence of the work function of ruthenium-based gate electrodes

The effect of device fabrication temperature on the work function of ruthenium (Ru) metal gate and its bilayers was investigated. The work function shows strong temperature dependence when Ru electrodes are deposited on silicon oxide, SiO2, but not on hafnium silicates (HfSiOx). Specifically, the work function of Ru on SiO2 increased from 4.5 eV at 500 °C to 5.0 eV at 700 °C. On further annealing to 900 °C or higher, the work function dropped to about 4.4 eV. In the case of HfSiOx, the work function of Ru changed by less than 100 mV over the same temperature range. Identical temperature dependence was observed using hafnium (Hf)/Ru and tantalum (Ta)/Ru bilayers. However, the peak values of the work function decreased with increasing Hf/Ru and Ta/Ru thickness ratios. Materials analysis suggests that these trends are driven by interactions at the Ru metal gate–dielectric interface.

Evaluation of titanium silicon nitride as gate electrodes for complementary metal-oxide semiconductor

The effect of deposition temperature and film thickness on the work function of TiSiN gate electrodes has been studied. It is shown that the work function of TiSiN can be tuned from 4.28–4.74eV on SiO2, 4.40–4.79eV on HfO2, and 4.44–4.83eV on HfSiOx. For high-k dielectrics, the work function can be tuned by 200meV on each side of the band gap, making it a suitable electrode for fully depleted silicon-on-insulator devices. Furthermore, TiSiN deposition at high temperature increases the work function to 4.87eV while Si implantation increases it to 4.93eV, making TiSiN a good p-type metal candidate.

Investigation on the Work Function of Tungsten and Thermal stability of W/SiO2/Si, W/SiON/Si and W/HfO2/Si Gate Stacks

AbstractReplacement of poly-Si and SiO2with new gate electrode and high k gate oxide is an inevitable trend for next-generation CMOS integrated circuits. Therefore, work function (£Xm) of gate electrodes as well as the thermal stability and electrical behaviors of MOS capacitors should be understood. In this study, tungsten (W) is applied as the gate electrode and the gate dielectric materials are SiO2, SiON and HfO2. £Xm of W and electrical properties of the MOS structures are investigated. £Xm,measuredof W is calculated from the flat-band voltage (VFB) of MOS capacitors with dielectrics of various thicknesse. For W/SiO2/Si structure, the £Xm,measuredof W is 4.67 V; however, the £Xm,measuredof W in W/SiON/Si and W/HfO2/Si structures is 4.60 V and 4.84 V, respectively. The result means that the £Xm,measuredof W in W/HfO2/Si structures has extrinsic contributions to Fermi level pinning. The phase of as-deposited W is £]-W (or £]-W+£\-W) phase and transfers to £\-W+WO3 mix phase after annealing at 500°C in N2+H2 ambient for 30 min. The trapped charges and oxide charges of dielectric are reduced after annealing. However, the EOT of W/SiO2/Si increases significantly after annealing, indicating the thermal stability of this capacitor is poor.

Three-Layer laminated metal gate electrodes with tunable work functions for CMOS applications

This letter presents a novel technique for tuning the work function of a metal gate electrode. Laminated metal gate electrodes consisting of three ultrathin (/spl sim/1-nm) layers, with metal nitrides (HfN, TiN, or TaN) as the bottom and top layers and element metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO/sub 2/, followed by rapid thermal annealing annealing. Annealing of the laminated metal gate stacks at high temperatures (800/spl deg/C-1000/spl deg/C) drastically increased their work functions (as much as 1 eV for HfN-Ti-TaN at 1000/spl deg/C). On the contrary, the bulk metal gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated metal gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000/spl deg/C.

Ab initio study of metal gate electrode work function

The work function of metal multilayers and monolayers on bulk metals was studied using the first principle pseudopotential method within the local density approximation in order to find a way to modulate the work function of metal gate electrodes. Various multilayer stacks and bilayer stacks of two systems, Al–Pt and Al–Ni, were examined. It was found that two or three layers of the metal are enough to shift the work function to that of the surface metal. Also, it was found that even a submonolayer could affect the work function of the bulk metal significantly.

Metal Gate Work Function Engineering on Gate Leakage of MOSFETs

We present a systematic study of tunneling leakage current in metal gate MOSFETs and how it is affected by the work function of the metal gate electrodes. Physical models used for simulations were corroborated by experimental results from SiO/sub 2/ and HfO/sub 2/ gate dielectrics with TaN electrodes. In bulk CMOS results show that, at the same capacitance equivalent oxide thickness (CET) at inversion, replacing a poly-Si gate by metal reduces the gate leakage appreciably by one to two orders of magnitude due to the elimination of polysilicon gate depletion. It is also found that the work function /spl Phi//sub B/ of a metal gate affects tunneling characteristics in MOSFETs. It is particularly significant when the transistor is biased at accumulation. Specifically, the increase of /spl Phi//sub B/ reduces the gate-to-channel tunneling in off-biased n-FET and the use of a metal gate with midgap /spl Phi//sub B/ results in a significant reduction of gate to source/drain extension (SDE) tunneling in both n- and p-FETs. Compared to bulk FET, double gate (DG) FET has much lower off-state leakage due to the smaller gate to SDE tunneling. This reduction in off-state leakage can be as much as three orders of magnitude when high-/spl kappa/ gate dielectric is used. Finally, the benefits of employing metal gate DG structure in future CMOS scaling are discussed.

The characteristics of hole trapping in HfO2∕SiO2 gate dielectrics with TiN gate electrode

The characteristics of charge trapping during constant voltage stress in an n-type metal–oxide–semiconductor capacitor with HfO2∕SiO2 gate stack and TiN gate electrode were studied. We found that the dominant charge trapping mechanism in the high-k gate stack is hole trapping rather than electron trapping. This behavior can be well described by the distributed capture cross-section model. In particular, the flatband voltage shift (ΔVfb) is mainly caused by the trap filling instead of the trap creation [Zafar et al., J. Appl. Phys. 93, 9298 (2003)]. The dominant hole trapping can be ascribed to a higher probability for hole tunneling from the substrate, compared to electron tunneling from the gate, due to a shorter tunneling path over the barrier for holes due to the work function of the TiN gate electrode.

Effect of Boron Dose and Post-thermal Budget on Electrical Properties of MOS-Capacitors with a W / WN x / poly ­ Si1 − xGex Gate Stack

We investigated the effect of boron dosage and post-thermal budget on the electrical properties such as capacitance-voltage (C-V), gate leakage current-voltage and charge-to-breakdown of metal oxide semiconductor (CMOS) capacitors with gates stack. The C-V curve of the MOS-capacitors with the stack had a lower flatband voltage and showed less gate depletion effect (GDE), compared with that of the stack due to the decrease of gate electrode work function and the increase of dopant activation rate with the increase of Ge content, respectively. Although the curves of MOS-capacitors with gates stack exhibited similar behaviors regardless of Ge content, the beginning of conduction in the curves accelerated with the increase of Ge content due to the decrease of the gate electrode work function. The of gates stack was much higher than that of the gates stack due to the reduced boron penetration in the gate oxide. We also found that annealing temperatures between 800 and 850°C had no influence on the electrical properties of MOS capacitors with gates stack. © 2003 The Electrochemical Society. All rights reserved.

A low-temperature metal-doping technique for engineering the gate electrode of replacement metal gate CMOS transistors

This work describes a low-temperature metal annealing technique that can be a helpful tool for fabricating the gate electrode of replacement metal gate CMOS transistors. The goal of the technique is to form doped metal (TaSiN, TiSiN, TaCN, TaPN, etc.) to change the work function of the metal gate electrode. The low-temperature doping process was performed in an ambient containing the precursors of the dopants, including silane, phosphine, and carbon-rich organic precursors. Experiments have been conducted to incorporate dopants such as P, C, Si into TaN or TiN. The transistor and C-V data show the resultant doped metals are suitable materials for P- and N-MOSFETs by providing the right metal work function.

Nickel induced crystallization of α- Si gate electrode at 500 °C and MOS capacitor reliability

We present a study of MOS capacitor reliability when nickel (Ni) is used to crystallize a phosphorus-doped, amorphous silicon (/spl alpha/-Si)-gate electrode by metal-induced crystallization (MIC). The dopant in the gate electrode was also activated during the MIC. We report that there was an increase of about 0.1 eV in the gate electrode workfunction due to Ni. Through capacitance-voltage ( C-V), current-voltage (I-V) and charge-to-breakdown (Q/sub BD/) measurements, we show that the Ni MIC in the gate electrode does not degrade the MOS capacitor reliability.

Control of a Metal-Electrode Work Function by Solid-State Diffusion of Nitrogen

AbstractThe work function of a metal gate electrode has been adjusted with the introduction of nitrogen by solid-source diffusion from an over-stoichiometric TiN1+x layer. RBS measurements have shown that measurable concentrations of nitrogen can be diffused into a 10nm Ta layer at moderate anneal temperatures (>500°C), and that this concentration increases with temperature in the range 500-1000°C. Capacitance-voltage measurements have been carried out on 10nm tantalum layers on Al2O3. These measurements have indicated that the work function of tantalum changes by -0.08eV due to the presence of the over-stoichiometric TiN1+x covering layer during anneal (800°C/30”). Similar C-V measurements have been carried out on 10nm molybdenum layers on SiO2 and on Al2O3 dielectrics. These have shown that the work function of molybdenum is substantially different for metal stacks with the TiN1+x covering layer after a similar anneal. The work function changes by -0.52eV for molybdenum on SiO2 and by -1.1eV for molybdenum on Al2O3. The results suggest great potential for molybdenum as a candidate for a single-metal dual-work function approach to integrating metal gates into future CMOS technologies.

Impact of gate workfunction on device performance at the 50 nm technology node

The optimal gate electrode workfunction was determined for the 50 nm technology node using a simulation strategy that takes into account the impact of short-channel effects on device performance in uniformly doped and super-steep-retrograde doped channels in conventional and dynamic threshold operation. Classical device simulations suggest that the optimal workfunction is such that the gate Fermi level is 0.2 eV below (above) the conduction (valence) band edge of silicon for NMOS (PMOS) devices. However, when quantum mechanical effects are taken into account, the optimal workfunction is such that the gate Fermi level coincides with the conduction (valence) band edge. Midgap gates are not viable because the resulting short-channel effects are too severe. In a surrounding-gate transistor the optimal workfunction is attained when the gate Fermi level is 0.35 eV below (above) the conduction (valence) band edge in NMOS (PMOS) device. Midgap gates are not viable because the resulting threshold voltage is too high and cannot be reduced by lowering the substrate doping.

Avalanche electron injection in 4-nm Si/sub 3/N/sub 4//8-nm SiO/sub 2/ dielectric structure: turn-around phenomenon and Si-SiO/sub 2/ interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si/sub 3/N/sub 4/+8-nm SiO/sub 2/) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si/sub 3/N/sub 4/ interface) and subsequent trapping near the SiO/sub 2/-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO/sub 2/-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>