Gate Dielectric Reliability Research Articles

Demonstration of 800°C SiC MOSFETs for Extreme Temperature Applications

Silicon Carbide (SiC) enhancement mode MOS electronics offer several benefits for realizing analog, digital and mixed signal electronics, but limitations on gate dielectric reliability has limited the adoption of MOS in high temperature application. In this work, we report GE’s lateral SiC MOSFETs exceeding previously reported temperature capabilities for SiC MOSFETs with experimental results that have shown that >500°C operation of SiC MOSFETS is possible with >400 hours demonstrated at 620°C, and short-term functionality demonstrated to 800°C. The result shows that MOS-based SiC electronics can continue to be a viable choice for circuit implementations at extreme temperatures >600°C.

Ge-friendly gate stacks: Initial property and long-term reliability

This work presents specific exploration on the novel gate stack strategies for the intriguing Ge p-MOSFET, where high pressure oxidation (HPO) process is utilized for sufficient oxidation and thus fewer oxygen vacancies, while yttrium doping is developed to strengthen the dielectric bonding for higher ruggedness. Superior gate controllability and stability have been achieved correspondingly, where then detailed comparison on the gate dielectric reliability is conducted. The HPO based GeO2 gate stack exhibits larger susceptibility to the gate bias stress, and could even breakdown under negative bias, which has been attributed to the local bond breakage that facilitates the irreversible network change. The yttrium-doped GeO2, on the other hand, presents impressive ruggedness against gate bias stress. Based on detailed bond breakage analysis, cation-doping in GeO2 is suggested to be effective in enhancing the bond rigidness, promising for a wider safe operation range for the gate bias in Ge MOSFET.

The Effect of Diluted N2O Annealing Time on Gate Dielectric Reliability of SiC Metal-Oxide Semiconductor Capacitors and Characterization of Performance on SiC Metal-Oxide Semiconductor Field Effect Transistor

We performed dry oxidation on n-type silicon carbide (SiC), followed by annealing in diluted N2O, and subsequently fabricated n-type MOS structures. The study aimed to investigate the impact of different annealing times on the trap charges near the SiC/SiO2 interface and the reliability of the gate dielectric. Capacitance-voltage (C-V) and current-voltage (I-V) measurements of the n-type MOS revealed that increasing the annealing time with N2O effectively reduces the density of electron traps near the SiC/SiO2 interface, mitigates the drift in flat-band voltage and enhances the oxide breakdown field strength. However, excessive annealing time leads to an increase in the flat-band voltage drift of the MOS, resulting in premature oxide breakdown. Using the optimized annealing conditions, we fabricated n-type LDMOSFETs and obtained the threshold voltage (Vth), field-effect mobility (μFE) and specific on-resistance (Ron-sp) from the transfer curve (Id-Vg) and output curve (Id-Vd) measurements. The research findings provide valuable insights for the gate oxidation process of SiC.

Insight into gate dielectric reliability and stability of SiO2/GaN MOS devices

Gate dielectric reliability and stability of SiO2/GaN metal–oxide–semiconductor (MOS) capacitors were systematically investigated by means of area-dependent and time-dependent dielectric breakdown (TDDB) characteristics. It was found that, although high-temperature post-deposition annealing (PDA) that causes Ga diffusion in SiO2 gate dielectrics has only a minor impact on electrical properties of the SiO2/GaN interfaces, PDA at temperatures above 800 °C severely degrades dielectric reliability and stability of GaN MOS devices. Area dependences of time-zero and TDDB characteristics revealed the formation of local weak spots and generation of uniform charge trapping sites throughout the gate oxides depending on the PDA temperatures. Determinant factors for dielectric reliability of SiO2/GaN gate stacks and reasonable measures for improving their reliability and stability are discussed on the basis of the experimental findings.

Study of Asymmetric Cell Structure Tilt Implanted 4H-SiC Trench MOSFET

The reliability of gate dielectrics is one of the key issues in SiC Trench MOSFET. While reducing the gate oxide electric field in OFF state through dedicated shielding structures by various designs, JFET resistances are often introduced. In this letter, a new asymmetric cell structure, tilt implanted 4H-SiC trench MOSFET (ACTI-TMOS) is proposed. This approach achieves a better trade-off between gate oxide electric field and specific ON-resistance ( $R_{ \mathrm{\scriptscriptstyle ON}}$ ). The 2D numerical simulation was used to compare ACTI-TMOS with double trench MOSFET and gate bottom p-well trench MOSFET. The maximum gate oxide electric field of the ACTI-TMOS is 42.1% and 6.5% lower in OFF state compared to the other two designs. Both gate charge ( $Q_{G}$ ) and gate drain charge ( $Q_{GD}$ ) are significantly improved. The results show that ACTI-TMOS is a more attractive device structure.

(Invited) Laser Annealing in CMOS Manufacturing

Laser Annealing was introduced into mainstream CMOS manufacturing nearly a decade ago and since then has been capturing new applications and expanding into new process regimes. This talk reviews applications of millisecond-scale laser annealing in CMOS technologies from dopant activation to gate dielectric reliability effects to creating metastable alloys to forming silicides. Mitigation of thermal pattern effects and laser-induced substrate distortions are discussed in the context of different device architectures built on both bulk and SOI substrates. Nanosecond-scale laser annealing greatly expands the annealing process space enabling synthesis of highly metastable alloys, spatially selective thermal processing, and targeted thermal treatments with virtually zero impact on the overall thermal budget. Building on the presented historical perspective, we discuss and compare applications of nanosecond-scale laser annealing in future CMOS technologies with 3-dimensional transistors and advanced BEOL interconnects.

Control of Ga-oxide interlayer growth and Ga diffusion in SiO2/GaN stacks for high-quality GaN-based metal–oxide–semiconductor devices with improved gate dielectric reliability

A simple and feasible method for fabricating high-quality and highly reliable GaN-based metal–oxide–semiconductor (MOS) devices was developed. The direct chemical vapor deposition of SiO2 films on GaN substrates forming Ga-oxide interlayers was carried out to fabricate SiO2/GaOx/GaN stacked structures. Although well-behaved hysteresis-free GaN-MOS capacitors with extremely low interface state densities below 1010 cm−2 eV−1 were obtained by postdeposition annealing, Ga diffusion into overlying SiO2 layers severely degraded the dielectric breakdown characteristics. However, this problem was found to be solved by rapid thermal processing, leading to the superior performance of the GaN-MOS devices in terms of interface quality, insulating property, and gate dielectric reliability.

Gate dielectric reliability and instability in GaN metal-insulator-semiconductor high-electron-mobility transistors for power electronics

Abstract

Device physics towards high performance GaN-based power electronics

Gallium-nitride-based power electronic devices, with the inherent high breakdown voltage, high working frequency, high output current density and high temperature operating capability, are promising candidates for next-generation high-efficiency and compact power management systems. In this work, the scientific and technical challenges towards high-performance GaN power devices, including threshold voltage instability, dynamic ON-resistance degradation, enhancement-mode gate techniques and long-term reliability of gate dielectrics, are investigated based on in-depth analysis of the physical origin of interface states and high-voltage current collapse. Oxidation of (Al) GaN surface are suggested to be the primary cause for the surface/interface states in GaN-based power devices. State-of-the-art device technologies, including nitridation-interficial-layer to suppress dielectric/(Al) GaN interface oxidation, polarized PEALD-AlN passivation for compensation of deep interface states, E-mode techniques of fluorine plasma ion implantation and high-temperature low-damage gate-recess, high-breakdown-strength LPCVD-SiN x and O3-sourced ALD-Al2O3 gate dielectrics are introduced for fabrication of high performance and reliability GaN-based power electronic devices.

(Invited) Intrinsic Reliability Assessment of 650V Rated AlGaN/GaN Based Power Devices: An Industry Perspective

Although astounding performance is already proven by many research papers, the widespread adoption of GaN power devices in the market is still hampered by (1) yield and reproducibility ; (2) cost ; (3) reliability. All three factors are to be considered, but to convince customers to adopt GaN power devices, proven device and product reliability is a must. Cost is kept acceptably low by growing the GaN epi stack on 6 inch and 8inch Si substrates, and by processing the GaN power device technology in standard CMOS production lines. This paper will focus on the most important intrinsic reliability mechanisms for GaN power devices. It will cover gate dielectric reliability, Ohmic contact reliability, accelerated drain stress testing (high temperature reverse bias--HTRB) and high voltage device wear-out testing (high voltage off-state stress--HVOS). Acceleration models are discussed A measurement strategy to extract valuable information about the physical properties of the buffer layers (e.g. activation energies of the traps, conduction mechanisms, …) based on simple transmission line structures, is outlined.

(Invited) Intrinsic Reliability Assessment of 650V Rated AlGaN/GaN Based Power Devices: An Industry Perspective

GaN devices are promising candidates for the next generation power devices for energy efficient applications. Although astounding performance is already proven by many research papers, the widespread adoption of GaN power devices in the market is still hampered by (1) yield and reproducibility ; (2) cost ; (3) reliability. All three factors are to be considered, but to convince customers to adopt GaN power devices in their next generation products, proven device and product reliability is a must. Cost is kept acceptably low by growing the GaN epi stack on 6inch and 8inch Si substrates, and by processing the GaN power device technology in standard CMOS production lines, with a proper contamination control protocol in place. This paper will focus on the most important intrinsic reliability mechanisms for GaN power devices. It will cover gate dielectric reliability, Ohmic contact reliability, accelerated drain stress testing (high temperature reverse bias--HTRB) and high voltage device wear-out testing (high voltage off-state stress--HVOS). The need to do reliability investigations based on statistical data on large area power transistors (100+ mm gate width) instead of small test structures will be emphasized. Acceleration models and statistical distribution models (Weibull, lognormal) are discussed. The correlation between the GaN buffer stack vertical leakage and the parametric drift in prime device parameters under accelerated stress will be highlighted. Furthermore, since the MOCVD epi layers of the GaN-on-Si buffer stack are key to the device performance, a measurement strategy to extract valuable information about the physical properties of the buffer layers (e.g. activation energies of the traps, conduction mechanisms, …) based on simple transmission line structures, is outlined. This information will also be linked to the so-called “dynamic Ron”, a recoverable reduction in on-state current due to the trapping of charges in the buffer stack and/or the interface. Finally, it will be shown that through proper engineering of the epi buffer stack, device layout and device passivation scheme, dynamic Ron-free power transistors can be obtained.

Dipole-induced gate leakage reduction in scaled MOSFETs with a highly doped polysilicon/nitrided oxide gate stack

Gate leakage current is reduced up to 24% using a highly doped polysilicon gate/nitrided oxide gate stack. Interestingly, various factors that could affect the gate leakage current such as equivalent oxide thickness (EOT), overlap capacitance, gate dielectric reliability and sub-threshold voltage were found to be unrelated to the reduction in leakage current. Instead, an additional band offset due to an interfacial dipole at the highly doped polysilicon gate and nitrided oxide interface is proposed to explain the anti-intuitive leakage current reduction. This result implies that there is an optimal gate doping condition that will minimize the leakage current accounting a trade-off between the effect of the interfacial dipole and reliability.

Printed polymer and carbon nanotube thin film transistors with high-k barium titanate insulator

One of the difficulties in printed electronics is the robustness and reliability of the thin film transistor gate dielectrics. Thin layers are needed for low voltage operation. Proportionally thicker layers can be used if a higher permittivity (high-k) dielectric is chosen. Here we present the experimental results of partly inkjet and gravure printed thin film transistors with a commercial blend of barium titanate and poly(methyl methacrylate) (PMMA). Poly(triarylamine) (PTAA) or single walled carbon nanotube (SWCNT) inks were deposited as the semiconductor layer. Gravure printing of the dielectric material worked very well. On the other hand the SWCNT ink printing resulted in very thin layers which did not work well in transistors. Large hysteresis and high off current was present in most cases. The reference PTAA transistor measurements show that also a polymer semiconductor can work without hysteresis on top of the high-k dielectric.

Physical, Electrical, and Reliability Characteristics of Multi-Step Deposition-Annealed HfO2 Film

The physical, electrical, and reliability characteristics of the HfO2 gate dielectrics that were fabricated by a single-step and a multi-step deposition-annealing method are compared in this study. After annealing at 750°C, the single-step annealed HfO2 film has transformed into the polycrystalline phase, whereas the multi-step annealed HfO2 film is found to remain in a nanocrystalline phase. Additionally, the density and composition of the HfO2 dielectric films are enhanced by multi-step deposition-annealing process. These changes result in an improvement in the electrical characteristics, breakdown voltage, and reliability for the multi-step deposition-annealed HfO2 film, revealing that the multi-step deposition-annealing method is a promising means for improving the thermal stability and reliability of HfO2 gate dielectrics. In addition to static stress (DC) evaluation, the reliability characteristics of multi-step deposition-annealed HfO2 dielectrics under unipolar and bipolar stresses were also examined. The dielectric breakdown failure time under bipolar stress is longer than those under the other two stress methods. Moreover, as the number of deposition-annealing steps increases, the lifetime enhancement is reduced. However, the failure time is still longer than that of the single-step annealed HfO2 film.

Accuracy assessment of sheet-charge approximation for Fowler-Nordheim tunneling into charged insulators

Various insulators are used as gate dielectrics and passivation layers in wide-bandgap (WBG) semiconductor devices as well as in advanced Si devices, and the understanding of their current conduction mechanism is essential to achieve their high performance and high reliability. Because these insulators are more or less charged, the conduction current is mostly caused by the Fowler-Nordheim (FN) tunneling into charged insulators, ruling out the conventional analytic FN formula. In order to facilitate the analysis of these currents, we focused on the method, named sheet-charge approximation (SCA), of approximating the charge distribution in the insulators by a charge sheet that has the same areal density and centroid as those of the original. Using, as references, the results obtained exactly calculating the tunneling current in the framework of the Wentzel-Kramers-Brillouin approximation, we confirmed the advantage of SCA over the previous method using a tunneling-endpoint field, the error of SCA-estimated areal charge densities being at most 30% for rectangular charge distributions of which charge centroids are known as in stacked films. In a more general case where the centroid is unknown, the SCA usually provides only a charge moment with reference to the insulator/anode interface, being unable to decompose the moment into the areal charge density and centroid. However, this demerit of SCA can be overcome through a reverse-biased current-voltage measurement using a capacitor formed on a heavily doped substrate or a capacitor with a diffusion layer attached, which measurement provides a charge moment with reference to the original cathode/insulator interface. Using these two kinds of charge moments, we can separately extract the areal charge density and centroid. Hence, the SCA has practical significance as a tool for analyzing conduction currents through charged insulators, especially through stacked films, and accordingly will play an important role in improving the performance and reliability of gate dielectrics and passivation layers for various WBG semiconductor devices as well as of high-k gate stacks for advanced Si devices.

Reliability of La-Silicate MOS Capacitors with Tungsten Carbide Gate Electrode for Scaled EOT

Reliability of La-silicate gate dielectrics with tungsten carbide gate electrode have been investigated by Constant Voltage Stress (CVS) measurement. During constant voltage stress of the MOS capacitors, La-silicate MOS capacitors with tungsten carbide gate electrodes show better reliability due to the nice interface properties.

Erratum: “Work function tuning and improved gate dielectric reliability with multilayer graphene as a gate electrode for metal oxide semiconductor field effect device applications” [Appl. Phys. Lett. 100, 233506 (2012)

First Page

Reliability study of ultra-thin dielectric films with variable thickness levels

The time-dependent dielectric breakdown of ultra-thin gate oxides is one of the major reliability issues facing scaled metal-oxide semiconductor technologies. As the thickness of the gate dielectric film approaches its scaling limit, process issues such as poor wafer uniformity and oxide growth control become critical for ultra-thin gate dielectric reliability. This article investigates both the physics and statistical aspects of the reliability of the ultra-thin gate dielectric when film thickness variations are present. A physics-based Spatio-Temporal Monte Carlo Simulation (STMCS) model is developed to study the effects of thickness and thickness non-uniformity on dielectric reliability. Its use allows the root cause for the non-linear characteristic of the Weibull time-to-breakdown distribution observed in experimental studies to be revealed. In addition, a Bayesian Weibull Mixture (BWM) model is proposed to analyze the time-to-breakdown data considering the existence of thickness non-uniformity. Numerical results are presented that show that the proposed BWM model is significantly superior to the basic Weibull model for use in reliability projection. Both the STMCS and BWM models can successfully reproduce the experimentally observed non-linear characteristic of the Weibull time-to-breakdown distribution and thus can be used to predict device reliability when the dielectric films in a gate are of unequal thicknesses.

Work function tuning and improved gate dielectric reliability with multilayer graphene as a gate electrode for metal oxide semiconductor field effect device applications

Graphene with varying number of layers is explored as metal gate electrode in metal oxide semiconductor structure by inserting it between the dielectric (SiO2) and contact metal (TiN) and results are compared with TiN gate electrode. We demonstrate an effective work function tuning of gate electrode upto 0.5 eV by varying the number of graphene layers. Inclusion of even 1-3 layers of graphene results in significantly improved dielectric reliability as measured by breakdown characteristics, charge to breakdown, and interface state density. These improvements are attributed to the impermeability of graphene for TiN and hence reduced metallic contamination in the dielectric.

Effect of Al incorporation on the performance and reliability of p-type metal-oxide-semiconductor field effect transistors

This study examined the performance and reliability of HfO2 gate dielectrics in p-type metal-oxide-semiconductor field effect transistors (pMOSFETs) capped with Al or Al2O3. The presence of Al capping deteriorated the pMOSFET scalability and channel mobility compared to Al2O3 capping. Al capping caused a higher rate of Al diffusion in the HfO2 dielectric layer, reducing the device performance and oxide thickness scaling. This degradation of the negative bias temperature instability of the Al-incorporated sample was attributed to decay of the interface quality rather than to a decrease in charge trapping in the bulk high-k dielectric.