Gate Delay Time Research Articles

Validation of a Four-Quadrant Gate Simulation Model: Predicted Versus Actual Gate Operating Values

Coleman and Moon demonstrated a traffic engineering-based design methodology to determine gate delay (length of flashing signal operation prior to entry gate descent) and gate interval time (time period between initiation of descent of entry gates and initiation of descent of exit gates) at four-quadrant gate crossings. A simulation model incorporating this traffic engineering-based design methodology was developed for the Illinois Department of Transportation to assist in establishing four-quadrant gate operating parameters. To assist in validating the four-quadrant gate simulation model, a comparison of the gate operating parameters at a recent installation in North Carolina was undertaken. The findings from the comparison indicate there is close agreement with the values used in the field installation and those determined by the simulation model.

A low-resistance self-aligned T-shaped gate for high-performance sub-0.1-μm CMOS

This paper describes the high performance of T-shaped-gate CMOS devices with effective channel lengths in the sub-0.1-/spl mu/m region. These devices were fabricated by using selective W growth, which allows low-resistance gates smaller than 0.1 /spl mu/m to be made without requiring fine lithography alignment. We used counter-doping to scale down the threshold voltage while still maintaining acceptable short-channel effects. This approach allowed us to make ring oscillators with a gate-delay time as short as 21 ps at 2 V with a gate length of 0.15 /spl mu/m. Furthermore, we experimentally show that the high circuit speed of a sub-0.1-/spl mu/m gate length CMOS device is mainly due to the PMOS device performance, especially in terms of its drivability.

The relevance of f/sub T/ and f/sub max/ for the speed of a bipolar CE amplifier stage

Expressions relating the bandwidth of a common-emitter (CE) amplifier stage and the small-signal CML gate delay time to directly measurable transistor parameters, such as f/sub T/, f/sub max/, and input bandwidth f/sub /spl upsi//, are presented. They are valid for an arbitrary division of the base resistance and base-collector depletion capacitance into internal and external components. No resistance measurements are needed. It is shown that the transistor input bandwidth f/sub /spl upsi// is an important figure of merit for the speed of a CE stage. Under a given bias condition, f/sub /spl upsi// is determined by the base resistance and the cut-off frequency. In most cases the value of the maximum oscillation frequency f/sub max/ is only of minor importance. It would therefore be more meaningful to present besides f/sub T/ also f/sub /spl upsi// instead of f/sub max/ as a figure of merit for transistors for high-speed, low-power analog and digital circuits.

12-ps ECL using low-base-resistance Si bipolar transistor by self-aligned metal/IDP technology

A self-aligned metal/IDP (SMI) technology is proposed to reduce the external base resistance and to enable fabrication of high-speed bipolar transistors. This SMI technology produces a self-aligned base electrode of stacked layers of metal and in situ-doped poly-Si (LDP) with a small thermal budget by selective tungsten CVD. It provides the low base resistance and a shallow link base for the small-collector capacitance and the high-cutoff frequency. The base resistance is reduced to a half that in a transistor having a conventional poly-Si base electrode. A maximum oscillation frequency of 81 GHz and a 12.2-ps gate delay time in an ECL ring oscillator at a voltage swing of 250 mV were achieved by using the SMI technology even with an ion-implanted base.

Design of Gate Delay and Gate Interval Time for Four-Quadrant Gate System at Railroad-Highway Grade Crossings

A design methodology for gate delay and gate interval time for at-grade crossings using four-quadrant gates is developed. The design approach is based on the concept of dilemma zones related to signal change intervals at signalized intersections. The design approach is validated based on data from six sites in Illinois on a proposed high-speed rail corridor. Gate delay and gate interval times are determined that provide an optimal safe decision point to allow a driver to stop before the crossing or to proceed through the crossing without becoming trapped by the exit gates.

Design of Gate Delay and Gate Interval Time for Four-Quadrant Gate System at Railroad-Highway Grade Crossings

A design methodology for gate delay and gate interval time for at-grade crossings using four-quadrant gates is developed. The design approach is based on the concept of dilemma zones related to signal change intervals at signalized intersections. The design approach is validated based on data from six sites in Illinois on a proposed high-speed rail corridor. Gate delay and gate interval times are determined that provide an optimal safe decision point to allow a driver to stop before the crossing or to proceed through the crossing without becoming trapped by the exit gates.

Assessment of soot volume fractions from laser-induced incancescence by comparison with extinction measurements in laminar, premixed, flat flames

For the validation of detailed chemical models for soot formation, and for their application to turbulent flames, 2-D measuring techniques are necessary to derive locally resolved soot volume fractions, particle sizes, and number densities. In one-dimensional laminar flames, these particle properties are derived from Rayleigh-scattering/extinction techniques. The extinction technique, as a line-of-sight method, is not appropriate for investigation of three-dimensional, nonstationary, turbulent systems. Therefore, for turbulent flames, other measuring techniques have to be developed that can be employed in combination with, for example, Rayleigh scattering. One technique that has been applied to obtain soot volume fractions in laminar flames is Laser-Induced Incandescence (LII) [1]. The major task in applying this technique is to clarify in which way the relative LII signals should be calibrated to yield absolute soot volume fractions. In this work, the LII technique is investigated systematically in laminar, premixed, ethyne/argon/oxygen flames using a pulsed, high-power Nd:YAG laser. Therefore, the LII signals are compared with soot volume fractions obtained using extinction. The systematic investigation of the LII technique under different detection conditions (camera gate width and gate delay times) shows that there are inconsistencies between calibrated LII signals and soot volume fractions from extinction. The aim of this work is to explain these inconsistencies by a numerical simulation of the LII signal, based on mass and energy balance equations of the heated soot particles for different flame conditions. Additionally, a sensitivity analysis with respect to different parameters of the balance equation is performed. The results indicate that geometric irregularities of the soot particles probably have to be taken into account for correct prediction of soot volume fractions using LII.

Very-high-speed silicon bipolar transistors with in-situ doped polysilicon emitter and rapid vapor-phase doping base

We present a detailed study of the performance of very-high-speed silicon bipolar transistors with ultra-shallow junctions formed by thermal diffusion. Devices are fabricated with double-polysilicon self-aligned bipolar technology with U-groove isolation on directly bonded SOI wafers to reduce the parasitic capacitances. Very thin and low resistivity bases are obtained by rapid vapor-phase doping (RVD), which is a vapor diffusion technique using a source gas of B/sub 2/H/sub 6/. Very shallow emitters are formed by in-situ phosphorus doped polysilicon (IDP) emitter technology with rapid thermal annealing (RTA). In IDP emitter technology, the emitters are formed by diffusion from the in-situ phosphorus doped amorphous silicon layer. Fabricated transistors are found to have ideal I-V characteristics, large current gain and low emitter resistance for a small emitter. Furthermore, a minimum ECL gate delay time of 15 ps is achieved using these key techniques. Analyses of the high performance using circuit and device simulations indicate that the most effective delay components of an ECL gate are cut-off frequency and base resistance. A high cut-off frequency is achieved by reducing the base width and active collector region. In this study, RVD is used to achieve both high cut-off frequency and low base resistance at the same time. >

Fabrication of a Single Crystal Silicon Substrate for AM-LCD Using Vertical Etching of (110) Silicon

ABSTRACTIn this paper, feasibility of crystalline silicon (c-Si) substrate for transmissive active matrix liquid crystal displays (AM-LCDs) has been investigated. The transparent pixel areas of AM-LCD were formed by vertical etching of (110) silicon substrate using anisotropie etching property of aqueous KOH. Combining this vertical etching process with the conventional MOSFET fabrication process, the pixel switching devices, peripheral circuits and transparent apertures were successfully integrated on the same c-Si substrate. The pixel NMOS devices exhibit an electron mobility of about 600cm2/V-s, a subthreshold slope of 65mV/decade and ON/OFF current ratio of 9 decades at 5V drain voltage. And the gate delay time is 3.3ns at 10V power voltage, measured from a ring oscillator which has enhancement-load type NMOS inverters having the (W/L) iload- (W/L) driverer of 25μm/15μm - 50μm/10μm.

Time and Spatially Resolved Spectrum Study of Laser-Induced Plasma in Reduced Pressure Atmospheres of Argon and Helium.

In order to find the optimum conditions which give best line-to-background ratio as well as high spectral line intensity, the emission characteristics of a Nd: YAG laser-induced plasma were studied in argon and helium atmospheres at reduced pressures from 760 to 1 Torr by using a combination of space and time resolution. From the experimental results, the conditions of a 200 Torr argon, an observation position of about 1.5mm above the sample surface, and a gate delay time of 2μs measured after the initiation of the laser pulse were established as optimum.

Time-Resolved Luminescence Spectroscopy: Computer Interfacing and Software Development for a Boxcar-Based Laser-Luminescence Spectrometer

The undesirable resistance-capacitance (RC) distortion coming from the exponential moving averaging process of a boxcar integrator/averager acquisition system in kinetic and spectral luminescence measurements could be effectively eliminated by interfacing it to a microcomputer. Accurate acquisition of luminescence decay curves and time-resolved spectra was provided by a developed software that allows synchronous scan control of the gate delay time in the boxcar integrator with the emission wavelength in the monochromator. Some simple mathematical calculation routines, including excited-state lifetime extraction from luminescence decay curves and normalization of time-resolved spectra, were added. The main characteristics of both the software and the interfacing hardware are reported.

Study of BiCMOS logic gate configurations for improved low-voltage performance

A simple BiCMOS configuration employing the source-well tie PMOS/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS/n-p-n (conventional) BiCMOS gate is confirmed by means of inverter simulations and measured ring oscillator data. The source-well tie PMOS/n-p-n BiCMOS gate outperforms its conventional BiCMOS counterpart in the low-voltage supply range, at both high and low temperatures. A critical speed path from the 68030 internal circuit is used as a benchmark for the proposed BiCMOS design technique. The measured propagation delay of the BiCMOS speed path is faster than its CMOS counterpart down to 2.3 V supply voltage at -10 degrees C and sub-2 V at 110 degrees C. >

Near-future perspectives for Si and Si 1−yGe y bipolar transistors

The performance limits of self-aligned npn Si-BJTs and SiGe-HBTs are investigated for different types of processing. Using a one-dimensional drift-diffusion equation solver, device simulations are carried out for different doping and germanium profiles. From these simulations network parameters are extracted, which are used as input data for the SPICE-simulation of CML ring oscillators. In addition to one verification profile, three different types of processing are considered, which are designed to give the near-future performance limits of both Si and SiGe bipolar transistors: The first one is a profile as obtained by ‘conventional’ processing utilizing implantation and diffusion. The second one has a heavily doped base and a small, lightly doped emitter region, as might be realizable by epitaxial deposition of in-situ doped layers. The third one is similar to the second one, but uses a Si 0.8Ge 0.2/Si-strained base. The simulations show that CML gate delay times of approx. 15 ps, 10 ps and 7 ps, respectively, are realizable with these profiles.

Advanced process device technology for 0.3- mu m high-performance bipolar LSIs

A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3- mu m bipolar LSIs. Fabricated 0.5- mu m U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 mu m/sup 2/, and they have an isolation width of 2.0 mu m, a minimum emitter width of 0.2 mu m, a maximum cutoff frequency (f/sub T/) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3- mu m bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f/sub T/ and base resistance is also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Performance potential of silicon bipolar transistors

The performance potential of silicon bipolar transistors is investigated by device simulation. Using a one-dimensional drift-diffusion equation solver, the SPICE parameters of selfaligned transistors are extracted from doping profiles and device geometries. These parameters are used to predict the CML gate delay for different doping profiles. The validity of this extraction procedure is verified by comparison with experimental data. For a double-diffusion type doping profile with a pinch resistance of 15kΩ/□, a transit frequency of 56GHz and a CML gate delay of ∼15ps are achievable. With a doping profile including a low-doped emitter region and a high base doping concentration, significant improvements are found: A transit frequency of 81.6GHz and a pinch resistance of 10kΩ/□ enable CML gate delay times below 10 ps.

CMOS-compatible lateral bipolar transistor for BiCMOS technology. I. Modeling

A CMOS-compatible lateral bipolar transistor having neither an epitaxial layer nor n/sup +/-buried layers is proposed. The simulation indicates that the BiCMOS gate delay time shows a weak dependence on the metallurgical base width W/sub B/, (and hence on f/sub Tmax/, since f/sub T/ varies as 1/W/sub B//sup 2/) and strong dependence on the effective base width W/sub B(eff)/, where W/sub B(eff)/ nearly equals the distance between the emitter and the n/sup +/ collector, d/sub E-C/. This is because bipolar transistors in BiCMOS circuits are operated in high-level injection during the switching transient. Therefore, it is possible to build a high-speed BiCMOS gate using lateral bipolar devices with short d/sub E-C/. The transistor has a structure similar to that of an n-channel MOSFET. The emitter and collector are formed simultaneously and self-aligned to a polysilicon base electron like the source and drain in a MOSFET. >

Deep-submicrometer CMOS technology with reoxidized or annealed nitrided-oxide gate dielectrics prepared by rapid thermal processing

Deep submicrometer CMOSFETs with re-annealed nitride-oxide gate dielectrics have been demonstrated to satisfy 3.3-V operation, unlike conventional oxide FETs. The 1/4- mu m re-annealed nitrided-oxide CMOS devices achieve (1) an improved saturation transconductance g/sub m/ of approximately 250 mu S/ mu m for n-FETs together with acceptably small degradation in p-FET g/sub m/ resulting in a CMOS gate delay time of 55 ps/stage comparable or superior to the device/circuit performance of oxide FETs, and (2) device lifetimes improved by approximately 100 times to exceed 10 years with respect to both ON- and OFF-state hot-carrier reliability for n-FETs as well as gate-dielectric integrity together with unchanged p-FET hot-carrier reliability, all at 3.3-V operation. To achieve these CMOS performance/reliability improvements, both a light nitridation and subsequent re-annealing in O/sub 2/ (reoxidation) or in N/sub 2/ (inert-annealing) are found to be crucial. >

A 1.5-V full-swing BiCMOS logic circuit

A BiCMOS logic circuit applicable to sub-2-V digital circuits has been developed. A transiently saturated full-swing BiCMOS (TS-FS-BiCMOS) logic circuit operates twice as fast as CMOS at 1.5-V supply. A newly developed transient-saturation technique, with which bipolar transistors saturate only during switching periods, is the key to sub-2-V operation because a high-speed full-swing operation is achieved to remove the voltage loss due to the base-emitter turn-on voltage. Both small load dependence and small fan-in dependence of gate delay time are attained with this technique. A two-input gate fabricated with 0.3- mu m BiCMOS technology verifies the performance advantage of TS-FS-BiCMOS over other BiCMOS circuits and CMOS at sub 2-V supply.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analysis of highly doped collector transistors by using two-dimensional process/device simulation and its application of ECL circuits

A report is presented of the results of an investigation of device parameters and collector-to-emitter breakdown voltages of double polysilicon self-aligned transistors with highly doped collectors using a two-dimensional process/device simulation system. Favourable phosphorous-ion implanting condition for a highly doped pedestal collector was found to achieve a high cutoff frequency as well as low AC base resistance and small base-collector capacitance, thereby keeping the minimum collector-to-emitter breakdown voltage of 3 V. The authors also report ECL circuit performance improvements achieved in experiments that realized a minimum ECL gate delay time of 26.3 ps/gate at switching current of 1.64 mA as a result of process optimization. Moreover, a 1/8 static frequency divider T-F/F has been observed to operate up to a maximum frequency of 15.8 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates

A 45 K-gate emitter-coupled-logic (ECL)-compatible array with unbuffered and buffered direct-coupled FET-logic (DCFL and BDCFL) gates has been developed using 0.6- mu m-gate high-electron-mobility transistors (HEMTs) and four-level gold-based interconnects. The high-speed DCFL gates and more functional BDCFL gates are used to replace ECL macros efficiently. The basic cell, equivalent to four three-input NOR gates, consists of 12 enhancement-mode (E-mode) HEMTs, four depletion mode (D-mode) HEMTs, and two source-follower buffers. The basic gate delay times are 35 ps for 0.24-mW unbuffered DCFL gates and 50 ps for 0.38-mW BDCFL gates. The gate array chip is 9.8*9.8 mm and contains 45600 gates. The chip dissipates 11 W in 80% gate use. Silylated polymethyl silsequioxane (PMSS), which has a low dielectric constant of 3, is used for the interlayer dielectrics to reduce wiring delay.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>