Gate Delay Time Research Articles

Modeling of inner-outer gates and temperature dependent gate-induced drain leakage current of junctionless double-gate-all-around FET

In this paper, the temperature-dependent gate-induced drain leakage (GIDL) current model is proposed with the help of a lateral electric field (EL) across the inner and outer gate interfaces of the junctionless double-gate-all-around (JL-DGAA) field-effect transistor (FET). The EL at the interface is obtained from the surface potential equation after solving the 3D Poisson equation with appropriate boundary conditions. The derived model is validated using the well-calibrated TCAD simulator platform with experimental data. A higher GIDL current at the outer gate-channel interface is observed compared to the inner gate-channel interface in the OFF-state conditions due to the high EL between the channel and drain, which is reported for the first time here. The effect of temperature (from 200 K to 500 K) on the GIDL current is also observed, which increases linearly with increasing temperature. Further, the impact of induced mechanical stress (MS) is investigated on the GIDL current, where the GIDL current increases exponentially with increasing induced MS due to effective mass and band gap reduction. Finally, the dynamic performance is investigated in terms of the gate delay time as a function of channel length and temperature. The gate delay diminishes with decreasing channel length and increasing temperature, which shows the switching speed and ability of the device.

Flight Time and Flight Traffic Before, During, and After the Pandemic: What Has Changed?

This paper develops a model for quantifying the relationship between flight volume and its operational performance at the macro level and investigating whether there are any changes before, during, and after the pandemic. Inspired by the market basket concept from economics, we first calculate macro-level effective flight time (EFT) for the U.S. domestic flight market by constructing a flight basket. Semi-log-linear models are developed to formulate the relationship between the total number of flights and macro-level EFT and its components. The estimation results indicate that the total number of flights has a positive and significant impact on EFT and its components, with 29.244 min longer for the weighted EFT for the analysis period compared with a zero-traffic scenario. Further investigations into the post-pandemic period verify the performance of the model and indicate that deteriorating operational performance in this period, especially with regard to gate delay and taxi-in time, is not only a result of the recovery of the flight market.

Dynamic Gate Delay Time Control of Si/SiC Hybrid Switch for Loss Minimization in Voltage Source Inverter

The voltage source inverter (VSI) based on the Si/SiC hybrid switch (HyS) offers a better cost/performance tradeoff than the full-SiC VSI design. However, the Si/SiC hybrid VSI bears huge power losses with fixed gate turn-off delay time. In this article, a novel dynamic optimal gate turn-off delay time control method of Si/SiC HyS-based VSI is proposed to achieve the maximum efficiency over a wide load range. The optimal gate turn-off delay time is obtained by a load current-based mathematic power loss model. A 20-kHz 5-kW prototype of the single-phase constant current (CC) VSI using a 1200-V/25-A insulated gate bipolar transistor (IGBT) and a 1200-V/12.5-A SiC MOSFET is built to validate the proposed method. In comparison with the fixed gate turn-off delay time control method, the proposed method achieves 8% total power loss reduction and 0.24% conversion efficiency improvement at 1.5-kW output power.

Modeling of a vertical tunneling transistor based on Gr-hBN- χ 3 borophene heterostructure

We present a computational study on the electrical behavior of the field-effect transistor based on vertical graphene-hBN-χ3 borophene heterostructure and vertical graphene nanoribbon-hBN-χ3 borophene nanoribbon heterostructure. We use nonequilibrium the Green function formalism along with an atomistic tight-binding (TB) model. The TB parameters are calculated by fitting tight-binding band structure and first-principle results. Also, electrical characteristics of the device, such as ION/IOFF ratio, subthreshold swing, and intrinsic gate-delay time, are investigated. We show that the increase of the hBN layer number decreases subthreshold swing and degrades the intrinsic gate-delay time. The device allows current modulation 177 at room temperature for a 1.2 V gate-source bias voltage.

Analysis and simulation of asymmetrical nanoscale self-switching transistor

ABSTRACT In this paper, we present a computational study on the electrical behaviour of self-switching transistors (SSTs) based on InGaAs/InP heterojunction. Our simulation is based on the solution of Poisson and Schrodinger equations self-consistently by using Finite Element Method (FEM). By using this method, electrical characteristics of device, such as ratio, subthreshold swing, and intrinsic gate-delay time are investigated. Also, the effects of geometrical variations on the electrical parameters of SSTs are simulated. We show that appropriate design of the device allows current modulation exceeding at room temperature.

A Variable-Frequency Current-Dependent Switching Strategy to Improve Tradeoff Between Efficiency and SiC MOSFET Overcurrent Stress in Si/SiC-Hybrid-Switch-Based Inverters

Reliability remains an issue for the Si/SiC hybrid switch adopting the conventional switching strategy of the internal SiC MOSFET that turns on earlier, and off later. Such issue is attributable to the overcurrent stress under the heavy load operating condition, which adversely affects the SiC MOSFET during the gate delay time. To solve this problem without increasing the extra power loss, a novel variable-frequency current-dependent switching strategy combining the variable switching pattern strategy, and the variable pulsewidth modulation (PWM) frequency strategy is proposed. Variable switching pattern strategy can avoid the overcurrent stress of the SiC MOSFET at the heavy load operating condition, and the designed optimal delay time in different switching patterns can achieve the compromise between the excellent reliability, and the power loss of Si/SiC hybrid switch. Variable PWM frequency strategy can effectively reduce the switching loss of the Si/SiC hybrid switch by decreasing the switching frequency around the peak current region. An Si/SiC-hybrid-switch-based single-phase inverter platform is constructed and tested. Test results show that the power loss of the single-phase inverter adopting such switching strategy outperforms the current-dependent switching strategy with 9.4% reduction of power loss, and overcurrent stress of SiC MOSFET is avoided.

Influence of Glass Surface Modification on Thin Film Copper Electrodes

Large-area and ultra-high resolution displays continue to progress driven by new performance requirements and applications. As display sizes become larger, the industry demands metal electrodes with low resistance to reduce the gate delay time and signal distortion. Cu is an attractive candidate due to its relative low resistivity and its superior resistance to electromigration as opposed to materials such as Al or Mo. For bottom gate TFT technologies, the metal electrode is deposited directly on the glass substrate. Cu is known to have poor adhesion with oxide materials such as the substrate glass. Typically, an adhesion layer such as Ti, Mo, or other metal/alloy is required to improve the adhesion of Cu to the substrate. In this work, we modify Corning® Eagle XG® glass surfaces by various treatments to study the impact of the glass surface on the structural and electrical properties of Cu. Ti was used the adhesion layer in this study. Atomic force microscopy is used to examine the surface topography and the surface roughness of Cu. In-plane X-ray diffraction results characterize the crystallization and crystalline in-plane orientation of Cu. Transmission electron microscopy is used to further investigate the structure of the Ti and Cu films. The films properties are correlated with 4-point probe measurement of the sheet resistance. The film adhesion performance is determined using the tape test. The role of the glass surface state is demonstrated through its impact on the structural and electrical properties of Ti/Cu electrodes emanating from glass surface treatments.

Adaptive Gate Delay-Time Control of Si/SiC Hybrid Switch for Efficiency Improvement in Inverters

Varying gate delay time of the Si insulated-gate bipolar transistor/SiC MOSFET hybrid switch is the key to achieving high efficiency of Si/SiC-hybrid-switch-based power converters because of time-varying characteristics of its junction temperature and operation current. Based on the swarm intelligent algorithm, a novel adaptive delay-time control method of the Si/SiC hybrid switch in an inverter is proposed to achieve higher efficiency than the traditional fixed delay time. In addition, by evaluating the fitness values, the proposed method can easily achieve this goal without establishing the physics-based analytical model of device loss and additional hardware support. The platform of the Si/SiC-hybrid-switch-based single-phase inverter is established and tested, and the particle swarm optimization algorithm is taken as example. Experimental results demonstrate that the proposed technique yields 6.2% reduction in the total loss of the single-phase inverter compared to a fixed delay time.

A comparative computational study of tunneling transistors based on vertical graphene–hBCN heterostructures

In this paper, the electrical characteristics of tunneling transistors based on vertical graphene and a hexagonal boron-carbon-nitrogen (hBCN) heterostructure are studied and compared theoretically. We have considered three different types of hBCN, i.e., BC2N, BC2N′, and BC6N as a tunneling barrier. Our simulation is based on the nonequilibrium Green’s function formalism along with an atomistic tight-binding (TB) model. The TB parameters are obtained by fitting the band structure to first-principles results. By using this method, electrical characteristics of the device, such as the ION/IOFF ratio, subthreshold swing, and intrinsic gate-delay time, are investigated. For a fair comparison, the effects of geometrical variations and number of tunneling barrier layers on the electrical parameters of the device are simulated and investigated. We show that, by an appropriate design, the device can be used for low-power or high-performance applications. The device allows current modulation exceeding 106 at room temperature for a 0.6 V bias voltage.

Double-Gate Field-Effect Diode: A Novel Device for Improving Digital-and-Analog Performance

In this article, a novel double-gate (DG) field-effect diode (FED) has been proposed, which exhibits smaller short-channel effects (SCEs), smaller OFF-state current ( $I_{\mathrm{\scriptscriptstyle OFF}}$ ) and higher ON-state current ( $I_{\mathrm{\scriptscriptstyle ON}}$ ) compared with the previously introduced common FEDs and the side-contacted FEDs (SFEDs). Based on the TCAD simulation study, due to the stronger control of the two gates over the channel, the proposed double-gate FED (DGFED) is shown to suppress the SCEs and to improve $I_{\mathrm{\scriptscriptstyle ON}}$ / $I_{\mathrm{\scriptscriptstyle OFF}}$ ratio significantly compared with the SFEDs. The proposed device is also shown to have smaller gate delay time, smaller energy-delay product, larger cutoff frequency, and larger transconductance than the SFED. Thus, DGFED is a promising device for substituting the SFED in possible high-frequency analog and digital applications.

Active Gate Delay Time Control of Si/SiC Hybrid Switch for Junction Temperature Balance Over a Wide Power Range

The optimal gate delay time control between the two internal devices to achieve excellent electrical and thermal performance of the Si/SiC hybrid switch is considerably affected by several factors and requires careful adjustment to suit the different operation conditions of power converters. However, the conventional gate control solution for the hybrid switch applies a fixed delay time to achieve the minimum switching loss at a specific load current, resulting in disparities in junction temperature of internal devices over a wide load range. This effectively reduces the safe operating area by risking one internal switch subjected to overrated junction temperature in a wide range operation with regard to power handling condition. To avoid such a serious risk of reliability degradation or thermal breakdown, a novel active gate delay time control strategy based on the electro-thermal coupling loss model is proposed. The gate delay time was dynamically adjusted and optimized according to the operation conditions of power converters so that the operation junction temperature difference of the two internal devices can be minimized. Experimental results demonstrate that the junction temperature of the hybrid switch decreases by 20 °C at 8-kW load condition and its maximum power handling capability increases by 18%, without compromising the power converter's efficiency in a 20 kHz Si/SiC hybrid switch-based dc/dc buck converter compared with the conventional approach.

Ballistic Quantum Transport of Sub‐10 nm 2D Sb2Te2Se Transistors

Abstract2D materials, due to their ultrathin dangling‐bond‐free configuration and excellent electrostatic control, have potential as possible Si‐alternative building blocks for future competitive devices. Exploring 2D electronic materials with suitable band gap and high mobility is key to designing ultra‐scaled devices. The electronic properties and device performance of sub‐10 nm 2D Sb2Te2Se are studied by ab initio quantum‐transport simulations. The results show that 2D Sb2Te2Se, a stable system, possesses an indirect bandgap of 1.01 eV and high electron mobility exceeding 103 cm2 V−1 s−1. Through comparing with the ballistic quantum transports of Sb2Te2Se, the n‐metal‐oxide‐semiconductor field‐effect transistor (MOSFET) exhibits better device performance than p‐MOSFET. In particular, not only can the on‐current of n‐MOSFET with gate length Lg = 9 nm reach as high as 1660 µA µm−1, but its other figures of merit including gate capacity (0.72 fF µm−1), delay time (0.31 ps), and power dissipation (0.37 fJ µm−1) also satisfy the International Technology Roadmap for Semiconductors 2020 requirements. Therefore, 2D Sb2Te2Se could become a potential electronic material for next‐generation nanodevices.

Analysis Of Toll Gate Traffic Delay Time Using E-Toll System On Waru-Juanda Toll Road

Currently the traffic on the highway is getting crowded, because it filled with so many four-wheeled vehicles. To reduce congestion at the highway then be made to the motorway. But the government's efforts to maximize the use of toll roads to minimize congestion in fact, has not run optimally for payments using the system to pay cash (cash) is less effective. In 2017 PT. Margatama image Surabaya implement E-Toll at the toll booth Waru - Juanda. To find out how the effectiveness of the use of E-Toll system was conducted research to analyze traffic toll gate delay time with the e-toll system on toll roads hibiscus - juanda. Collecting data in this study conducted on Friday at 4:00 p.m. to 20:00 pm and is located at the toll gate Menanggal. The variables used were manual payment system / cash and payment systems using E-toll by noting the number of vehicles entering the toll gate along with the time needed to conduct transactions at toll booths. From the research conducted, the average time delay that is required at the time for using the E-Toll Card was 13.6 seconds / transaction so that they result in queues at toll gates. From these results it can be concluded that the use of E-Toll card is still not effective in reducing congestion at toll booths. The average time delay that is required at the time for using the E-Toll Card was 13.6 seconds / transaction so that they result in queues at toll gates. From these results it can be concluded that the use of E-Toll card is still not effective in reducing congestion at toll booths. The average time delay that is required at the time for using the E-Toll Card was 13.6 seconds / transaction so that they result in queues at toll gates. From these results it can be concluded that the use of E-Toll card is still not effective in reducing congestion at toll booths.

Quantitative analysis of Fuller's earth using laser-induced breakdown spectroscopy and inductively coupled plasma/optical emission spectroscopy.

Fuller's earth, most commonly known as Multani Matti (clay) in Urdu, among its various utilizations is traditionally used in skin care cosmetics, particularly for removing blackheads and to treat oily skin. It is also used for improving skin complexion. In this paper, laser-induced breakdown spectroscopy (LIBS) was effectively employed for the quantitative investigation of various clay samples for their special uses. To get the LIBS spectra with an optimal signal-to-noise as well as for a more robust and accurate analytical investigation, different experimental parameters (laser energy, gate delay time, and the distance between target and focusing lens) were optimized before the experiments on actual samples. The analysis of emission spectra revealed the presence of many different elements, including Al, Ca, Fe, Mg, Mn, Na, K, Li, S, Si, and Zn. The electron number density and plasma temperatures were determined using the Stark broadened line profile and Boltzmann plot method, respectively. To determine the relative concentration of observed elements, we used an integrated intensity ratio method, integrated intensity of every line from all elements, and calibration free (CF)-LIBS. The prevailing condition of local thermodynamic equilibrium during the experimental executions was verified with multiple criteria. The spectral lines used in CF-LIBS were characterized for the influence from the self-absorption phenomenon, but the same was found insignificant. The findings of our LIBS system were found to agree excellently with the outcomes of the inductively coupled plasma/optical emission spectroscopy, thereby yielding a high statistical correlation factor and hence enlighten the significance of LIBS as a safe and reliable tool for elemental analysis of clay samples.

Determination of excitation temperature in laser-induced plasmas using columnar density Saha-Boltzmann plot

In exploiting the analytical capabilities of plasma-based spectroscopy method, the evaluation of plasma parameters, particularly the plasma temperature, is a crucial step. In this work, a modified Saha-Boltzmann plot, which uses the columnar densities of atomic and ionic ground levels, is utilized to calculate the plasma temperature in a laser-induced plasma from an aluminum alloy target. The columnar densities are here calculated by quantifying the self-absorption of resonance lines. It is demonstrated that this is a promising method for accurate determination of plasma temperature. To validate the capability of this technique, plasma emission is measured at different gate delay times. For each delay, excitation temperature is calculated both by the conventional Saha-Boltzmann plot (by using the excited states) and by exploiting the new Columnar Density Saha–Boltzmann (CD-SB) plot. The results suggest that at later times of the plasma evolution, the CD-SB plot can be more suitable for the determination of plasma temperature than conventional Saha-Boltzmann plot. These findings provide a new approach for physical characterization of plasmas and give access to a wealth of information about the state of plasma.

Investigation on the dynamic characteristics of LIBS for heavy metal Mn in liquid matrix

Laser-induced breakdown spectroscopy in composition analysis of materials has many advantages over other analytical methods.Based on our Laser Induced Breakdown Spectroscopy (LIBS) survey system of heavy metals in the mixed solution and the optimum experimental parameters, we measured the integrated intensities of partial spectral lines of Mn when the ICCD gate delay time and the sample flow rate were ranged from 500ns to 2500ns, 35ml/min to 55ml/min respectively. With increasing the time delay, the electron temperature of the plasma decreases gradually, the electron density decreases firstly,then the change amplitude tends to be flat.As the flow rate continue increasing,the electron temperature of plasma increases firstly, then the change tends to be flat, the electron density increase gradually.The element particle density ratio of Mn at first ionization state to ground state and Mn at first ionization state are also obtained respectively. Finally, by comparing the experimental value of spectral line intensity ratio of Mn with the calculated value, the nonexistent conditions of local thermal equilibrium and self-absorption of laser plasma are verified.It provides the suppuration for forward quantitative analysis of the trace heavy metal elements in liquid matrix.

Evaluation of a 100-nm Gate Length E-Mode InAs High Electron Mobility Transistor With Ti/Pt/Au Ohmic Contacts and Mesa Sidewall Channel Etch for High-Speed and Low-Power Logic Applications

In this paper, a 100-nm gate length InAs high electron mobility transistor (HEMT) with non-alloyed Ti/Pt/Au ohmic contacts and mesa sidewall channel etch was investigated for high-speed and low-power logic applications. The device exhibited a low subthreshold swing (SS) of 63.3 mV/decade, a drain induced barrier lowering value of 23.3 mV/V, an ION/IOFF ratio of 1.34 $\times$ 104, a Gm,max/SS ratio of 27.6, a current gain cut-off frequency of 439 GHz with a gate delay time of 0.36 ps, and an off-state gate leakage current of less than 1.6 $\times 10^{-5}$ A/mm at VDS = 0.5 V. These results demonstrated that the presence of non-annealed ohmic contacts with mesa sidewall etch process allowed the fabrication of InAs HEMTs with excellent electrical characteristics for high-speed and low-power logic applications.

Temporal and spatial dynamics of optical emission from laser ablation of the first wall materials of fusion device

Laser-induced breakdown spectroscopy (LIBS) has been developed to in situ diagnose the chemical compositions of the first wall in the EAST tokamak. However, the dynamics of optical emission of the key plasma-facing materials, such as tungsten, molybdenum and graphite have not been investigated in a laser produced plasma (LPP) under vacuum. In this work, the temporal and spatial dynamics of optical emission were investigated using the spectrometer with ICCD. Plasma was produced by an Nd:YAG laser (1064 nm) with pulse duration of 6 ns. The results showed that the typical lifetime of LPP is less than 1.4 μs, and the lifetime of ions is shorter than atoms at ∼10−6 mbar. Temporal features of optical emission showed that the optimized delay times for collecting spectra are from 100 to 400 ns which depended on the corresponding species. For spatial distribution, the maximum LIBS spectral intensity in plasma plume is obtained in the region from 1.5 to 3.0 mm above the sample surface. Moreover, the plasma expansion velocity involving the different species in a multicomponent system was measured for obtaining the proper timing (gate delay time and gate width) of the maximum emission intensity and for understanding the plasma expansion mechanism. The order of expansion velocities for various species is These results could be attributed to the plasma sheath acceleration and mass effect. In addition, an optimum signal-to-background ratio was investigated by varying both delay time and detecting position.

Modeling of a Vertical Tunneling Transistor Based on Graphene–MoS2Heterostructure

In this paper, for the first time, we present a computational study on the electrical behavior of the field-effect tunneling transistor based on vertical graphene–MoS2 heterostructure and vertical graphene nanoribbon–MoS2 heterostructure. Our simulation is based on nonequilibrium Green’s function formalism along with an atomistic tight-binding (TB) model. The TB parameters are obtained by fitting the bandstructure to first-principle results. By using this model, electrical characteristics of device, such as ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio, subthreshold swing, and intrinsic gate-delay time, are investigated. We show that the combination of tunneling and thermionic transport allows modulation of current by four orders of magnitude confirming experimental results. The results indicate that the increase of MoS2 layer numbers leads to a higher ${I}_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio but degrades the intrinsic gate-delay time. Furthermore, it can be observed from the results that as the ribbon width increases the ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of device increases at the cost of a lower ${I}_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio.

A computational study of vertical tunneling transistors based on graphene-WS2 heterostructure

In this paper, for the first time, we present a computational study on electrical characteristics of field effect tunneling transistors based on a vertical graphene-WS2 heterostructure and vertical graphene nanoribbon (GNR)-WS2 heterostructure (VTGNRFET). Our model uses the nonequilibrium Green's function formalism along with an atomistic tight binding (TB) method. The TB parameters are extracted by fitting the bandstructure to first principles results. We show that, due to the advantage of switching between tunneling and thermionic transport regimes, an improvement can be achieved in the electrical characteristics of the device. We find that the increase of the number of WS2 layers enhances the on/off conductance ratio but degrades the intrinsic gate-delay time. The results indicate that the on/off conductance ratio of VTGNRFET increases with decreasing the GNR width.