Gate Bias Stress Test Research Articles

Design of different oxygen content and high performance bilayer In2O3 thin-film transistors at room temperature for flexible electronics

In this study, homojunction bilayer In2O3thin film transistors (TFTs) were prepared by RF-magnetron sputtering at room temperature. Herein, an active channel of bilayer In2O3TFTs are consist of the front channel with lower (poor) oxygen content and the back channel with higher (rich) oxygen content. Therefore, optimizedbilayer In2O3TFT was fabricatedandaμFE of 32.5 cm2/Vs and a small SS of 280 mV/decade, a small VTH of 0.3 Vwere achieved. In addition, small VTH shifts of 0.7 (−1.0) and 0.4 (−1.2) V under gate bias and light illumination stress tests were obtained. Through XPS band structure analysis indicated that the formation of band bending between the channel layers leads to electron injection from the back channel into the front channel, resulting in accumulation of forming carriers near the interface of the bilayer, resulting in increase the μFE of In2O3TFTs. Furthermore, XPS and LFN measurement demonstrate that control the oxygen content can reduced the oxygen-related defects and bulk/interface trap density while controlling the Ne and carrier transport in the bilayer In2O3 film,which enhance the stability of In2O3TFTs. Overall, the high-performance bilayer In2O3TFTshave opena new method to obtaine the flexible electronic devices.

Design Optimization and Reliability Evaluation in 1.2 kV SiC Trench MOSFET with Deep P Structure

In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), charge to breakdown (QBD), and time dependent dielectric breakdown (TDDB) tests were conducted. Also, high temperature gate bias (HTGB) and high temperature reverse bias (HTRB) stress tests were carried out for assembled samples to compare device reliability depending on different designs. For the target design, the promising reliability results were confirmed in both wafer level and assembled samples.

Enhanced electrical performance of InGaSnO thin-film transistors by designing a dual-active-layer structure

In this study, dual-active-layer InGaSnO (IGTO) thin-film transistors (TFTs) were designed, and their electrical properties were investigated. Consequently, compared with the single-layer IGTO (pure Ar) TFTs, the dual-layer IGTO TFTs exhibited improved electrical properties, including a high field-effect mobility of 25.1 cm2 V−1 s−1, a low threshold voltage of 0.8 V, a high on/off current ratio of 1 × 108, a small subthreshold slope of 300 mV/decade, and a low off current. Additionally, the dual-layer IGTO TFTs showed superior stability for small Vth shifts of −1.9 V and 1.8 V under gate bias stress test conditions. Band structure analysis indicated that a thin front layer of IGTO (pure Ar) can provide an appropriate carrier concentration (Ne) near the IGTO (pure Ar)/IGTO (Ar/O2) interface, whereas a thick layer of IGTO (Ar/O2) can control the channel conductance and threshold voltage of IGTO TFTs. Moreover, atomic force microscopy, X-ray photoelectron spectroscopy, and Hall effect measurement results showed that the surface roughness, oxygen vacancies, Ne, and total trap density of IGTO (Ar/O2) films and TFTs were reduced by increasing the oxygen flow rate. Over all, the high performance dual-active-layer IGTO TFTs provides insights that can contribute to developing a new generation of transparent oxide thin-film electronics.

InZnTiON Channel Layer for Highly Stable Thin-Film Transistors and Light-Emitting Transistors.

In this study, we incorporated TiN as a carrier suppressor into an amorphous InZnO channel to achieve stable channels for thin-film transistors (TFTs) and light-emitting transistors (LETs). The low electronegativity and standard electrode potential of the Ti dopant led to a reduction in the number of oxygen vacancies in the InZnO channel. Moreover, the substitution of nitrogen into the oxygen sites of InZnO effectively decreased the excess electrons. As a result, the cosputtering of the TiN dopant resulted in a decrease in the carrier concentration of the InZnO channel, serving as an effective carrier suppressor. Due to the distinct structures of TiN and InZnO, the TiN-doped InZnO channel exhibited a completely amorphous structure and a featureless surface morphology. The presence of oxygen vacancies in the InZnO channel creates trap states for electrons and holes. Consequently, the TFT with the InZnTiON channel demonstrated an improved subthreshold swing and enhanced stability during the gate bias stress test. Furthermore, the threshold voltage shift (ΔVth) changed from 3.29 to 0.86 V in the positive bias stress test and from -0.92 to -0.09 V in the negative bias stress test. Additionally, we employed an InZnTiON channel in LETs as a substitute for organic semiconductors. The reduction in the number of oxygen vacancies effectively prevented exciton quenching caused by hole traps within the vacancies. Consequently, appropriate TiN doping in the InZnO channel enhanced the intensity of the LET devices.

Rational design of oxide heterostructure InGaZnO/TiO2 for high-performance thin-film transistors

In this study, hetero-structured and self-passivated oxide thin film transistors (TFTs) were fabricated, wherein the channel comprised a N2O plasma (a-IGZO:N2O) treated a-IGZO front layer and TiO2 ultra-thin back layer. A high field-effect mobility (μFE) of 40.5 cm2/Vs and small sub-threshold swing (SS) of 250 mV/decade upon a SiO2/Si substrate were achieved using a rational design. Moreover, small threshold voltage shifts (ΔVth) of 0.5 (−0.7) and 0.8 (−0.9) V under gate bias and light illumination stress tests were obtained. Using Si3N4/HfO2 gate dielectrics, μFE and SS were enhanced to 53.6 cm2/Vs and 75 mV/decade, respectively. Experimental observations indicate that the electrons transfer from TiO2 to a-IGZO:N2O layer resulted in the accumulation of free carriers near a-IGZO:N2O/TiO2 interfaces. Additionally, an appropriate N2O treatment reduced the oxygen-related defects and bulk/interface trap density, while controlling the carrier density in the bilayer a-IGZO:N2O/TiO2 TFTs. Furthermore, the ultra-thin TiO2 layer acted as a surface passivation layer that reduced the leakage current and protected the channel from ambient influences. The proposed high-performance hetero-structured a-IGZO:N2O/TiO2 TFTs with superior stability are expected to provide a new and effective approach to obtaining high-performance metal oxide TFTs for application in thin film electronics.

Functional polymeric passivation-led improvement of bias stress with long-term durability of edge-rich nanoporous MoS2 thin-film transistors

Nanoporous patterning of two-dimensional materials using block copolymer lithography has drawn much attention. Lateral edge exposures made by the nanoporous patterning provide electrical and optical characteristics that are different from the original materials. However, nanopatterning processes inevitably generate edge exposure and surface defects that may result in poor reliability and reproducibility of the devices. In this study, we propose a reliable method to passivate nanoporous molybdenum disulfide (MoS2) thin-film transistors (TFTs) using polymer thin films, synthesized by initiated chemical vapor deposition (iCVD) to improve the electrical stability of nanoporous MoS2 TFTs. To this end, functional polymer films of electron-donating poly(1-vinylimidzole) (pVI) and inert poly(1H,1H,2H,2H-perfluorodecyl methacrylate) (pPFDMA) were utilized as passivation layers on nanoporous MoS2 TFTs. An n-type doping effect was observed in the pVI-deposited nanoporous MoS2 film due to the electron-donating imidazole ring, whereas the inert pPFDMA efficiently stabilized the electrical characteristics of the nanoporous MoS2 TFTs. Moreover, the hydrophobic fluoroalkyl chain of the pPFDMA film efficiently prevented oxygen and moisture adsorption on the nanoporous MoS2. The superior passivation effect of the pPFDMA layer was confirmed using gate-bias stress tests and long-term storage tests under ambient conditions.

High performance and illumination stable In2O3 nanofibers-based field effect transistors by doping praseodymium

Although different kinds of one dimensional (1D) metal oxide nanofibers (MO-NFs) based field effect transistors (FETs) have been developed in recent years, their intrinsic deficiency in illumination instability are not addressed yet, which further prevented their application in practical life. In this work, due to the outstanding performance of suppressing oxygen vacancies and the blue light down-conversion with low charge transfer transition energy, praseodymium (Pr) is demonstrated an ideal candidate to dope into In2O3 NFs for both transferring the depletion mode to the enhancement mode and enhancing the illumination stability of the FETs. The optima In2O3 NFs-based FET was achieved by doping with 3 mol% Pr and exhibited an excellent electrical performance with a carrier mobility of 6.92 cm2V−1s−1, an on/off current ratio of ∼5.4 × 107, threshold voltage of 5.2 V, and subthreshold swing of 0.37 V/dec. Moreover, the FETs exhibited good illumination stability under 3600 s negative gate bias stress test with illumination (NBIS). Finally, the FET was also used as a switch to bright the LED in this work, demonstrating its great promise of Pr-doped In2O3 NFs in future one-dimensional electronic devices.

Back-Channel-Etched IGZO TFTs With Cu-Based Multilayer Electrodes Using MoAl Alloy and MoMn Alloy as Buffer Layers

We report high-performance IGZO TFTs with MoAl/Cu/MoAl and MoMn/Cu/MoMn three-layer electrodes, where MoAl or MoMn alloy is used as the buffer layer. The multilayer electrode has good electrical properties and can effectively prevent the oxidation and diffusion of the middle Cu layer. In addition, the multilayer electrode can be etched in a PAN etchant solution and match the etching rate with Cu. Based on these MoAl/Cu/MoAl and MoMn/Cu/MoMn electrodes, vacuum-processed IGZO TFTs exhibit a turn-on voltage of 0 V, an on-off ratio of 10⁹, and a mobility of 10.7 cm² V⁻¹ s⁻¹ after annealing at 115 °C in N₂. Under the gate bias stress test, devices with MoMn electrodes, which exhibit a small threshold voltage shift, show better performance than those with MoAl electrodes. The presented studies may provide another option for the Cu buffer layer.

Reliability of p-Type Pi-Gate Poly-Si Nanowire Channel Junctionless Accumulation-Mode FETs

In this study, p-type Pi-gate (PG) poly-Si nanowire channel junctionless accumulation-mode (JAM) field-effect transistors (FETs) were successfully fabricated and their reliability was investigated. The reliability of these PG JAM FETs was found to be dependent on the effective channel doping concentration (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch,eff</sub> ). Through a negative gate bias stress (NGBS) test, we found that degradation in the average subthreshold swing (A.S.S.) and shift in the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) increases as the N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch,eff</sub> of the PG JAM FETs decreases. Furthermore, the PG JAM FETs with a lower N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch,eff</sub> show the more severe rate of deterioration in the transconductance (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) and ON current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ). By increasing N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch,eff</sub> to reduce the electric field ( E-field) on the gate oxide and tune the carrier transport mechanism in the poly-Si nanowire channel, a better immunity against the NGBS test in the p-type PG JAM FETs can be achieved under a gate overdrive voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GOD</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH,initial</sub> = -3.5 V) to perform the NGBS test.

Investigation of electrical performance and operation stability of RF-sputtered InSnZnO thin film transistors by oxygen-ambient rapid thermal annealing

We investigated the electrical properties and operational stability of amorphous indium-tin-zinc-oxide (a-ITZO) thin-film transistors (TFTs). We fabricated the a-ITZO TFTs using deposition by radio frequency sputtering at room temperature followed by a rapid thermal annealing (RTA) process at different temperatures and oxygen pressure (P O2). This is a more practical annealing route compared to a conventional furnace. Based on film densification and oxygen vacancy optimization, the a-ITZO TFTs exhibited 9.8 cm2 Vs−1, 0.82 V/decade and 1.39 V, for saturation mobility, sub-threshold swing and threshold voltage, respectively. Operation stability tests and hysteresis behavior of a-ITZO TFTs suggest that oxygen vacancy concentration of a-ITZO thin films gradually decreases under higher P O2, consequently affecting the threshold voltage and the shift seen after a gate bias stress test. This observation suggests that gate bias stress and hysteresis stability of an a-ITZO device is due to the effect of oxygen-controlled pressure in the RTA process. This a-ITZO TFTs electrical characterization qualitatively coincides with x-ray photoelectron spectroscopic analyses of oxygen vacancy concentration in a-ITZO thin films. Thus, our systematic a-ITZO thin film optimization using the oxygen-ambient RTA process is a practical basis for high-performance amorphous oxide semiconductor TFT post-annealing methods.

Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

Effect of Simplified-Single-Step Microwave Annealing in O2 Ambient for High Performance Solution-Processed In–Ga–Zn–O Thin Film Transistors

In this study, we propose a simplified-single-step microwave annealing (S₃-MWA) technique in an O₂ ambient, which is a low thermal budget heat treatment method, for the application in solutionprocessed amorphous indium-gallium-zinc oxide (a-IGZO) thin films. For the application of solutionprocessed a-IGZO films in electronic devices, a multi-step post deposition annealing (PDA) process, which involves baking at low temperatures to vaporize the solvent, and high temperature conventional thermal annealing to remove defects in the film, is essential. To simplify the multi-step PDA process, we studied the possibility of reducing the thermal process temperature and time by replacing it with a single-step PDA process using microwave equipment. The electrical properties were compared to investigate the effect of the annealing method and ambient on solution-processed a-IGZO thin film transistors (TFTs). As a result, the S₃-MWA-processed a-IGZO TFTs were found to exhibit superior electrical characteristics in comparison with the conventional PDA-processed devices. It was found that the O₂ ambient process not only shortened the annealing time of S₃-MWA but also improved the electrical properties. Furthermore, the S₃-MWA was superior to the conventional PDA in the evaluation of device reliability under a gate bias stress test. The S₃-MWA process in the O₂ ambient was also responsible for improving the reliability of solution-processed a-IGZO TFTs. Therefore, we confirmed that the proposed S₃-MWA in the O₂ ambient is a more effective and promising technique than conventional PDA for the low thermal budget treatment of solution-processed a-IGZO TFTs.

A Novel Non-Intrusive Technique for BTI Characterization in SiC mosfets

Threshold voltage ( V TH) shift due to bias temperature instability (BTI) is a well-known problem in SiC mosfet s that occurs due to oxide traps in the SiC/SiO2 gate interface. The reduced band offsets and increased interface/fixed oxide traps in SiC mosfet s makes this a more critical problem compared to silicon. Before qualification, power devices are subjected to gate bias stress tests after which V TH shift is monitored. However, some recovery occurs between the end of the stress and V TH characterization, thereby potentially underestimating the extent of the problem. In applications where the SiC mosfet module is turned off with a negative bias at high temperature, if the V TH shift is severe enough, there may be electrothermal failure due to current crowding since parallel devices lose synchronization during turn- on . In this paper, a novel method that uses the forward voltage of the body diode during reverse conduction of a small sensing current is introduced as a technique for monitoring V TH shift and recovery due to BTI. This non-invasive method exploits the increased body effect that is peculiar to SiC mosfet s due to the higher body diode forward voltage. With the proposed method, it is possible to non-invasively assess V TH shift dynamically during BTI characterization tests.

16‐3: Investigation of Mechanical Stress and Gate Bias Stress on Flexible Dual‐gate a‐IGZO Thin Film Transistors

The effects of mechanical stress and gate bias stress on dual‐gate a‐IGZO thin‐film transistors on a flexible substrate were investigated. Both tensile and compressive stresses increased free electrons and deep states in a‐IGZO. More deep defects will be formed under strong tensile stress, while small compressive stress can repair defects in the relatively poor quality etch‐stop layer. Moisture still influence the stability even for the TFTs with etch stop layer and passivation layer under gate bias stress test.

Effects of Yttrium Doping on a-IGZO Thin Films for Use as a Channel Layer in Thin-Film Transistors

Amorphous In−Ga−Zn−O (a-IGZO) has been studied as a channel layer in thin-film transistors (TFTs). To improve the bias-induced instability of a-IGZO TFTs, we introduced yttrium with high bond enthalpy by magnetron co-sputtering system. The Y-doped a-IGZO (a-IGZO:Y) films show relatively lower carrier concentration and higher Hall mobility, which is due to the suppression of oxygen vacancies caused by Y doping. The a-IGZO:Y showed a relatively higher transmittance in the visible light region compared to non-doped IGZO, which could be due to the decrease of shallow defect levels caused by oxygen vacancy in the band gap. The a-IGZO without Y doping showed dramatic changes in electrical properties as times progressed (over 240 h); however, the a-IGZO:Y showed no significant changes. The a-IGZO:Y TFTs demonstrated a more stable driving mode as exhibited in the positive gate bias stress test even though the values of VTH and SS were slightly degraded.

Stability Improvement of Nitrogen Doping on IGO TFTs under Positive Gate Bias Stress and Hysteresis Test

Thin-film transistors (TFTs) using indium-gallium-oxide (IGO) semiconductor materials as channel layers were fabricated. In this study, nitrogen was introduced in the process of channel deposition to investigate its effect on device performance. The experimental results showed that moderate nitrogen doping can significantly improve the device stability under positive gate bias stress owing to the reduction of oxygen vacancies. Furthermore, for the purpose of understanding the influence of different doping levels, the nitrogen doping ratio was modulated in ascending order from 0 sccm to 5 sccm. Among the fabricated c-IGO TFTs, the one with 2 sccm nitrogen doping exhibited the least threshold voltage shift. In addition, the hysteresis measurement further confirmed that the interface traps between the channel and the dielectric were significantly passivated in nitrogen-doped TFT. In this regard, the method of in-situ nitrogen doping was certified to serve an efficient way of fabricating a passivation-free TFT and improve the device stability simultaneously.

Multi- and single-step in situ microwave annealing as low-thermal-budget techniques for solution-processed indium–gallium–zinc oxide thin films

In this study, low-thermal-budget in situ microwave annealing of solution-processed indium–gallium–zinc oxide (IGZO) thin films was investigated as a potential alternative to the conventional high-thermal-budget annealing process. The low-temperature baking and high-temperature post-deposition annealing of the solution-processed IGZO film were continuously performed using the same microwave equipment, leading to a reduced heat treatment processing time and temperature. We compared the electrical characteristics of IGZO thin film transistors (TFTs) produced using single- and multi-step in situ microwave annealing methods with those of TFTs manufactured via the conventional annealing method and found that the proposed single-step microwave annealing method yielded TFTs with electrical characteristics better than those of the TFTs fabricated using the multi-step and conventional annealing methods. In addition, the reliability was evaluated by conducting positive and negative gate bias stress tests, in which the IGZO TFTs manufactured using the proposed heat treatment method proved superior to those fabricated via the conventional heat treatment method. We investigated the effects of heat treatment on the composition and energy band structures of the IGZO films by performing x-ray photoelectron spectroscopy analysis and found that the proposed in situ microwave annealing method is more effective than the conventional method in solution processing.

The influence on electrical characteristics of amorphous indium tungsten oxide thin film transistors with multi-stacked active layer structure

In order to effectively enhance the carrier mobility and device stability, simultaneously, a multi-stacked active layer of thin film transistor with a novel type of channel material, amorphous indium-tungsten-oxide, is proposed in this work. Atop-cappingoxygen-rich indium-tungsten-zinc-oxide thin film is used for suppressing the influence of the molecular adsorption or desorption from the ambient at the back channel in the gate bias stress test. In addition, a bottom-bufferingoxygen-rich indium-tungsten-zinc-oxide thin film is deposited to avoid the oxygen vacancy generation during the following thermal process. On the other hand, a 1-nm thick WO3 film is inserted between the high-k gate insulator and active layer, which play important roles as interfacial layer for improving the interface quality and keeping the stability of front channel film. Besides, an HfO2 dielectric film is chosen as gate insulator for realizing the low-voltage operation. As a result, the novel tungsten doped channel material with both-sideoxygen-rich active layer exhibits a high ION/IOFF current ratio of ~6 × 107 for low gate leakage current, attributing to the top-cappingoxygen-rich thin film. Then, a high field-effect mobility of ~27.9 cm2/V.s and a low sub-threshold swing of 0.079 V/decade are achieved by the good interface quality. This structure with both-sideoxygen-rich active layer exhibits its potential application for the future high-resolution and large-size display manufacture.

Bias temperature instability and condition monitoring in SiC power MOSFETs

Threshold voltage shift due to bias temperature instability (BTI) is a major concern in SiC power MOSFETs. The SiC/SiO2 gate dielectric interface is typically characterized by a higher density of interface traps compared to the conventional Si/SiO2 interface. The threshold voltage shift that arises from BTI has significant implications on the reliability of SiC power MOSFETs, hence, techniques for detecting the change in electrical parameters due to gate oxide degradation are desirable. Using accelerated high temperature gate bias stress tests on SiC MOSFETs, it has been shown that the output and transfer characteristics are affected by BTI. This paper presents the impact BTI induced threshold voltage shift on the forward voltage of the SiC MOSFET body diode during third quadrant operation. Using the forward voltage of the body diode during reverse conduction of low currents, threshold voltage shift can be detected, hence, the impact of BTI can be evaluated. The implications of the body diode forward voltage shift on junction temperature measurements are also studied in the context of TSEPs. The findings in this paper are important for engineers seeking to implement condition and health monitoring techniques on SiC power devices.

(Invited) High Density IGZO Film for Highly Reliable TFT By Inductively Coupled Plasma Sputtering Technology in Low Temperature Process

Transparent amorphous oxide semiconductors (TAOS) represented by IGZO have excellent characteristics such as high mobility, and a low off current compared with amorphous Si (a-Si) semiconductor. Furthermore, TAOS can be deposit by standard sputtering systems. Large area fabrication at a lower cost than low temperature polysilicon semiconductor (LTPS) is also possible. Therefore, there is a possibility to manufacture a display with high definition / low power consumption at low cost. However, many studies have shown the insufficient electrical reliability of IGZO TFTs. Although application to flexible displays is expected, in the conventional fabrication of IGZO TFTs, post annealing processes at a high temperature of 300°C is necessary. Therefore, low temperature formation of IGZO TFT is required. The inductively coupled plasma (ICP) sputtering system under development is characterized by its capacity to deposit high density films and high target usage efficiency. Figure 1 shows the schematic of the ICP sputtering system. In this system, the antenna is installed in the chamber, and a high-frequency generator is connected to the antenna. ICP is generated in the chamber by applying high-frequency to the antennas. In this device, since the magnetic field is not arranged on the target, ICP diffuses uniformly into the chamber. In order to perform sputtering, a negative bias voltage is applied to the target, ions are pulled from the ICP, and the target material is deposited on the substrate. The target material was uniformly consumed, and usage efficiency showed a very high value of 85%. In addition, since antennas and targets are connected to independent power supplies, independent control is possible. By increasing the high-frequency power applied to the antennas and controlling the plasma density, deposition is possible without lowering deposition rate even at low target voltage. We considered that independent control of RF power and target voltage is important because both may be related to film density. The density of the IGZO films deposited by changing the RF power and the target voltage was obtained using X-ray reflectivity. The results are shown in figures 2 (a) and (b). The relationship between RF power and film density could not be confirmed. When the target voltage was increased, the film density decreased. Therefore, performing deposition at a lower target voltage yielded a high-density IGZO film. Under all conditions, the IGZO films exhibited a film density of more than 6.0 g/cm3. In this study, the bottom-gate top-contact TFTs were fabricated by low-temperature process using high-density two-layer structure IGZO film deposited by ICP sputtering system, and the transfer characteristics and reliability were examined. Bottom-gate top-contact TFTs structure is shown in figure 3. The two-layer structure IGZO (In:Ga:Zn = 1:1:1) films were deposited by ICP sputtering system with different O2/Ar gas ratio condition at room temperature. The TFTs were subjected to post annealing at 150°C or 200°C or 250°C for 2 h under the O2/N2 mixed gas atmosphere. The passivation of the photosensitive polysilsesquioxane was coated using a straightforward solution process for samples annealed at 250°C, and baked at 250°C. The TFTs were subjected to a positive gate bias stress test (PBS) by applying a gate voltage (V gs) of 20 V, for a total stress time of 10000 s. Figure 4 show transfer characteristics of each post annealing temperature. When no annealing is performed, the TFT shows switching behavior but the threshold voltage (V th) became negative. When post annealing was carried out, V th became positive. Transfer characteristics at annealing temperature of 150°C to 250°C exhibited similar values. The electric field effect mobility of V ds = 0.5 V obtained from the transfer characteristic at post annealing temperature of 150°C was 7.9 to 8.8 cm2/Vs. The results of PBS are shown in figure 5. Threshold voltage shift (ΔV th) was used as an index of reliability. ΔV th of post annealing temperature of 150°C, 200°C and 250°C were 0.73 V, 0.75 V, 0.66 V, respectively. A sample with post annealing temperature at 250°C coated with polysilsesquioxane passivation has a ΔV th = 0.09 V. The reason why TFTs showing comparatively high-mobility can be fabricated even through a low-temperature process is considered to be the deposition of high-density films with low vacancy after deposition by the ICP sputtering system. In addition, it was found that the TFT with the annealing temperature of 150°C has the same reliability as the TFT with the annealing temperature of 250°C. We are set to demonstrate TFTs showing high-reliability at low-temperature process by using passivation that can be coated even at low temperatures. Figure 1