AlGaAs-GaAs Heterojunction Bipolar Transistors Research Articles

Simulation of the thermal response of self-heating power transistors using a time step adaption method

An implementation of the Rosenbrock-Wanner scheme with embedded time-step adaption in the thermal simulation of AlGaAs-GaAs heterojunction bipolar transistors (HBT) is presented. The simulations are based on discrete 3-D models of the device using the finite integration technique for the solution of the thermal equation. The thermally coupled current response of the device in DC operation is obtained by a nonlinear EM/sub 3/ model. Several simulations featuring the thermal crosstalk and the current collapse instability demonstrates the utility of time-step adaption in simulating the alternating slow-fast transients in multifinger HBTs.

A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip

A byte-slice datapath for exploring multi-chip RISC processor development in AlGaAs-GaAs heterojunction bipolar transistor (HBT) technology has been designed, fabricated and tested. The circuits are implemented using differential current-mode logic (CML) and emitter-coupled logic (ECL) with signal swings of 250 mV. Each datapath chip contains a single slice, including an 8-bit by 32-word single-port register file with a 230-ps read access time, and an 8-bit carry-select adder with a 140-ps select path and a 380-ps ripple-carry path. Each unpackaged die was tested using an at-speed boundary scan test scheme. The register file and adder carry chain are also implemented in a special test chip for accurate performance characterization of these critical circuits.

Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy

Integrated-circuit interconnect characterization is growing in importance as devices become faster and smaller. Along with this trend, interconnect geometry is becoming more complex, consisting of an increasing number of wiring levels. Accurate numerical extraction of three-dimensional (3-D) interconnect capacitance is essential for achieving design targets in the multigigahertz digital regime. Interconnect-capacitance extraction is complicated by the presence of inhomogeneous layers with differing dielectric constant. Dielectric anisotropy as well is common in many low-/spl kappa/ polymeric dielectrics used in high-performance ICs. A CAD procedure using the novel floating random-walk extractor QuickCAP is presented. Our procedure is efficient enough to extract a substantial amount of a chip's 3-D wiring. We include as well dielectric anisotropy and inhomogeneity. The procedure is not based on effective conductor geometry or on a finite-sized conductor library but rather on the entire 3-D layout, accounting for actual local variations in conductor separations and shapes. We then apply our procedure to an experimental circuit vehicle implemented in AlGaAs-GaAs heterojunction bipolar transistor current-mode logic. This vehicle is used to validate the accuracy of our CAD procedure in predicting circuit speed. Measured and predicted test-capacitor values and ring-oscillator propagation times agreed generally to within 2-4%. To verify results on a larger digital circuit, we analyzed all interconnects in an adder carry-chain oscillator using our procedure. Predicted propagation delays were generally within 3% of measurement.

Low-frequency noise characterization of self-aligned AlGaAs-GaAs heterojunction bipolar transistors with a noise corner frequency below 3 kHz

To find dominant 1/f noise sources, generalized noise analyses have been performed for self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBT's). For shorted base-emitter condition, the resistance fluctuation 1/f noise is dominant, while for open base-emitter condition, the base-emitter current 1/f noise is dominant. The collector-emitter 1/f current noise, though generally considered an important noise source, is negligible. The resistance 1/f noise stems mainly from the emitter resistance fluctuation. Our noise-reduction work is focused on the reduction of the base-emitter current 1/f noise. We have investigated the base-emitter-current noise properties as a function of emitter-base structure and surface passivation condition. It is found that the surface-recombination 1/f noise can be significantly reduced by the heterojunction launcher of the abrupt junction with 30% aluminum mole fraction emitter. The depleted AlGaAs ledge surface passivation further suppresses the surface-recombination currents. Consequently, we have achieved a very low 1/f noise corner frequency of 2.8 kHz at the collector current density of 10 kA/cm/sup 2/. The dominant noise source of the HBT is not a surface-recombination current, but a bulk current noise. This is the lowest 1/f noise corner frequency among the III-V compound semiconductor transistors, and is comparable to those of low-noise Si bipolar junction transistors (BJTs).

Failure mechanism and SPICE modeling of [formula omitted] HBT long-term current instability

The long-term current instability of AlGaAs GaAs heterojunction bipolar transistor (HBT) is studied, and the physical mechanism contributing to such a behavior is investigated. Based on this, a model capable of predicting the HBT long-term current drift and mean time to failure (MTTF) is developed. In addition, such a model is implemented into SPICE circuit simulator, thus allowing the simulation of HBT circuits subjected to an electrical and thermal stress condition.

Effects of H 2 plasma exposure on [formula omitted] heterojunction bipolar transistors

GaAs AlGaAs heterojunction bipolar transistors with highly C-doped base layers ( p = 7 × 10 19 cm −3) were exposed to Inductively Coupled Plasma (ICP) or Electron Cyclotron Resonance (ECR) H 2 plasmas at different source powers and rf chuck powers to simulate the effects of ion damage and hydrogen passivation during CH 4 H 2 dry etch fabrication of the devices. The HBT d.c. current gain decreases with increasing rf chuck powers in both types of reactor because of increased ion damage. This gain is less affected at high ICP source power because of the suppression of cathode dc self-bias and hence ion energy, but is more degraded at high ECR source power since cathode d.c. self-bias increases under these conditions. The ICP tool is preferred for CH 4 H 2 dry etching of HBTs because there is less disruption of the electrical properties of these devices.

Perimeter and bulk recombination currents in GaAs homojunction diodes and [formula omitted] heterojunction bipolar transistors after surface processing

The emitter-mesa surface (perimeter) and emitter-base bulk recombination currents, in GaAs AlGaAs heterojunction bipolar transistors (HBTs), are known to degrade device performance at low applied voltages, where these currents dominate. To study the effects of the etchant (used in defining the diode mesas) on the perimeter recombination current, GaAs homojunction diodes were given a short time etch in a selection of wet chemical etchants and the effect on the edge leakage current investigated. It was observed that the edge leakage current could be modified by the process used to fabricate the mesa. Following encouraging results, the work was extended to include GaAs AlGaAs HBTs, and an investigation was undertaken of the effects on recombination at the perimeter of the emitter-mesa and on bulk recombination current, with surface treatments. A simple model was used to separate the bulk and perimeter contributions from the recombination current. The surface recombination current was strongly dependent on the process used to define the mesa, and can therefore, by appropriate processing, be reduced.

Lightly doped emitter HBT for low-power circuits

We report an approach to reduce the base-emitter capacitance in AlGaAs-GaAs heterojunction bipolar transistors (HBT's) by adding a lightly doped emitter (LDE) region together with appropriate planar (/spl delta/) doping region to a conventional base-emitter junction. This improves both the f/sub t/ and /spl beta/ for low collector current density (J/sub c/) operation while preserving the high peak f/sub t/ at high J/sub c/. When applied to a current mode logic 128/129 programmable prescaler, the LDE HBT results in a reduction in power dissipation and improved bandwidth without any circuit modifications.

HBT high-frequency modeling and integrated parameter extraction

This paper presents, for the first time, a novel nonlinear model for accurate dc, small-signal, and noise characterization of AlGaAs-GaAs heterojunction bipolar transistors (HBTs). A new set of equations are introduced to take into account the bias, temperature, and frequency dependencies in noise calculations. This model provides significant improvement in predicting small-signal noise for HBT-based circuits. We also present an integrated method for accurate HBT model parameter extraction by fitting the dc, multibias S-parameter, and noise measurements simultaneously. The extracted model provides accurate small-signal, dc current, and noise characteristics. This technique is general and can be used for parameter extraction of other microwave devices such as MESFETs and high electron mobility transistors (HEMTs). Our new HBT model is validated using devices from different foundries. An integrated parameter extraction technique is demonstrated for a foundry HBT and excellent results are obtained.

Microwave and thermal characteristics of backside-connectedflip-chip power heterojunction bipolar transistors

Measured and modelled characteristics are reported for a new geometry for contacting AlGaAs-GaAs heterojunction bipolar transistors (HBTs), which provides lower thermal resistance and lower emitter inductance than does the conventional approach. Common-emitter connected HBTs are mounted emitter side down on a metal heatsink, which also serves as electrical ground. Connections to the base and collector are made with substrate vias that extend through the GaAs substrate from the backside of the wafer. This configuration was measured to have values of thermal resistance as small as 0.23 K/mW for a 132 /spl mu/m/sup 2/ emitter area HBT, in agreement with simulations. An output power per unit emitter area of 2.9 mW//spl mu/m/sup 2/ (total power of 370 mW) at 9 GHz was observed.

Failure mode analysis of [formula omitted] HBTs using electrostatic discharge method

The failure modes of AlGaAs GaAs heterojunction bipolar transistors (HBTs) showing increases of base leakage current found during the bias and temperature reliability test have been examined and analysed by using an electrostatic discharge (ESD) method. In the examination for HBT having an emitter of 2 × 20 μm, increases of a base leakage current have been observed when an ESD of around 100 V is applied through a base-emitter junction. Furthermore, increases of a collector leakage current have been observed with the additional ESD of around 150 V. Since no fatal effects for the transistor amplification are found in the high current region, the degradations are concluded to be responsible to the local damages of the base layer at the edge of base-emitter junction. Applying the Wunsch-Bell model to the damaged region, the temperature is estimated to be in a range from 400 to 550°C. It is thought that thermal destruction occurs in a base layer.

Current transport in [formula omitted] heterojunction bipolar transistors operating between 300 and 500 K

The current transport in AlGaAs GaAs heterojunction bipolar transistors (HBTs) operating in the temperature range of 300–500 K is investigated based on an analytical model including the lattice heating effect. It is found that an uneven increase in the base and collector currents gives rise to the current gain degradation at high temperatures. In addition, the study suggests that the effect of lattice heating becomes more important if the HBT area is reduced and/or the ambient temperature is increased. Experimental data and results simulated from a device simulator are included in support of our finding.

Formula omitted] HBTs with buried SiO 2 in the extrinsic collector

This paper presents novel structures of AlGaAs GaAs heterojunction bipolar transistors with buried SiO 2 in the extrinsic collector. Transistor layer structures are grown by molecular beam epitaxy on GaAs substrates patterned with SiO 2. Single-crystal and polycrystal structures are grown in the SiO 2 openings and on the SiO 2, respectively. Due to the low dielectric constant of SiO 2, about one-third that of GaAs, and the complete carrier depletion of polycrystalline GaAs, a 40–65% reduction in the base-collector capacitance is realized without sacrificing the current gain or cutoff frequency.

Thermal stabilization of [formula omitted] power HBTs using n-Al xGa 1− xAs emitter ballast resistors with high thermal coefficient of resistance

The use of n-Al x Ga 1− x As an emitter ballast layer material for AlGaAs GaAs heterojunction bipolar transistors (HBTs) is proposed and demonstrated. A high thermal coefficient of resistance can be obtained owing to the temperature dependence of the relative populations of the conduction band Γ, L and X valleys if the Al mole fraction x of the n-Al x Ga 1 − x As ballast layer is adjusted to give the appropriate intervalley energy separation. Al 0.3Ga 0.7As and Al 0.35Ga 0.65As emitter ballast layers incorporated in HBT structures have an average thermal coefficient of resistance of about 8 × 10 −3°C −1, which is significantly higher than that of GaAs ballast resistances. The temperature stabilizing effect of n-Al x Ga 1− x As ballast layer is assessed by measuring the d.c. current-voltage characteristics of single-emitter finger and multi-emitter finger HBTs. Large power HBTs with integrated n-Al x Ga 1− x As ballast resistors have been fabricated and an output power of up to 10 W at 0.9 GHz has been obtained.

Novel fabrication of self-aligned [formula omitted] and [formula omitted] microwave power heterojunction bipolar transistors

Self-aligned processing of high efficiency power heterojunction bipolar transistors (HBTs) using implant isolation, selective wet and dry etching for mesa formation, plasma-enhanced chemical vapor deposited SiN x for sidewall spacers and through-wafer via connections is reported. GaAs AlGaAs and GaAs InGaP HBTs were grown by Metal Organic Molecular Beam Epitaxy utilizing carbon for high, well-confined base doping and tin for n-type doping to reduce emitter contact resistance. GaAs AlGaAs HBTs with twelve 2 × 15 μm 2 double-emitter finger devices produced power-added efficiencies of 63%, power gain of 10 dB and output power of 1.7 W at 4 GHz. The results of power measurements at 4–12 GHz for GaAs InGaP HBTs with common emitter and common base configuration are also reported.

Combined effects of graded and setback layers on the [formula omitted] HBT current-voltage characteristics

The combined effects of graded and setback layers ( W G and W I) on the AlGaAs GaAs heterojunction bipolar transistor (HBT) d.c. performance are investigated, and an anlaytical model which can describe the behavior of such HBTs is presented. The HBT base and collector currents accounting for the variation of the conduction and valence bands due to the presence of W G and W I are also calculated. It is shown that including W G and W I actually degrades the HBT current gain at low current levels. The current gain at high current levels, on the other hand, can be enhanced if W I = 150 A ̊ and 0 ≤ W G ≤ 300 A ̊ or W I = 0 and 150 A ̊ ≤ W G ≤ 300 A ̊ are used. The model predictions compare favorably with results calculated from a numerical model.

A comprehensive optical characterization method for high-performance n-p-n AlGaAs-GaAs heterojunction bipolar transistors

We report a comprehensive optical wafer evaluation technique for C-doped n-p-n heterojunction bipolar transistors (HBT) using low temperature photoluminescence spectroscopy. The correspondence between the optically determined parameters at the wafer level and the electrical device parameters is demonstrated. The hole density in the base of transistor structures was obtained from optical transitions in the p/sup +/-GaAs layer exploiting the bandgap narrowing effect. Furthermore, our experimental studies, which combine optical and electrical measurements, show that a photovoltaic effect observed in the optical spectrum measures the strength of carrier recombination processes in the emitter-base heterojunction region. Because interface recombination strongly affects the dc current gain of these devices, photoluminescence spectroscopy of epitaxial wafers provides critical information on HBT device parameters prior to device fabrication.

A 6-b, 4 GSa/s GaAs HBT ADC

A GaAs-AlGaAs heterojunction bipolar transistor (HBT) process was developed to meet the speed, gain, and yield requirements for analog-to-digital converters (ADC's). The HBT has current gain of over 100 and f/sub T/ and f/sub MAX/ of over 50 GHz. A 6-b, 4 GSa/s (4 giga-samples/s) ADC was designed and fabricated in this process. The ADC uses an analog folding architecture, includes an on-chip master-slave track-and-hold (T/H) circuit, and provides Gray-encoded digital outputs. The ADC achieves 5.6 effective bits at 4 GSa/s, a faster clock rate than any noninterleaved semiconductor ADC reported to date. It has a resolution bandwidth (the frequency at which effective bits has dropped by 0.5 b) of 1.8 GHz at 4 GSa/s, higher than any published ADC. The chip operates at up to 6.5 GSa/s. GaAs HBT IC's are especially prone to high operating temperatures. This led to reliability problems that were overcome by the use of a fast DC thermal simulator written for this project. A SPICE model for self-heating effects is also described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Thermally stable WTiAu non-alloyed ohmic contacts on In 0.5Ga 0.5As for GaAsAlGaAs heterojunction bipolar transistor applications

This paper demonstrates WTiAu as a thermally stable, low resistance, non-alloyed, emitter ohmic contact for GaAsAlGaAs heterojunction bipolar transistor applications. The minimum W layer thickness required for low contact resistance and long-term thermal stability was obtained. A W layer 900 Å thick yielded the lowest contact resistance ( R c = 0.045 ω mm ) with a high degree of uniformity after (1) a collector ohmic contact rapid thermal annealing cycle at 420 °C and (2) 500 h at 250 °C. Secondary ion mass spectroscopy results indicate that In outdiffusion contributes to the thermal instability when thinner W layers are used.

The effect of emitter layer variations on the current gain of AlGaAs-GaAs heterojunction bipolar transistors grown by chemical beam epitaxy

AlGaAs-GaAs heterojunction bipolar transistors have been fabricated with current gains > 200 for devices with emitter dimensions of 2×2 μm 2. The epitaxial layers were grown using chemical beam epitaxy and were npn single heterojunction transistors with aluminum grading in the base. The high current gains observed in these devices are attributed to leaving a thin AlGaAs emitter layer (30–60 nm) over the entire base mesa and alloying through this layer to make base contact. This reduces the surface recombination currents to the extent that no significant decreases of current gain were observed with decreasing emitter size. Values of f t and f max from 50–110 GHz were measured with f max values dependent on the base doping which was in the (2−6) × 10 19 cm -3 range. The epitaxial layers were grown on 3 inch diameter semi-insulating substrates in a VG Semicon 4200 CBE system. Room temperature photoluminescence intensities were used to determine the optimum growth conditions for both the n-Al 0.3Ga 0.7As emitters and the p-Al x Ga 1− x As graded bases. SIMS, DCD X-ray diffraction, Hall effect measurements and photoreflectance were also used to evaluate the grown layers. Variations in emitter composition, doping and thickness were studied as well as the effects of growth interrupts at the emitter-base junction. Digital circuits that operate at data rates above 10 Gb/s> have been demonstrated. These include 4:1 multiplexers, 1:4 demultiplexers, dividers, preamplifiers and decision circuits.