Future Technology Nodes Research Articles

Diffusion and activation of dopants in silicon and advanced silicon-based materials**Invited paper.

A quantitative description of the transient diffusion and activation of boron during post-implantation annealing steps is one of the most challenging tasks in the simulation of silicon doping processes. In industrially relevant situations, simulations needs to address diffusion at extrinsic concentrations, the agglomeration of self-interstitials, and the formation of boron-interstitial clusters. This paper describes the experimental work performed or used to calibrate model parameters as independently as possible. The combined model is then applied to ultra-shallow junction formation by annealing boron implanted into crystalline or preamorphized silicon. In comparison to bulk silicon, much less is known about diffusion of dopants in SiGe and germanium which are considered as technological options for future technology nodes. Therefore, dedicated experiments were performed to clarify open points in the diffusion behaviour of dopants in these materials.

Electromigration in damascene copper interconnects of line width down to 100 nm

The electromigration reliability of Cu interconnects of line width down to 100 nm is investigated. The activation energy for the electromigration failure of the line width of 150 nm is found to be 1.2 eV, and the Cu/Ta interface is found to be the fast diffusion path for the line widths of 100 nm and 150 nm without any catastrophic void formation in the lines. An atomic flux divergence-based finite element model is used to explain the observed failure sites. Both the resistivity and electromigration reliability of the fabricated interconnects are found to be promising for future technology nodes.

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si1-xGex S/D) technology. Experimental results on Si1-xGex S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si1-xGex is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si1-x Gex and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si1-xGe x S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes

Comparison of Trimming Techniques for Sub-Lithographic Silicon Structures

The trimming of electron beam features is investigated to explore the limits of this scaling technique for the fabrication of nano-scale devices. The semiconductor industry, in particular, needs features below 50 nm, e.g., for extremely small gates for future technology nodes. In addition, sub-lithographic structures are required for other device concepts, such as the fin-type field effect transistor (FinFET). The trimming of very thin layers of calixarene, an organic resist material, as well as an oxide-like resist (hydrogen-silesquioxane) were investigated and extremely small feature sizes, well below 10 nm, were achieved. Resist structures down to 4 nm in width and silicon features of about 8 nm have been successfully fabricated. Different trimming procedures utilizing plasma resist trimming, etching of Tetraethylorthosilicate (TEOS) hard-masks in hydrofluoric acid (HF) and sacrificial oxidation were compared and, for the first time, a comprehensive study of these techniques applied to sub-10 nm-structuring is presented. In summary, results prove the potential of the trimming procedures investigated here, each of which has specific applications.

Ultrathin-body strained-Si and SiGe heterostructure-on-insulator MOSFETs

The combination of channel mobility-enhancement techniques such as strain engineering with nonclassical MOS device architectures, such as ultrathin-body (UTB) or double-gate structures, offers the promise of maximizing current drive while maintaining the electrostatic control required for aggressive device scaling in future technology nodes. The tradeoff between transport enhancement and OFF-state leakage current is compared experimentally for UTB MOSFETs in two types of materials: 1) strained Si directly on insulator (SSDOI) and 2) strained Si/strained Si/sub 1-z/Ge/sub z/ (z=0.46-0.55)/strained Si heterostructure-on-insulator (HOI). SSDOI of moderate strain level (e.g. /spl sim/ 0.8%) yields high electron-mobility enhancements for all electron densities, while high strain levels (e.g. /spl sim/ 1.6%) are required to obtain hole-mobility enhancements at high inversion charge densities. HOI is demonstrated to have similar electron-mobility characteristics to SSDOI, while hole mobilities are improved and can be maintained at high inversion charge densities. Hole mobility in strained channels with thickness below 10 nm is studied and compared for SSDOI and HOI. As the channel thickness is reduced, mobility decreases, as in unstrained silicon-on-insulator (SOI), though hole-mobility enhancements are demonstrated into the ultrathin-channel regime. Increased OFF-state leakage currents are observed in HOI compared to SSDOI and SOI. For a 4-nm-thick buried SiGe layer, leakage is reduced relative to devices with thicker SiGe channels.

<B>In-Situ Characterizarion of Interfaces-Induced Resistivity in Nanometric Dimensions</B>

AbstractTo improve the speed of integrated circuits it is highly important to minimize the electrical resistivity of their interconnects. However, as the dimensions of the interconnects approach the mean free path of the electrons, a substantial rise in resistivity occurs due to additional electron scatterings from grain boundaries and interfaces. To investigate the role of interfaces, in-situ resistivity measurements were preformed for thin copper films on which different materials were deposited. The resistivity was monitored before and after the deposition, enabling to observe the changes as a new top interface was created. Among the materials tested, tantalum resulted in the highest resistivity increase. This fact is of special importance since this material and its nitride serve today as the common diffusion barrier for copper metallization. Titanium resulted in a smaller resistivity increase, but still higher than that of a free copper surface in vacuum. The developed approach enables to test the influence of different diffusion barriers on copper resistivity. With the continuously shrinking dimensions of copper interconnects, this factor will have an increasing importance in future technology nodes.

Effect of buried Si∕SiO2 interface on dopant and defect evolution in preamorphizing implant ultrashallow junction

P -type ultrashallow junctions are widely fabricated using Ge preamorphization prior to ultralow-energy boron implantation. However, for future technology nodes, issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). An understanding of the effect of the buried Si∕SiO2 interface on defect evolution, electrical activation, and diffusion is needed in order to optimize the preamorphization technique. In the present study, boron has been implanted in germanium preamorphized silicon and SOI wafers with different preamorphizing implant conditions. Subsequent to implantation an isothermal annealing study of the samples was carried out. Electrical and structural properties were measured by Hall-effect and secondary-ion-mass spectroscopy techniques. The results show a variety of interesting effects. For the case where the Ge preamorphization end-of-range defects are close to the buried oxide interface, there is less dopant deactivation and less transient-enhanced diffusion, due to a lower interstitial gradient towards the surface.

Scaling of Statistical and Physical Electromigration Characteristics in Cu Interconnects

AbstractEven after the successful introduction of Cu-based metallization, the electromigration (EM) failure risk has remained one of the important reliability concerns for most advanced process technologies. Ever increasing operating current densities and the introduction of low-k materials in the backend process scheme are some of the issues that threaten reliable, long-term operation at elevated temperatures. The main factors requiring attention and careful control are the activation energy related to the dominating diffusion mechanism, the resulting median lifetimes, and the lognormal standard deviation of experimentally acquired failure time distributions. Whereas the origin of the EM activation energy and the behavior of median lifetimes with continuing device scaling are relatively well understood, detailed models explaining the origin and scaling behavior of the lognormal standard deviation are scarce. The statistical behavior of EM-induced void sizes and resulting lifetime distributions appear to be explainable by geometrical variations of the void shapes and the consideration of kinetic aspects of the EM process. Using these models, expected lifetime distributions for future technology nodes can be simulated from current, experimentally obtained void size and lifetime distributions. These simulations have to include geometrical factors of the EM test structures and actual, on-chip interconnects, as well as kinetic aspects of the mass transport process, such as differences in interface diffusivity between the lines. By extrapolating the expected lifetime distributions for future technology nodes from current EM data, it is possible to predict when insertion of new process schemes, such as Cu-alloys and/or metallic coating of the Cu/passivation interface is required.

Effect of B dose and Ge preamorphization energy on the electrical and structural properties of ultrashallow junctions in silicon-on-insulator

AbstractFormation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next generations of CMOS devices, particularly for source-drain extensions. For p-type dopant implants (boron), a promising method of increasing junction abruptness is to use Ge preamorphizing implants prior to ultra-low energy B implantation and solid-phase epitaxy regrowth to re-crystallize the amorphous Si. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Previous results have shown that the buried Si/SiO2 interface can improve dopant activation, but the effect depends on the detailed preamorphization conditions and further optimization is required. In this paper a range of B doses and Ge energies have been chosen in order to situate the end-of-range (EOR) defect band at various distances from the back interface of the active silicon film (the interface with the buried oxide), in order to explore and optimize further the effect of the interface on dopant behavior. Electrical and structural properties were measured by Hall Effect and SIMS techniques. The results show that the boron deactivates less in SOI material than in bulk silicon, and crucially, that the effect increases as the distance from the EOR defect band to the back interface is decreased. For the closest distances, an increase in junction steepness is also observed, even though the B is located close to the top surface, and thus far from the back interface. The position of the EOR defect band shows the strongest influence for lower B doses.

Solid-phase epitaxial regrowth of a shallow amorphised Si layer studied by X-ray and medium energy ion scattering

Solid-phase epitaxial regrowth (SPER) of Si amorphised by ion implantation is considered as a potential solution for the fabrication of ultra-shallow junctions for future technology nodes of Si CMOS devices. In the present work, a series of Epi-Si samples amorphised by ultra-low energy As implantation was investigated by monitoring the lattice recovery during SPER and the simultaneous evolution of implantation-induced defects using the combined capabilities of X-ray scattering methods and medium energy ion scattering. Annealing temperatures between 550 and 700 °C and times from 10 to 200 s were chosen to characterise different stages of the SPER as well as the onset of defect annealing. Small defect clusters were detected in the end-of-range damage region of the implanted samples and layer-by-layer regrowth of the amorphised region was clearly observed. The complementary nature of the information obtained by the two methods is demonstrated. This study confirms that the high dose As implant causes the slowing down of the SPER rate in Si.

Understanding the role of buried Si/SiO 2 interface on dopant and defect evolution in PAI USJ

For CMOS technology, generations beyond the 65 nm node a major goal is achieving highly activated, ultra-shallow and abrupt profiles. In the case of p-type (boron) implants, one method to achieve this is using Ge preamorphization (PAI) prior to ultra-low energy B implantation. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Understanding the strong impact of the buried Si/SiO 2 interface, will enable tests of fundamental models on defect evolution, electrical activation and diffusion. In the present study, boron has been implanted in germanium-preamorphized silicon and SOI wafers. Subsequent to implantation, an isochronal and isothermal annealing study of the samples was carried out. Electrical and structural properties were measured by Hall effect and SIMS techniques. The results show a range of effects in both substrate types, including TED and deactivation driven by interstitials from the end-of-range (EOR) defects. However, in the SOI material there is a lower boron deactivation and the EOR defects are eliminated at a lower thermal budget in SOI than in the bulk silicon due to competition between the upper SOI interface and the Si surface which both act as sinks for interstitials.

Raman spectroscopy of strain in subwavelength microelectronic devices

The use of Raman spectroscopy to determine strain in microelectronic devices is intrinsically limited by optical diffraction. The critical issue is not the limited spatial resolution itself, but rather the averaging of inhomogeneously strained regions reducing the sensitivity significantly. To eliminate this effect, we took advantage of the near-field properties of an illuminated subwavelength periodic structure. As it is possible to restrict the investigated volume to the transistor channel only, the sensitivity increases significantly. The technique is advantaged by a very small pitch of the devices, and therefore can be also used in the future technological nodes.

Angled implants for controlling gate–source/drain extension: A TCAD modeling study

TCAD process simulations are carried out on NMOS and PMOS to study the effect of high tilt in source/drain extension (SDE) implants and millisecond, non-melt laser anneals on junction depth and gate–SDE overlap. High tilt implants along with millisecond laser anneals are proposed as a solution for future device technology nodes (<65nm) to obtain very shallow (Xj<15nm), abrupt (<3nm/dec) junctions, with a degree of freedom to optimize gate overlap. TCAD modeling shows upon increasing the tilt angle from 0° to 30° the gate/extension overlap can increase from 2nm to over 10nm, without loss of shallow junction depth. Angled high tilt arsenic implants followed by laser anneals are also performed to study the junction depth and sheet resistance variations with tilt angle. Channeling issues at tilt angles are also analyzed and a solution based on Ge pre-amorphization is proposed to circumvent this problem. The TCAD results indicate that high tilt implant is a critical requirement on the low energy, high current implanter, and that such feature is important for controlling the gate–extension overlap with millisecond (“diffusion-light”) laser anneal technologies.

Electrical activation of solid-phase epitaxially regrown ultra-low energy boron implants in Ge preamorphised silicon and SOI

The formation of highly activated ultra-shallow junctions (USJ) is one of the key requirements for the next generation of CMOS devices. One promising method for achieving this is the use of Ge preamorphising implants (PAI) prior to ultra-low energy B implantation. In future technology nodes, bulk silicon wafers may be supplanted by Silicon-on-Insulator (SOI), and an understanding of the Solid Phase Epitaxial (SPE) regrowth process and its correlation to dopant electrical activation in both bulk silicon and SOI is essential in order to understand the impact of this potential technology change. This kind of understanding will also enable tests of fundamental models for defect evolution and point-defect reactions at silicon/oxide interfaces. In the present work, B is implanted into Ge PAI silicon and SOI wafers with different PAI conditions and B doses, and resulting samples are annealed at various temperatures and times. Glancing-exit Rutherford Backscattering Spectrometry (RBS) is used to monitor the regrowth of the amorphous silicon, and the resulting redistribution and electrical activity of B are monitored by SIMS and Hall measurements. The results confirm the expected enhancement of regrowth velocity by B doping, and show that this velocity is otherwise independent of the substrate type and the Ge implant distribution within the amorphised layer. Hall measurements on isochronally annealed samples show that B deactivates less in SOI material than in bulk silicon, in cases where the Ge PAI end-of-range defects are close to the SOI back interface.

Nickel Germanosilicide Contacts Formed on Heavily Boron Doped&amp;lt;tex&amp;gt;$rm Si_1-xrm Ge_x$&amp;lt;/tex&amp;gt;Source/Drain Junctions for Nanoscale CMOS

Formation of source/drain junctions with a small parasitic series resistance is one of the key challenges for CMOS technology nodes beyond 100 nm. A new source/drain technology based on selective deposition of heavily in situ doped Si/sub 1-x/Ge/sub x/ layers was recently developed in this laboratory. This paper presents formation and structural characterization of self-aligned nickel germanosilicide contacts formed on heavily boron doped Si/sub 1-x/Ge/sub x/ alloys. The results show that thin NiSi/sub 1-x/Ge/sub x/ contacts with a resistivity of /spl sim/25 /spl mu//spl Omega/-cm can be formed on Si/sub 1-x/Ge/sub x/ alloys at temperatures as low as 350/spl deg/C. However, the low resistivity and the structural integrity of the NiSi/sub 1-x/Ge/sub x/ films can be maintained up to a maximum temperature of 450/spl deg/C. At higher temperatures, Ge out-diffusion from NiSi/sub 1-x/Ge/sub x/ grains results in interface roughening and NiSi spikes. If the maximum processing temperature is kept within 400/spl deg/C, p/sup +/-n junctions with excellent leakage behavior can be formed. A minimum contact resistivity of 2/spl times/10/sup -8/ /spl Omega/-cm/sup 2/ is demonstrated for Ge concentrations above /spl sim/40%, which can be linked to the smaller semiconductor bandgap and high boron activation under the metal contact. The results suggest that NiSi/sub 1-x/Ge/sub x/ contacts formed on Si/sub 1-x/Ge/sub x/ junctions have the potential to satisfy the contact resistivity requirements of future CMOS technology nodes.

A Physically Based Compact Gate&amp;lt;tex&amp;gt;$Chbox--V$&amp;lt;/tex&amp;gt;Model for Ultrathin (EOT&amp;lt;tex&amp;gt;$sim1~hbox nm$&amp;lt;/tex&amp;gt;and Below) Gate Dielectric MOS Devices

A computationally efficient and accurate physically based gate capacitance model of MOS devices with advanced ultrathin equivalent oxide thickness (EOT) oxides (down to 0.5 nm explicitly considered here) is introduced for the current and near future integrated circuit technology nodes. In such a thin gate dielectric regime, the modeling of quantum-mechanical (QM) effects simply with the assumption of an infinite triangular quantum well at the Si-dielectric interface can result in unacceptable underestimates of calculated gate capacitance. With the aid of self-consistent numerical Schro/spl uml/dinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E/sub 1//spl prop/F/sub ox//sup 2/3/), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration. The filling of excited states consistent with Fermi statistics has been addressed. The quantum-corrected gate capacitance-voltage (C-V) calculations have then been tied directly to the Fermi level shift as per the definition of voltage (rather than, for example, obtained indirectly through calculation of quantum corrections to the charge centroids offset from the interface). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO/sub 2/, Si/sub 3/N/sub 4/ and high-/spl kappa/ (e.g., HfO/sub 2/) gate dielectrics on (100) Si with EOTs down to /spl sim/1.3 nm. The compact model has also been adapted to address interface states, and poly depletion and poly accumulation effects on gate capacitance.

Low voltage stress-induced leakage current in 1.4–2.1 nm SiON and HfSiON gate dielectric layers

This work examines stress-induced leakage current (SILC) in both ultrathin silicon oxynitride and hafnium silicate dielectric layers for future MOS technology nodes. SILC is confirmed to be sense voltage dependent and is observed to have a dependence on bulk oxide traps for both dielectric layers. A possible explanation for the sense voltage dependence is provided. SILC is found to be a greater problem in the HfSiON layers, because of its magnitude relative to the initial current. This results in the leakage current density quickly becoming greater than that for SiON. The SILC is found to have a transient component in the HfSiON layers, indicating the presence of slow electron traps. Finally, the correlation between SILC and drive current reduction is demonstrated. It is concluded that in the high-k layers investigated in this study, SILC seems more of a problem than dielectric breakdown.

Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells

An ‘atomistic’ circuit simulation methodology is developed to investigate intrinsic parameter fluctuations introduced by discreteness of charge and matter in decananometer scale MOSFET circuits. Based on the ‘real’ doping profile, the impact of random device doping on 6-T SRAM static noise margins are discussed in detail for 35 nm physical gate length devices. We conclude that SRAM may not gain all the benefits of future bulk CMOS scaling, and new device architectures are needed to scale SRAM down to future technology node.

In Search of “Forever,” Continued Transistor Scaling One New Material at a Time

This work looks at past, present, and future material changes for the metal-oxide-semiconductor field-effect transistor (MOSFET). It is shown that conventional planar bulk MOSFET channel length scaling, which has driven the industry for the last 40 years, is slowing. To continue Moore's law, new materials and structures are required. The first major material change to extend Moore's law is the use of SiGe at the 90-nm technology generation to incorporate significant levels of strain into the Si channel for 20%-50% mobility enhancement. For the next several logic technologies, MOSFETs will improve though higher levels of uniaxial process stress. After that, new materials that address MOSFET poly-Si gate depletion, gate thickness scaling, and alternate device structures (FinFET, tri-gate, or carbon nanotube) are possible technology directions. Which of these options are implemented depends on the magnitude of the performance benefit versus manufacturing complexity and cost. Finally, for future material changes targeted toward enhanced transistor performance, there are three key points: 1) performance enhancement options need to be scalable to future technology nodes; 2) new transistor features or structures that are not additive with current enhancement concepts may not be viable; and 3) improving external resistance appears more important than new channel materials (like carbon nanotubes) since the ratio of external to channel resistance is approaching /spl sim/1 in nanoscale planar MOSFETs.

Mainstream rapid thermal processing for source–drain engineering from first applications to latest results

Rapid thermal processing (RTP) technology has been commercially available in the semiconductor industry for about 30 years. Already in 1957, e.g., a solar furnace with a parabolic Al reflector was designed. Despite this, it took several decades for RTP of semiconductors to penetrate the market. Over the last decade, RTP has become a mature application. As a replacement of standard furnaces, it provides outstanding ambient control and very short heating cycles with the highest ramp rates for promotion of desired processes such as implant activation, silicide formation or oxide growth while suppressing unintended processes like diffusion or surface degradation. In the field of ultra-shallow junction (USJ) formation, which is necessary to avoid short channel effects arising during continued scaling of CMOS devices, RTP is indispensable. With the introduction of CoSi 2 as the source–drain contact material and its transition to NiSi for future technology nodes, RTP delivers unique benefits in terms of ambient control and single wafer processing capability. In the current paper, we will present the development and potential of RTP throughout this era and show latest results in USJ annealing as well as source–drain contact formation down to the 90 and 65 nm technology node of the ITRS2003, respectively.