Future Technology Nodes Research Articles

Characterization and modeling of structural properties of SiGe/Si superlattices upon annealing

Stacked multichannel or nanowire CMOS transistors are foreseen as viable options in future technology nodes. Superior electric performances and a relative immunity to short channel effects have already been demonstrated in such devices. They rely on (i) the epitaxy of SiGe/Si superlattices, (ii) the anisotropic etching of the source and drain (S/D) blocks and the channels, and (iii) the high degree of selectivity that can be achieved when laterally etching the SiGe sacrificial layers. The voids left by the removal of SiGe are then conformally filled by HfO2/TiN/poly-Si gates, leading to the formation of multichannel devices. Doping elements can be included in situ in the SiGe layers during the epitaxial step in order to achieve a proper S/D doping after annealing. Precise knowledge of the diffusion behavior of all species is then crucial to understand and tailor final device performance. In this work, we investigated the properties of intrinsic or in situ doped (with B, C, or P) SiGe/Si superlattices upon annealing, using several characterization techniques, such as x-ray diffraction, x-ray reflectivity, time-of-flight-secondary ion mass spectrometry, and dark-field electron holography; as well as diffusion simulation tools such as S-Process. The combined analysis and simulation approaches allowed a complete characterization of the studied structures upon annealing. In the first step, the diffusion of both germanium and dopants was observed experimentally and quantified with simulation. Their diffusion mechanisms were also studied. In the second step, the evolution of the strain distribution upon annealing was experimentally monitored and simulated to quantify the strain relaxation in such structures.

Prediction and Comparison of High-Performance On-Chip Global Interconnection

As process technology scales, numerous interconnect schemes have been proposed to mitigate the performance degradation caused by the scaling of on-chip global wires. In this paper, we review current on-chip global interconnect structures and develop simple models to analyze their architecture-level performance. We propose a general framework to design and optimize a new category of global interconnect based on on-chip transmission line (T-line) technology. We perform a group of experiments using six different global interconnection structures to discover their differences in terms of latency, energy per bit, throughput, area, and signal integrity over several technology nodes. Our results show that T-line structures have the potential to outperform conventional repeated RC wires at future technology nodes to achieve higher performance while using less power and improving the reliability of wire communication. Our results also show that on-chip equalization is helpful to improve throughput, signal integrity, and power efficiency.

Atomic Layer Deposition of High-κ Dielectrics on Sulphur-Passivated Germanium

High mobility channels are currently being explored to replace the silicon channel in future CMOS technology nodes. However, until now the promising bulk properties are very difficult to translate into high transconductance due to a poor passivation of the interface between the gate dielectric and the channel. We have studied the S-passivation of the germanium surface combined with various high-permittivity dielectric gate stacks. (NH4)2S is used to achieve a S-terminated Ge surface. We found that the Ge/S/Al2O3 interface is superior to both the Ge/S/ZrO2 and Ge/S/HfO2 interfaces. Bi-layer stacks consisting of Ge/S/Al2O3/HfO2 or Ge/S/Al2O3/ZrO2 were built to achieve a gate stack with low EOT (Equivalent Oxide Thickness). In these bi-layer stacks, the Al2O3 thickness is reduced to a minimum without degradation of the interface properties. Rather thick Al2O3 interlayers (∼ 2 nm) are needed due to island growth on S-terminated Ge surface. A pMOSFET was built using a bi-layer gate stack (Ge/S/Al2O3/HfO2). The peak mobility of this device is > 200 cm2/Vs at an EOT of 1.5 nm.

Interface and Border Traps in Ge-Based Gate Stacks

A critical issue for the successful integration of Ge devices into future high-performance technology nodes is the electrical passivation of the Ge surface. We have examined this electrical passivation in terms of interface and border traps for several Ge-based gate stacks, where we varied amongst others the GeO2 thickness, the high-k material and the Post Deposition Anneal (PDA). The GeO2 thickness seems to have the largest impact, and an inverse relation between the density of interface traps Dit and border traps Nbt exists for GeO2 layers up to ~2 nm. We found that the most optimal passivation is achieved by using an (almost) oxide-free surface as this would result in the lowest Nbt. Although such a surface is characterized by a high mid-gap Dit, this can be improved by performing the correct PDA. We conclude that the most promising oxide-free surface is obtained after an H2S treatment.

The evolution of standard cell libraries for future technology nodes

Evolvable Hardware has been a discipline for over 15 years. Its application has ranged from simple circuit design to antenna design. However, research in the field has often been criticised for not addressing real world problems. Intrinsic variability has been recognised as one of the major challenges facing the semiconductor industry. This paper describes an approach that optimises designs within a standard cell library by altering the transistor dimensions. The proposed approach uses a Multi-objective Genetic Algorithm to optimise the device widths within a standard cell. The designs are analysed using statistically enhanced transistor models (based on 3D-atomistic simulations) and statistical Spice simulations. The goal is to extract high-speed and low-power designs, which are more tolerant to the random fluctuations present in current and future technology nodes. The results show improvements in both the speed and power of the optimised standard cells and that the impact of threshold voltage variation is reduced.

Physical analysis of breakdown in high-κ/metal gate stacks using TEM/EELS and STM for reliability enhancement (invited)

In this invited paper, we demonstrate how physical analysis techniques that are commonly used in integrated circuits failure analysis can be applied to detect the failure defects associated with ultrathin gate dielectric wear-out and breakdown in high-κ materials and investigate the associated failure mechanism(s) based on the defect chemistry. The key contributions of this work are perhaps focused on two areas: (1) how to correlate the failure mechanisms in high-κ/metal gate technology during wear-out and breakdown to device processing and materials and (2) how the understanding of these new failure mechanisms can be used in proposing “design for reliability” (DFR) initiatives for complex and expensive future CMOS nanoelectronic technology nodes of 22 nm and 15 nm. Hf-based high-κ materials in conjunction with various gate electrode technologies will be used as main examples while other potential high-κ gate materials such as cerium oxide (CeO 2) will also be demonstrated to further illustrate the concept of DFR.

Effluent Management for Non-Oxidizing Plasma Strip Processes

This paper reports on the techniques employed to control the re-deposition of the partially dissociated organic photoresist (PR) by-products in advanced non-oxidizing strip processes developed to meet the PR removal requirements of future technology nodes. System features, such as the design of heated process chamber walls and an on-board, RF-based oxygen plasma effluent abatement system are described in detail. The performance of these features to prevent or eliminate hydrocarbon buildup and manage effluent with non-oxidizing strip processes is also presented and discussed.

Dielectric reliability of 70 nm pitch air-gap interconnect structures

Scaling air-gap interconnects to 70 nm pitch is demonstrated for the first time by combining air-gap technology (SiO 2 etch-back and non-conformal CVD) and the double patterning approach. A capacitance reduction of 45% was measured on the air-gaps compared to the SiO 2 reference. The reliability performance of the air-gaps was then evaluated and it was found that the structures exceeded 10 years lifetime at 2 MV/cm, almost matching the performance of SiO 2 interconnects. Air-gaps could therefore make a promising low-RC solution for future technology nodes.

13nm gate Intentional Defect Array (IDA) wafer patterning by e-beam lithography for defect metrology evaluation

Fabricating and inspecting wafers with defects intentionally created at known locations enables a quantitative and repeatable methodology to assess the performance of in-line defect metrology tools with regard to ITRS requirements. With each successive design node, in-line defect inspection technology becomes more challenging and there are significant concerns about the capability to support 2× and 1× technology nodes. In this paper we report progress at the College of Nanoscale Science and Engineering (CNSE) in Albany, New York, to print and process advanced defect metrology test structures intended to represent a 13nm gate length. The ISMI 13nm gate Intentional Defect Array (IDA) has lithographic defects in known locations with sizes varying from 25% to 400% of the corresponding 32nm node, resulting in defect sizes ranging from 8 to 128nm. The film stack consists of 30nm TEOS hard mask, 60nm polysilicon, 35nm TiN and 2nm HfO2 on top of silicon. The patterns are first printed (at 1×) on a 300mm wafer using a Vistec VB300 electron beam lithography tool with a high resolution HSQ resist (commercially known as Dow Corning XR-1541). The features are subsequently etched to transfer the pat- tern from the resist onto the wafer stack. The resulting IDA wafers are intended to help ISMI engineers investigate next generation metrology techniques and identify solutions for future technology nodes.

Physics of Gate Modulated Resonant Tunneling (RT)-FETs: Multi-barrier MOSFET for steep slope and high on-current

A new concept of nanoscale MOSFET, the Gate Modulated Resonant Tunneling Transistor (RT-FET), is presented and modeled using 3D Non-Equilibrium Green’s Function simulations enlightening the main physical mechanisms. Owing to the additional tunnel barriers and the related longitudinal confinement present in the device, the density of state is reduced in its off-state, while remaining comparable in its on-state, to that of a MOS transistor without barriers. The RT-FET thus features both a lower RT-limited off-current and a faster increase of the current with V G , i.e. an improved slope characteristic, and hence an improved I on/ I off ratio. Such improvement of the slope can happen in subthreshold regime, and therefore lead to subthreshold slope below the kT/q limit. In addition, faster increase of current and improved slope occur above threshold and lead to high thermionic on-current and significant I on/ I off ratio improvement, even with threshold voltage below 0.2 V and supply voltage V dd of a few hundreds of mV as critically needed for future technology nodes. Finally RT-FETs are intrinsically immune to source–drain tunneling and are therefore promising candidate for extending the roadmap below 10 nm.

Variable-shaped e-beam lithography enabling process development for future copper damascene technology

To realize fast and efficient integrated circuits the interconnect system gains an increasing importance. In particular, this is the case for logic and processor circuits with up to 12 metallization layers. In order to optimize this technology and the according processes it is desirable to generate flexible test structures in small lot production. In opposition to standard optical lithography using masks, Electron Beam Direct Write (EBDW) lithography can rapidly deliver special test structures at low cost. Furthermore, critical dimensions of future technology nodes which are not yet manufacturable by standard optical lithography tools can be produced. In this paper we demonstrate the potential of the 50kV variable shaped EBDW cluster for patterning of future back-end-of-line (BEOL) structures on full 200mm wafers. The patterned wafers have been used to develop next generation copper damascene interconnect processes for critical dimensions down to 50nm.

Recouping etch rates in pulsed inductively coupled plasmas

Pulsed rf plasmas are increasingly being employed for plasma etching at future technological nodes. Although the plasma uniformity usually improves with pulsing, the lower time-averaged power decreases the etch rate and the lower throughput is undesirable. It is therefore important to evaluate different strategies to restore higher etch rates while retaining the advantages of pulsed plasmas. In this work, the impact of varying pulsing modes in an inductively coupled plasma on plasma characteristics and feature profile evolution are discussed using the results from a two-dimensional reactor scale plasma model coupled to a Monte Carlo based feature profile model. Results are discussed for poly-Si etching in an Ar/Cl2 gas mixture. The consequences of source-only and bias-only pulsing modes on discharge characteristics, ion energy distributions (IEDs) to the wafer, and feature profile evolution are discussed. Although the etch depth rates were found to be higher for source-only pulsing compared to the synchronized (source and bias) pulsing mode, the higher ion energies in the afterglow period during source-only pulsing may also increase ion bombardment damage. Compensation of power may allow for increased etch depth rates while retaining the benefits of synchronized pulsing. Further, power compensation level can be varied to achieve fine tuning of the IEDs to the wafer.

A CMOS Compatible Carbon Nanotube Growth Approach

ABSTRACTIn future technology nodes, 22nm and below, carbon nanotubes (CNTs) may provide a viable alternative to Cu as an interconnect material. CNTs exhibit a current carrying capacity (up to 109 A/cm2), whilst also providing a significantly higher thermal conductivity (SWCNT ~ 5000 WmK) over Copper (106 A/cm2 and ~400WmK). However, exploiting such properties of CNTs in small vias is a challenging endeavor. In reality, to outperform Cu in terms of a reduction in via resistance alone, densities in the order of 1013 CNTs/cm2 are required. At present, conventional thermal CVD of carbon nanotubes is carried out at temperatures far in excess of CMOS temperature limits (400 C). Furthermore, high density CNT bundles are most commonly grown on insulating supports such as Al2O3 and SiO2 as they can effectively stabilize metallic nanoparticles at elevated temperatures but this limits their application in electronic devices. To circumvent these obstacles we employ a remote microwave plasma to grow high density CNTs at a temperature of 400 C on conductive underlayers such as TiN. We identify some critical factors important for high-quality CNTs at low temperatures such as control over the catalyst to underlayer interaction and plasma growth environment while presenting a fully CMOS compatible carbon nanotube synthesis approach

Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design

Six-transistor SRAM cells have served as the workhorse embedded memory for several decades. However, with aggressive technology scaling, designers find it increasingly difficult to guarantee robust operation at low voltages because of the worsening process variation. This article presents circuit techniques pursued by industry to overcome SRAM scaling challenges in future technology nodes.

III-V CMOS technologies on Si platform

ABSTRACTThe heterogeneous integration of III-V semiconductors with the Si platform is expected to provide high performance CMOS logic for future technology nodes because of high electron mobility and low electron effective mass in III-V semiconductors. However, there are many technology issues to be addressed for integrating III-V MOSFETs on the Si platform as follow; high-quality MOS interface formation, low resistivity source/drain formation, and high-quality III-V film formation on Si substrates. In this paper, we present several possible solutions for the above critical issues of III-V MOSFETs on the Si platform. In addition, we present the III-V CMOS photonics platform on which III-V MOSFETs and III-V photonics can be monolithically integrated for ultra-large scale electric-optic integrated circuits.

VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

We present a novel approach for the on-chip generation of a fault-tolerant clock. Our method is based on the hardware implementation of a tick synchronization algorithm from the distributed systems community. We discuss the selection of an appropriate algorithm, present the refinement steps necessary to facilitate its efficient mapping to hardware, and elaborate on the key challenges we had to overcome in our actual ASIC implementation. Our measurement results confirm that the approach is indeed capable of creating a globally synchronized clock in a distributed fashion that is tolerant to a (configurable) number of arbitrary faults. This property facilitates eliminating the clock as a single point of failure. Our solution is based on purely asynchronous design, obviating the need for crystal oscillators. It is capable of adapting to parameter variations as well as changes in temperature and power supply–properties that are considered highly desirable for future technology nodes.

Continuum simulation of solid phase epitaxial regrowth of amorphized silicon including most advanced physical interactions

AbstractSolid‐phase‐epitaxial regrowth (SPER) of Si amorphized by ion implantation is considered as a potential solution for the fabrication of highly‐activated ultra‐shallow junctions for future technology nodes of Si CMOS devices. In the frame of 32 and 22 nm technologies node development, SPER occurs after amorphizing implantations used in source/drain regions. To get an accurate simulation of dopant activation and junction depth position, a suitable continuum SPER model, implemented into a commercial simulator, is now mandatory. This TCAD model must consider the different physical effects associated with SPER: silicon regrowth rate, dopants redistribution snow plough effect, and interaction with silicon point defects. In this work, using a previously established model, we have implemented an improved physically based model for SPER and, several formulations have been developed to enable a robust/accurate modeling of the recrystallization velocity. It takes into account the direct interaction between amorphous/crystalline interface kinetics and point defects, and a regrowth rate dependent on temperature. Simulation results of dopant concentration profiles are in good agreement with experimental data and can provide important insight for optimizing the bulk silicon process as well in one dimension as two dimensions.

Study of Alternative Plasma Strip Techniques for Advanced Photoresist Removal

This paper reports on the investigation and development of two alternative plasma strip processes to meet the photoresist (PR) removal requirements of future technology nodes. Experimental results show that new plasma strip approaches have comparable crust breakthrough and removal capabilities as O2/N2:H2 and fluorine-containing strip processes, but achieve significantly lower silicon oxidation, which is comparable to, or even lower than that of an N2:H2-only plasma process. Improved residue removal capability and very low metal (TiN and TaN) oxidation values have also been achieved. SIMS analyses of implanted silicon wafers processed with the new strip approaches have shown minimal dopant loss and profile changes. This work demonstrates that these novel plasma strip approaches are viable candidates for meeting the demanding wafer cleaning requirements of the 32nm technology node and beyond.

Length scaling of carbon nanotube transistors

Carbon nanotube field-effect transistors are strong candidates in replacing or supplementing silicon technology. Although theoretical studies have projected that nanotube transistors will perform well at nanoscale device dimensions, most experimental studies have been carried out on devices that are about ten times larger than current silicon transistors. Here, we show that nanotube transistors maintain their performance as their channel length is scaled from 3 µm to 15 nm, with an absence of so-called short-channel effects. The 15-nm device has the shortest channel length and highest room-temperature conductance (0.7G₀) and transconductance (40 µS) of any nanotube transistor reported to date. We also show the first experimental evidence that nanotube device performance depends significantly on contact length, in contrast to some previous reports. Data for both channel and contact length scaling were gathered by constructing multiple devices on a single carbon nanotube. Finally, we demonstrate the performance of a nanotube transistor with channel and contact lengths of 20 nm, an on-current of 10 µA, an on/off current ratio of 1 x 10⁵, and peak transconductance of 20 µS. These results provide an experimental forecast for carbon nanotube device performance at dimensions suitable for future transistor technology nodes.

Electrothermal theory of photomodulated optical reflectance on active doping profiles in silicon

The electrical characterization of the source and drain extension regions of complementary metal oxide semiconductor (CMOS) transistors is highlighted in the international technology roadmap for semiconductors (ITRS) as a major challenge for future technology nodes. In practice, there is a clear need for techniques which are simultaneously accurate, nondestructive, fast, local, and highly reproducible. The photomodulated optical reflectance (PMOR) technique has shown to be a very promising candidate to solve this need. However, even though this technique has been widely studied on homogeneous bulk material and on as-implanted (i.e., unannealed) doping profiles, the extension toward active doping profiles requires a detailed investigation (due to the presence of a built-in electric field). In this paper, after performing an in-depth investigation of the optical and transport models involved in a PMOR experiment, we derive an analytical theory to explain the PMOR signal behavior observed on active doping profiles. In the optical model, we show that only the electrorefractive Drude and thermorefractive effects are to be considered for red and near-infrared wavelengths on Si. In the transport model, we begin the discussion with the study of homogeneous Si substrates. We show that, due to the high carrier injection induced by the lasers, the only important effects are, for the free carriers, the Auger recombinations, the (ambipolar) diffusion and the bandgap narrowing-induced quasidrift; the thermoelectric effects being negligible. Based on the results on homogeneous substrates and on the assumption that the quasi-Fermi levels are flat through the space-charge region, we derive an analytical formula for PMOR signals on active doping profiles. We discuss this formula based on experimental PMOR data measured on active doping profiles with a simple boxlike shape. This formula proves to be in good qualitative agreement with the experimental data both when the power of the pump laser is varied (power curves) and when the distance between the lasers is changed (offset curves). We also show that, for the formula to be quantitative, a very good knowledge of the bandgap profile throughout the sample would be required.