Functional Fault Model Research Articles

A Test Design Methodology for Protocol Testing

Communication protocol testing can be done with a test architecture consisting of remote Lower Tester and local Upper Tester processes. For real protocols, tests can be designed based on the formal specification of the protocol which uses an extended finite state machine model. The specification is transformed into a simpler form consisting of normal form transitions. It can then be modeled by a control and a data flow graph. The graphs are decomposed into subtours and data flow functions, respectively. Tests are designed by considering parameter variations of the input primitives of each data flow function and determining the expected outputs. The methodology gives complete test coverage of all data flow functions and control paths in the specification. Functional fault models are proposed for functions that are not formally specified.

Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams

This correspondence presents a test generation methodology for VLSI circuits described at the functional level. A VLSI circuit is modeled as a network of functional modules such as registers, adders, RAM's, and MUX's. The functions of the individual modules are described using binary decision diagrams. A functional fault model is developed independent of the implementation details of the circuit. A generalized D algorithm is proposed for generating tests to detect functional as well as gate-level faults. Algorithms which perform fault excitation, implication, D propagation, and line justification on the functional modules are also described.

On generating tests for microprossors

This paper presents a systematic method to generate tests for microprocessors. A general model for the microprocessor is developed and it is represented by a set of mechanisms implementing various microprocessor functions. Recommendations facilitating the test generation for the data manipulation mechanisms are given. The data manipulation control mechanisms and their faults are modelled, and the test detection conditions and the test generation procedure are developed and justified. The data storage and transfer mechanism and the data transfer control mechanisms realising the register selection and the data interchange control are considered. For these mechanisms, functional fault models are proposed, and test generation procedures are developed to detect any fault in the fault model.

Characterization and Testing of Physical Failures in MOS Logic Circuits

Studies indicate that the conventional stuck-at fault model is inadequate for modeling the effects of physical failures on MOS circuits. The authors illustrate various types of non-stuck-at behavior, such as indeterminate logic levels, timing errors, and alteration of logic functions. They discuss the generation of tests for detecting the failures in simple and complex MOS circuits. An advantage of testing for failures at the circuit level is that in some cases it may be possible to utilize the structural properties of the circuit to design a much simpler test set compared to one that is based on a gatelevel description of the circuit. The authors outline a methodology whereby functional fault models are derived by studying the effects of physical failures at the circuit level for functional modules.

Fault diagnosis of bit-slice processor

This paper proposes a microdiagnostic procedure for efficient fault diagnosis of bit-slice processors that are formed by an array of identical bit-slice processors. A test generation procedure for testing the entire array simultaneously instead of testing single slice, one after another, is presented, which is based on the high functional fault model and restricted multiple slice fault assumption within an array. Fault detection and fault location procedures using the generated test sequence are also presented. Using these procedures, a test microprogram and diagnostic system for the bit-sliced processor constructed by the array of four Am 2901 bit-slices are developed.

A Functional Approach to Testing Bit-Sliced Microprocessors

Bit-sliced microprocessors are representative of an important class of LSI components that can be interconnected in a regular way to construct many useful types of digital systems. This paper develops an analytic test generation methodology for bit-sliced systems. A formal model C for a 1-bit bit-sliced microprocessor is defined which has the main features of many commercially available microprocessors. Using a functional fault model instead of the usual stuck-line fault model, a technique is presented for deriving a complete and near-minimal sequence of tests for C. The basic cell C is extended to form two more general cells Ck and Ck. n. Ck is a k-bit version of C, while Ck, n is Ck with an n × k-bit scratchpad RAM. The internal structure of C4,16 closely resembles that of the AMD 2901 processor slice. Test sequences for these cells are derived in much the same way as for C. It is shown that the test sequence for a single cell (C, Ck, or Ck, n) can easily be extended to a test sequence for an array of N identical cells with no increase in the number of tests required. It is observed that for test generation purposes, bit-sliced microprocessors can be viewed as C-testable iterative logic arrays, which require a constant number of test patterns independent of array size. Some new results on test generation for C-testable systems are presented, as well as a method for modifying iterative logic arrays to make them C-testable.