Frequency Synthesizer For Applications Research Articles

Low-Power High-Frequency Phase Frequency Detector for Minimal Blind-Zone Phase-Locked Loops

This paper describes a symmetric phase frequency detector (PFD). The symmetric structure of PFD provides phase-locked loop (PLL) functions with a low jitter. The most important point in designing PFDs is attention to their dead zone, the extent of their linearity, and the frequency range of operation. As the dead zone of a phase detector circuit is smaller, this circuit is capable of detecting fewer phase differences in high frequencies. In this paper, considering the trade-off between the dead zone and the maximum operating frequency, the highest operating frequency is achieved with minimal dead zone design. Post-layout simulation for TSMC 0.13 μm technology is performed using the CMOS technology: The results so obtained are then compared with existing literature. These results indicate a power consumption of less than 90 μW and a frequency response of 4.1 GHz, as well as a dead zone of less than 25 ps in the worst case: This is a suitable condition as compared to previous, related works. The area of the proposed symmetric circuit is 250 μm2. Finally, the proposed PFD tested in PLL and the results indicate that the structure is useful for frequency synthesizer applications.

A size-miniaturized bandpass filter with selectivity-enhanced and high harmonic suppression performance

In this paper, a novel microstrip bandpass filter is proposed to enhance sideband selectivity, suppress harmonic frequency up to three-order as well as to keep a miniaturized size for frequency synthesizer application. The filter is constructed by four λ/4 folded stepped-impedance resonators (FSIRs) and two λ/2 stepped-impedance resonators at input/output ports to create three pairs of coupling paths and then to produce three cross-coupling transmission zeros (TZs) as well as to achieve a size miniaturization with 96% reduction compared with the conventional filter. By adding a common grounded metallized via hole among four λ/4 FSIRs of the filter, additional four mixed electric and magnetic coupling paths are set to generate extra four TZs. With these seven TZs, the proposed filter achieves a good sideband selectivity and harmonic suppression. Finally, the filter is designed, fabricated, and measured, its measured results are in well agreement with its simulated results.

Size‐miniaturized and selectivity‐enhanced bandpass filter using folded stepped‐impedance resonators

ABSTRACTIn this article, a 3.5 GHz size‐miniaturized microstrip bandpass filter based on folded stepped‐impedance resonators (FSIR) structure is presented for frequency synthesizer application to achieve a moderate wide stopband performance and an enhanced sideband selectivity performance by two transmission zeros (TZs). The filter is composed of four half‐mode FSIRs, where two FSIRs in the middle consist of a tri‐mode resonator which produces a TZ, and a pair of 180‐degree feed ports produce another TZ. After the filter is fabricated and measured, its measurement results are agreed with its simulated ones very well, and show its in‐band (1dB bandwidth from 3.3 GHz to 3.7 GHz) insertion loss is less than 1.6 dB, its sideband suppression is 45dB at 260MHz away from the upper sideband, as well as its stopband rejection is 26 dB far to the fourth harmonic of the center frequency. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:60–62, 2017

A 3.01–3.82 GHz CMOS LC voltage-controlled oscillator with 6.29% VCO-gain variation for WLAN applications

A wideband low-phase-noise LC voltage-controlled oscillator (VCO) with low VCO gain (KVCO) variation for WLAN fractional-N frequency synthesizer application is proposed and designed on a 0.13-μm CMOS process. In order to achieve a low KVCO variation, an extra switched varactor array was added to the LC tank with the conventional switched capacitor array. Based on the proposed switched varactor array compensation technique, the measured KVCO is 43 MHz/V with only 6.29% variation across the entire tuning range. The proposed VCO provides a tuning range of 23.7% from 3.01 to 3.82 GHz, while consuming 9 mA of quiescent current from a 2.3 V supply. The VCO shows a low phase noise of −121.94 dBc/Hz at 1 MHz offset, from the 3.6 GHz carrier.

A CMOS Transformer-Based Current Reused SSBM and QVCO for UWB Application

This paper presents the design of a low-voltage current-reused single-sideband mixer (SSBM) and quadrature voltage-controlled oscillator (QVCO) for Mode-1 multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer application. The proposed architecture is a low-voltage and low-power solution by stacking the SSBM on top of a pMOS parallel QVCO. For low-voltage operation, two symmetric transformers are used to perform quadrature oscillation and signal coupling. In addition, source degeneration capacitors are introduced to eliminate bimodal oscillation in QVCO and fix the phase sequence of the quadrature signal. For experimental demonstration, the proposed circuit was fabricated in a 0.18- $\mu{\hbox {m}}$ CMOS technology. The prototype occupies a core area of 0.8 $ {\hbox {mm}}^{2}$ and consumes about 11 mA from a 1.6-V power supply. Measurement results show that the image spurious rejection is over 43 dBc and the output phase noise of the SSBM is better than ${-}{\hbox{111.4 dBc/Hz}}$ at 1-MHz offset from carrier (3.432 GHz).

Electroplated nickel based micro-machined disk resonators for high frequency applications

Microelectromechanical system (MEMS) based resonators can be used for filtering and frequency synthesis applications in many subcomponents of radio frequency wireless integrated circuits due to their small size, high level of frequency selectivity, low cost batch fabrication, ease of integration with CMOS circuits. Electroplated nickel is an attractive low cost material for CMOS compatible MEMS due to their low deposition temperatures. Among the different modes of vibration, radial-contour mode resonators are preferred for high frequency applications because they offer higher effective stiffness. Two different types of electroplated nickel based radial-contour bulk-mode circular disk resonator geometries which depend on capacitive actuation and readout technique is presented in this work. Material, mechanical and electrical characterizations were performed on these structures to show their functionality.

A Long Sequence Length, Reduced Complexity MASH 1-1-1 DDSM for Fractional-N Frequency Synthesizer

In this paper, a long sequence length, reduced complexity MASH 1-1-1 digital delta-sigma modulator (DDSM) suitable for fractional-N frequency synthesizer applications is presented. Good shaping of quantization noise is achieved by using the state of art MASH structure for a digital third-order delta-sigma modulator, meanwhile, the hardware required for this modulator is considerably reduced by recoding all carry output signal from accumulators. The functional operation of the modulator is confirmed by simulation.

A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications

In this paper, a low-cost, power efficient and fast Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cell (named DCVSL-R) is proposed. We use the DCVSL-R cell to implement high frequency and power-critical delay cells and flip-flops of ring oscillators and frequency dividers. When compared to TSPC, DCVSL circuits offer small input and clock capacitance and a symmetric differential loading for previous RF stages. When compared to CML, they offer low transistor count, no headroom limitation, rail-to-rail swing and no static current consumption. However, DCVSL circuits suffer from a large low-to-high propagation delay, which limits their speed and results in asymmetrical output waveforms. The proposed DCVSL-R circuit embodies the benefits of DCVSL while reducing the total propagation delay, achieving faster operation. DCVSL-R also generates symmetrical output waveforms which are critical for differential circuits. Another contribution of this work is a closed-form delay model that predicts the speed of DCVSL circuits with 8% worst case accuracy. We implement two ring-oscillator-based VCOs in 0.13 μm technology with DCVSL and DCVSL-R delay cells. Measurements show that the proposed DCVSL-R based VCO consumes 30% less power than the DCVSL VCO for the same oscillation frequency (2.4 GHz) and same phase noise (-113 dBc/Hz at 10 MHz). DCVSL-R circuits are also used to implement the high frequency dual modulus prescaler (DMP) of a 2.4 GHz frequency synthesizer in 0.18 μm technology. The DMP consumes only 0.8 mW at 2.48 GHz, a 40% reduction in power when compared to other reported DMPs with similar division ratios and operating frequencies. The RF buffer that drives the DMP consumes only 0.27 mW, demonstrating the lowest combined DMP and buffer power consumption among similar synthesizers in literature.

Reduced Complexity MASH Delta–Sigma Modulator

A reduced complexity digital multi-stage noise shaping (MASH) delta-sigma modulator for fractional-N frequency synthesizer applications is proposed. A long word is used for the first modulator in a MASH structure; the sequence length is maximized by setting the least significant bit of the input to ldquo1;rdquo shorter words are used in subsequent stages. Experimental results confirm simulations.

Towards generic charge-pump phase-locked loop, jitter estimation techniques using indirect on chip methods

Due to desirable operational and implementation characteristics, charge-pump phase locked loop (CP-PLL) systems are the architecture of choice for a variety of embedded frequency synthesis applications. A key performance metric of these systems is the spectral purity of the output signal. Spectral purity is difficult to measure directly, especially within a production test environment. This situation is not likely to improve as on-chip system frequencies increase. This paper focuses on specific aspects of a new framework including techniques and methodologies that can detect significant block level errors that lead to spectral degradation. The final crux of the work is to focus towards measurement techniques that can be mapped directly to spectral degradation, and thus prove unambiguously that the CP-PLL system is ‘right by design’ and free from errors without resorting to difficult direct measurements. This paper provides an overview of typical non-idealities and the associated effects on spectral degradation and also provides explanations of suitable detection methods. It is expected that with ever increasing system frequencies, thorough analysis of the relationship between system non-idealities and jitter/phase noise may be the only option available for rapid production testing of fully embedded CP-PLLs.

Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications

A reduced complexity third-order digital delta-sigma modulator for fractional-N frequency synthesis is presented. The high-performance modulator, which consists of two sub-blocks, has a single-bit output making it best for this sort of application. A good shaping of quantisation noise is achieved using a new architecture for a digital third-order delta-sigma modulator. The hardware required for this modulator is considerably less than that in previously reported leading to lower power and area consumption and a higher operating frequency. The field programmable gate array (FPGA) implementation of the whole system shows an SNR of at least 94 dB and an operating input range of 0.7 of the full scale (0.7 FS) with an oversampling ratio of 167. The post-layout simulation of the digital circuit using 0.25 /spl mu/m CMOS technology predicts a maximum operating frequency of over 60 MHz at a supply voltage of 1.5 V.

Rigorous Analysis of Delta–Sigma Modulators for Fractional-<tex>$N$</tex>PLL Frequency Synthesis

In this paper, rigorous analyses are presented for higher order multistage noise shaping (MASH) Delta-Sigma (/spl Delta//spl Sigma/) modulators, which are built out of cascaded first-order stages, with rational DC inputs and nonzero initial conditions. Asymptotic statistics such as the mean, average power, and autocorrelation of the binary quantizer error are formulated using a nonlinear difference equation approach. An important topic of interest considered here is the fractional-N phase-locked-loop frequency synthesis applications, where the input to the modulator has to be a rational constant. It has been mathematically shown that, regardless of the initial conditions, first-order and second-order MASH /spl Delta//spl Sigma/ modulators with rational DC inputs cannot sufficiently randomize the quantization error samples, and, therefore, are not suitable for fractional-N synthesis applications. An irrational initial condition imposed on the first accumulator of a third or higher order MASH modulator, on the other hand, annihilates the tones throughout the whole output spectrum, and provides a very smooth noise shaping. Simulation results are provided to support the theoretically derived results. Implementation issues of the irrational initial condition in the digital domain are also discussed and investigated together with the effect of finite accumulator size on the noise-shaping quality factor.

A Survey of Heterojunction Bipolar Transistor (HBT) Device Reliability

Heterojunction bipolar transistor (HBT) technology has become a major player in wireless communication, power amplifier, mixer, and frequency synthesizer applications. HBTs extend the advantages of silicon bipolar transistors to significantly higher frequencies. Since the mid-1980s, HBT technology development has focussed on reducing cost and improving reliability which, in turn, led to numerous commercial products, such as prescalers, gate arrays, digital-to-analog converters, mux/demux chip sets, logarithmic amplifiers, RF chip sets for CDMA wireless communication systems, and power amplifiers for cellular communications. They have become a natural choice for very high frequency military applications requiring a high current drive, high transconductance, high voltage handling capability, low noise oscillator, and uniform threshold voltage. Emerging HBT technologies allow the integration of a large quantity of high performance RF circuits and high speed digital circuits on a single chip. This paper provides an overview of HBT device reliability issues.

Motivations towards BIST and DfT for embedded charge-pump phase-locked loop frequency synthesisers

Charge-pump phase-locked loops (CP-PLL) are the circuit architecture of choice for embedded frequency synthesis applications. In all situations a frequency synthesis system will generate timing or reference signals for other important system functions. Therefore, it is a key element for satisfactory system level operation and must be verified correctly. The key performance metric for CP-PLLs is often stated in terms of spectral purity or jitter of the generated output signal. However, in a production test environment it can be difficult to assess system performance directly in these terms. For a correctly designed system, output signal degradation can often be related back to deviations or errors introduced during the manufacturing process. In many instances the CP-PLL may be the only analogue block present on a digital SoC (system on chip), and in consequence production test is often focused towards sufficient verification using methods applicable for digital only testers. Direct access DfT (design for test) techniques are often employed to address test requirements for analogue portions of the CP-PLL; however, problems can occur in terms of noise injection and general test access. The paper presents an introductory overview and tutorial providing information relating to key CP-PLL deviations, common direct access DfT extraction methods and the associated problems. In addition, a review of recent significant BIST (built-in-self-test)/DfT test approaches is provided. The focus is on methods that can indirectly validate CP-PLL closed loop performance and be useful in highlighting key jitter or phase noise contributors.

Investigations for minimum invasion digital only built-in "ramp" based test techniques for charge pump PLL's

Due to a number of desirable operational and design characteristics, CP-PLL's (Charge Pump Phase Locked Loops) have, in recent years become a pervasive PLL architecture. CP-PLL architectures are exploited for a variety of applications such as on chip clock generation, CRC (clock recovery circuits) and radio frequency synthesis applications. This paper describes a simple, digital only, minimally invasive and fully automated test approach for high performance CP-PLL's that can be used to provide more information about the CP-PLL function beyond that obtained through the commonly used FLT (Frequency Lock Test). The test strategy described here allows the estimation of forward path gain and relative leakage in the forward path loop components. Applications of the test are focussed towards digital only testing of fully embedded CP-PLL's, however further test modifications could yield marked test time improvements for embedded and board level CP-PLL's incorporating multiple CP currents and or multiple loop filter configurations.

A pipelined noise shaping coder for fractional-N frequency synthesis

In this paper, we present the design considerations and implementation aspects of a pipelined all-digital fourth-order multi-stage-noise-shaping (MASH) delta-sigma (/spl utri//spl Sigma/) modulator suitable for fractional-N (F-N) phase-locked loop (PLL) frequency synthesis applications. In an effort to reduce the hardware complexity and power consumption, the alignment registers, which are normally required in pipelined adders, are eliminated by taking advantage of static modulator input. The MASH modulator has successfully been targeted to an Altera/sup TM/ field-programmable-gate-array (FPGA) device. The functional operation of the modulator has been verified through structural bit-level simulations as well as experimental results on the actual FPGA implementation.

An ultralow power CMOS/SIMOX programmable counter LSI

We designed and fabricated an extremely low-power CMOS/SIMOX programmable counter large scale integrated circuits (LSI) for high-speed phase-locked loop (PLL) frequency synthesizer applications. This was to verify the potential usefulness of ultrathin-film 0.24-/spl mu/m-gate CMOS/SIMOX process technology for creating an extremely low-power LSI containing high-speed circuits operating at frequencies of at least 1 GHz and at low supply voltages. While operating at up to 2.2 GHz and consuming only 4.5 mW at 1.5 V, it is capable of 4-GHz performance with power consumption of 19 mW at 2.5 V. Even at a low supply voltage of 1.5 V, high input-sensitivity was also achieved in the 1- to 2-GHz frequency range. These low-power and high input-sensitivity characteristics outperform those of state-of-the-art BiCMOS PLL LSIs.

Residual phase noise measurements of VHF, UHF, and microwave components

The results of residual phase noise measurements on a number of VHF, UHF, and microwave amplifiers, both silicon (Si) bipolar junction transistor (BJT) and gallium arsenide (GaAs) field effect transistor (FET) based, electronic phase shifters, frequency dividers and multipliers, etc., which are commonly used in a wide variety of frequency source and synthesizer applications are presented. The measurement technique has also been used to evaluate feedback oscillator components, such as the loop and buffer amplifiers, which can play important roles in determining an oscillator's output phase noise spectrum (often in very subtle ways). While some information has previously been published related to component residual phase noise properties, it generally focused on the flicker noise levels of the devices under test, for carrier offset frequencies less than 10 kHz. The work reported herein makes use of an extremely low noise, 500 MHz surface acoustic wave resonator oscillator (SAWRO) test source for residual phase noise measurements, both close-to-and far-from-the-carrier. Using this SAWRO-based test source at 500 MHz, we have been able to achieve a measurement system phase noise floor of -184 dBc/Hz, or better, for carrier offset frequencies greater than 10 kHz, and a system flicker phase noise floor of -150 dBc/Hz, or better, at 1 Hz carrier offset. The paper discusses the results of detailed residual phase noise measurements performed on a number of components using this overall system configuration. Several interesting observations related to the residual phase noise properties of moderate to high power RF amplifiers, i.e., amplifiers with 1 dB gain compression points in the range of +20 to +33 dBm, are highlighted.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A high-speed multimodulus HBT prescaler for frequency synthesizer applications

A high-speed variable modulus prescaler that divides the input clock frequency by 128 up to 255 with unit step increment has been implemented with heterojunction bipolar transistor (HBT) technology. A maximum operating frequency of 9.72 GHz with power consumption of 650 mW has been measured. The high-speed performance is attributed to the circuit design, which minimizes the critical path delay, and the intrinsic high-speed characteristics of HBT technology. The phase noise of the prescaler is important for frequency synthesizer applications. With 6.24-GHz input frequency, the phase noise was -110 dBc/Hz at 100-Hz offset frequency and -120 dBc at 1-kHz offset frequency. The noise floor decreases as the input frequency decreases. Phase noises of -125 dBc/Hz at 100-Hz offset and -135 dBc/Hz at 1-kHz offset were obtained for a 1.2-GHz input frequency. >

GaAs prescalers and counters for fast-settling frequency synthesizers

A number of low-power GaAs direct-coupled FET logic (DCFL) components developed for use in compact, fast-settling phase-locked-loop-type frequency synthesizer applications are discussed. These components include a divide-by-two circuit (2.7 GHz, 1.3 mW), a dual-modulus (/10/11) prescaler (2.4 GHz, 15 mW), a 4-b ripple counter (2.4 GHz, 4.6 mW), a 4-b programmable prescaler (1.7 GHz, 36 mW), a 3-b programmable counter (1.9 GHz, 57 mW), a 4-b programmable counter (1.8 GHz, 70 mW), and a 6-b programmable counter (1.4 GHz, 90 mW). The circuits are fabricated with a high-yield refractory self-aligned gate process and operate over a wide variation in power supply voltage and temperature. When operated over a -55 to 125 degrees C temperature range, the circuits show less than 20% degradation in their maximum clock frequency. The results demonstrate state-of-the-art high-frequency performance at extremely low power dissipation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>