fractional-N Frequency Synthesizer Research Articles

A Noise Filtering Technique for Fractional-$N$ Frequency Synthesizers

A noise filtering technique for fractional-N frequency synthesizers (FNFSs) is presented. The noise filter is based on an integer-N (N = 1) phase-locked loop that is placed in a feedback path of an FNFS. By adopting the noise filter, out-of-band quantization noise of a high-order delta-sigma modulator is suppressed. In addition, folded noise due to nonlinearity of a phase/frequency detector (PFD) and a charge pump is improved by reducing phase errors at PFDs. An FNFS using the noise filter is fabricated in 90-nm complementary metal-oxide-semiconductor technology. Its die area is 950 by 950 μm, and its power consumption is 30 mW for a supply voltage of 1 V. The frequency resolution of this FNFS is less than 1 Hz.

Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL

Digital delta-sigma modulators (DDSMs) applied in fractional-N frequency synthesizers suffer from spurious tones which undermine the synthesizer's spectral purity. We propose a solution featuring no hardware overhead while achieving equivalent spur elimination effect as using LFSR-dithering. This method can be implemented on MASH and single-loop DDSMs of 3rd- and 2nd-order.

A fractional spur suppression technique in the fractional-N frequency synthesizer

A fractional spur suppression technique is presented based on the principle of spur generation, which makes the phase between the divider output and the reference be permanently coherent like integer-N frequency synthesizer, so a real lock is achieved. The spurious tones are strongly reduced without sacrificing the PLL bandwidth. The detailed scheme and corresponding key building blocks are deeply discussed. A 1.9 GHz frequency synthesizer with a 100 kHz bandwidth is implemented with the proposed way. SpectreVerilog simulation results show that the technique can reduce over 10 dBc/Hz spurious tones. So it is suitable for high spectral purity frequency synthesizer.

A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller

A 0.3–1.4 GHz all-digital phase locked loop (ADPLL) with an adaptive loop gain controller (ALGC), a 1/8-resolution fractional divider and a frequency search block is presented. The ALGC reduces the nonlinearity of the bang-bang phase-frequency detector (BBPFD), reducing output jitter. The fractional divider partially compensates for the large input phase error caused by fractional-N frequency synthesis. A fast frequency search unit using the false position method achieves frequency lock in 6 iterations that correspond to 192 reference clock cycles. A prototype ADPLL using a BBPFD with a dead-zone-free retimer, an ALGC, a fractional divider, and a digital logic implementation of a frequency search algorithm was fabricated in a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox {m}}$</tex></formula> CMOS logic process. The core occupies 0.2 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\hbox {mm}}^{2}$</tex> </formula> and consumes 16.5 mW with a 1.2-V supply at 1.35-GHz. Measured RMS and peak-to-peak jitter with activating the ALGC are 3.7 ps and 32 ps respectively.

A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer

This paper presents a technique to reduce the quantization error in fractional division for a wideband fractional-N frequency synthesizer. By using a direct digital synthesis phase accumulator as the fractional divider and a DAC as the phase-to-pulse converter, the quantization error can be much smaller than the one by conventional sigma-delta modulated multi-modulus divider. With small quantization error, a dedicated compensation mechanism is no longer necessary for wide loop bandwidth applications. To demonstrate this concept, a prototype chip was implemented with 0.18-μm CMOS. The synthesizer consumes 19 mA from a 1.8 V supply. With 1 MHz closed-loop bandwidth, the in-band noise is -98 dBc/Hz and the 3 MHz offset noise is -122 dBc/Hz for a 1.8 GHz output. The output exhibited 27 dB phase noise reduction compared to the generic sigma-delta structure. The settling time is 2 μs under a 35 MHz frequency step.

A Single-VCO Fractional-$N$ Frequency Synthesizer for Digital TV Tuners

A single-voltage-controlled-oscillator (VCO) fractional-N frequency synthesizer is designed for Advanced Television Systems Committee, Digital Video Broadcasting-Terrestrial, and Integrated Services Digital Broadcasting-Terrestrial digital television tuners. This frequency synthesizer can cover all the frequency bands for all three standards with only one VCO, and thus, the chip area as well as the power consumption can be greatly reduced. Different channel spacing requirements can be fulfilled by fractional synthesis. A dynamic frequency calibration loop is also used to automatically choose the coarse setting of the VCO. The synthesizer was fabricated in a standard 0.13-μm complementary metal-oxide-semiconductor process and draws 14 mA from a 1.2-V supply. The measured phase noise is lower than -80 dBc/Hz from 1 to 100 kHz offset and -100 dBc/Hz at 1 MHz offset. The active area of the frequency synthesizer is smaller than 0.54 mm2.

A Δ-Σ fractional-N frequency synthesiser with quantisation noise folding suppression

A wideband Δ-Σ fractional-N frequency synthesiser with novel Δ-Σ quantisation noise folding suppression technique is presented in this article. A novel linearisation technique is proposed to suppress Δ-Σ quantisation noise folding due to nonlinearity of the phase frequency detector/charge pump (PFD/CP). In order to cover a wide frequency band and process, voltage and temperature (PVT) variation, a switched capacitors LC tank voltage-controlled oscillator and closed-loop automatic frequency band selection method are adopted. The chip is fabricated in a HeJian 0.18 radio frequency (RF) CMOS process. The measured output frequency is from 1.75 to 2.25 GHz with tuning range as wide as 500 MHz. The measured phase noise performance is −81.97 dBc/Hz and −112 dBc/Hz at 10-KHz and 1-MHz offset frequency, respectively. The measured reference spur is −44.05 dBc/Hz at 10-MHz offset frequency. The frequency synthesiser consumes 27.8 mW from a 1.8 V power supply.

A 2-to-2.4-GHz differentially-tuned fractional-N frequency synthesizer for DVB tuner applications

This paper describes the design of a fractional-N frequency synthesizer for digital video broadcasting-terrestrial (DVB-T) receivers. Transfer functions in differentially-tuned PLL are derived and loop parameters are designed. In addition, a fully-differential charge pump is presented. An 8/9 high speed prescaler is analyzed and the design considerations for the CML logic are also presented. Test results show that the RMS phase error is less than 0.7° in integer-N mode and less than 1° in fractional-N mode. The implemented frequency synthesizer draws 10 mA from a 1.8-V supply while occupying a die area of about 1-mm2 in a 0.18-μm CMOS process.

Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔfractional-N synthesizer

A 19 mW highly integrated GPS receiver with a ΣΔfractional-N synthesizer is presented in this paper. Fractional-N frequency synthesizer architecture was adopted in this work, to provide more degrees of freedom in the synthesizer design. A high linearity low noise amplifier (LNA) is integrated into the chip. The radio receiver chip was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process and packaged in a 48-pin 2 mm×2 mm land grid array chip scale package. The chip consumes 19 mW (LNA1 excluded) and the LNA1 6.3 mW. Measured performances are: noise figure<2 dB, channel gain=108 dB (LNA1 included), image rejection>36 dB, and −108 dBc/Hz @ 1 MHz phase noise offset from the carrier. The carrier noise ratio (C/N) can reach 41 dB at an input power of −130 dBm. The chip operates over a temperature range of [−40, 120] °C and ±5% tolerance over the CMOS technology process.

A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver

This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18 μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order Σ–Δ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8o respectively. The measured phase noise is −116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than −60 dBc. The settling time is within 80 μs. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.

Digital High Order Multiplier-free Delta Sigma Modulator for Multistandard Fractional-N Frequency Synthesizer

This paper proposes a new stable design strategy for 1-bit high order digital DS modulator for multistandard fractional-N frequency synthesizer. The proposed digital DS modulator presents simplicity, low power consumption and controls a dual-modulus divider instead of multi-modulus one as in existing DS fractional-N frequency synthesizer. Simulation results illustrate the DS modulator good performances in terms of spectrum purity and accuracy. Using this stable 1-bit digital DS modulator output to a fractional-N frequency synthesizer Simulink model verifies the multistandard frequency synthesizer specifications.

Subtraction Inversion for Delta Path's Hardware Simplification in MASH Delta-Sigma Modulator

The multistage noise-shaping (MASH) delta-sigma modulator (DSM) is the key element in a fractional-N frequency synthesizer. A hardware simplification method with subtraction inversion is proposed for delta-path's design in a MASH delta-sigma modulator. The subtraction inversion method focuses on simplification of adder-subtractor unit in the delta path with inversion of subtraction signal. It achieves with less hardware cost as compared with the conventional approaches. As a result, the hardware organization is regular and easy for expanding into higher order MASH DSM design. Analytical details of the implementation way and hardware cost function with N-th order configuration are presented. Finally, simulations with hardware description language as well as synthesis data verified the proposed design method.

A Low-Noise and Low-Power Frequency Synthesizer Using Offset Phase-Locked Loop in 0.13-$\mu{\rm m}$ CMOS

In this letter, a fractional-N frequency synthesizer based on an offset phase-locked loop (OPLL) architecture is presented. The proposed synthesizer achieves low-noise as the two low-pass filters that are inherent in the OPLL highly suppresses the quantization noise from the delta-sigma modulator. In addition, it consumes low power by employing charge-recycling technique in the sub-PLL. A prototype synthesizer implemented in 0.13 μm CMOS process achieves 9 dB of noise reduction compared to a conventional PLL while consuming 3.2 mW of power.

A CMOS high-speed pulse swallow frequency divider for .DELTA..SIGMA. fractional-N PLL's

A high-speed pulse-swallow frequency divider suitable for ΔΣ fractional-N synthesizers is proposed. The proposed structure employs the retiming scheme for the modulus control signal to extend the timing margin, thus remarkably increasing the maximum operating speed. Moreover, unlike the conventional structure, the modulus control signal is set and reset by a single triggering signal to eliminate the unwanted offset at the total division ratio. It simplifies the interface logic between the divider and the ΔΣ modulator in ΔΣ fractional-N PLL's. Simulation results show that the proposed divider provides over three times faster operating speed than the conventional one. The proposed divider has been successfully verified in CMOS RF ΔΣ fractional-N frequency synthesizers.

A voltage-controlled oscillator with an ultra-low supply voltage and its application to a fractional-N phase-locked loop

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma–delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is −116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma–delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43–1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is −110 dBc/Hz@1.0 MHz.

A fractional-N frequency synthesizer for WCDMA/Bluetooth/ZigBee applications

A triple-mode fractional-N frequency synthesizer with a noise-filter voltage controlled oscillator (VCO) for WCDMA/Bluetooth/ZigBee applications has been implemented in 0.18-μm RF-CMOS technology. The proposed synthesizer achieves a good phase noise lower than −80 dBc/Hz in band and −115 dBc/Hz@1 MHz for the three modes, and only draws 21 mA from a 1.8 V supply. It has a high hardware sharing and a small size, only 1.5 × 1.4 mm2. The system architecture, circuit design, and measured results are also presented.

DWA TECHNIQUE TO IMPROVE DAC OF SIGMA-DELTA FRACTIONAL-N FREQUENCY SYNTHESIZER FOR WIMAX

A first order of DWA (Data Weighted Averaging) algorithm with third order sigma-delta modulator is proposed for application in sigma-delta fractional-N frequency synthesizer for WiMAX. In addition, this paper discusses the impact of mismatch between Digital-to-Analog convertor (DAC) unit elements. The simulation results show the effectiveness of the DWA technique in reduction of spurs, also DWA technique proves its ability to solve DAC unit elements mismatch. The fractional spur noise is converted into a broadband. Quantization noise with DWA is improved by – 10 dB if the element mismatch 0.01 and – 5 dB if the element mismatch 0.08 with 8 bit PFD/DAC. Matlab (V.7) program is used for simulation.

A 0.13 &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\mu$&lt;/tex&gt; &lt;/formula&gt;&lt;emphasis emphasistype="roman"&gt;m&lt;/emphasis&gt; CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1deg RMS phase error and the measured phase noise is -164.5 dBc/Hz at 20 MHz offset from a 914.8 MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/-12 dBm for the low bands (850/900 MHz) and 3 dB/-11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 mum CMOS technology and occupies 10.5 mm2. The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5 times 5 mm2 40-pin QFN package.

Hardware Simplification to the Delta Path in a MASH 111 Delta–Sigma Modulator

A MASH 111 delta-sigma modulator (DSM) is widely used in a fractional-N frequency synthesizer. This brief presents a low-complexity delta-path design in a MASH 111 modulator by simply recoding all carry output signals from accumulators. Compared with the prior approach, the hardware complexity of the proposed delta path is reduced to 53.4% of the prior approach. For frequency synthesizers with limited channels or for the pipelined DSM with accumulators possessing long word lengths, this saving is significant.

A 5-GHz-Band CMOS Receiver With Low LO Self-Mixing Front End

A 5.0-GHz-band monolithic direct-conversion receiver front end employing subharmonic mixers (SHMs) is demonstrated in 0.18-mum CMOS technology. Instead of using transistors as transconductors, the SHMs adopt on-chip 1:4 transformers to achieve voltage gain, and hence, excellent local-oscillator self-mixing suppression and good linearity can be obtained. Additionally, a CMOS-compatible postprocess is used to selectively remove the silicon substrate underneath the inductors and transformers of the receiver front end. While dissipating 43.9 mW from a 1.8-V supply, the micromachined receiver front end exhibits a voltage gain of 28.0 dB, a noise figure of 9.7 dB, a third-order input intercept point of -7.8 dBm at 5.0 GHz, and an input-referred dc offset of -118.0 dBm. The proposed receiver front end is further integrated with analog baseband circuits, a fractional-N frequency synthesizer, and a serial-to-parallel data converter to accomplish a multioperation-mode receiver.