FPGA-based Reconfigurable Systems Research Articles

FPGA-BASED DATA COMMUNICATION SYSTEM IN DIGITAL SIGNAL PROCESSING DEVICES WITH PHASED ANTENNA ARRAYS

The paper represents some engineering solutions which provide coherence and coherent data transmission in radar and communication systems with phased array with computing components designed on the principles of FPGA-based reconfigurable computer systems. We developed the coherent gathering methods of digitized data from the phased array antenna elements, and data transmission among the distributed components that perform coherent digital signal processing. To provide coherent data processing and transmission, we use the signal of clock reference signal and the CPU-time, centrally generated and transmitted into all nodes with the same delay. Generation of all control signals in the processing nodes are based on these two signals. For data transmission, we suggest to use high-speed optical links, which are the most reliable in environmental conditions. To transmit the digitized data from phased array antenna elements, we suggested using packet data transmission with data integrity control and time-linked digitized data. Also, we applied a mechanism to monitor the delay mismatch of packets transmitted via different links and to synchronize them in data receivers. The most probable emergency situations for the data transmission system are considered and methods of parrying and minimizing the impact of transmission errors on the formation of the result are proposed. The developed engineering solutions were tested on a real FPGA-based beam-forming device with simulation of emergency situations. Many hours of tests and runs showed that all emergency situations were successfully solved by the data communication system.

The approach to design of dynamically reconfigurable arbitration units in embedded systems

Today we are seeing an intensive development of dynamically reconfigurable components in the FPGA-based embedded systems. Nevertheless, by their parameters, FPGA-based projects are essentially inferior to those that are on ASIC and the same design rules. This significantly limits applications of the FPGA-based reconfigurable systems. The paper presents relevance of dynamic reconfiguration for arbitration units in embedded systems. There is a review of existing design techniques for ASIC-based dynamically reconfigurable components. They have been also evaluated by applicability for the arbitration unit development (complex function modules for systems-on-chip and networks-on-chip). The authors have proposed the approach to the development of dynamically reconfigurable arbitration units in embedded systems. The approach makes it possible to consider specific requirements to these units.

Online placement and scheduling algorithm for reconfigurable cells in self-repairable field-programmable gate array systems

Most of the high-end very-large-scale integration- (VLSI-) based systems use a field-programmable gate array (FPGA) as their core component. As the complexity of systems increases, the chances of fault occurrence also increase. For systems that are part of safety-critical and mission-critical applications, even a single fault can result in entire mission failure. Fault tolerance techniques need to be installed in such systems to ensure reliable, prolonged operation in spite of fault occurrence. The level of fault tolerance exhibited in nature is very remarkable. Scientists are trying to reach that level of fault tolerance in the electronics world as well, which is not always completely acquirable. Basically, fault tolerance in an FPGA is achieved by the use of spare modules, which leads to high area overheads and routing complexity. The higher the number of faults to be handled, the greater the number of spares that will be required. Partial reconfiguration has always been a proven technique to improve the efficiency and flexibility of FPGAs. This paper discusses a multiple-fault repair algorithm for FPGA-based reconfigurable systems, using dynamic runtime partial reconfiguration, in order to relocate faulty modules. Three variants or cases of repair using the algorithm are discussed and demonstrated, namely, placement with the best resource utilization, placement with the least routing overhead, and a case to generate continuous free space for the relocation of a faulty module. The main advantage of the algorithm is its flexibility, which means that it can be used according to user demands and system lifetime requirements. Maximum care is taken to eliminate chances of an unrepaired fault or a repair that degrades the performance of the system. The algorithm can handle multiple permanent faults with the best resource utilization and the least overheads. The performance of the algorithm is analyzed quantitatively, while a comparison is made with some previous studies in the literature to justify the algorithm efficiency.

Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

With the advancement of mobile and embedded devices, many applications such as data mining have found their way into these devices. These devices consist of various design constraints including stringent area and power limitations, high speed-performance, reduced cost, and time-to-market requirements. Also, applications running on mobile devices are becoming more complex requiring significant processing power. Our previous analysis illustrated that FPGA-based dynamic reconfigurable systems are currently the best avenue to overcome these challenges. In this research work, we introduce efficient reconfigurable hardware architecture for principal component analysis (PCA), a widely used dimensionality reduction technique in data mining. For mobile applications such as signature verification and handwritten analysis, PCA is applied initially to reduce the dimensionality of the data, followed by similarity measure. Experiments are performed, using a handwritten analysis application together with a benchmark dataset, to evaluate and illustrate the feasibility, efficiency, and flexibility of reconfigurable hardware for data mining applications. Our hardware designs are generic, parameterized, and scalable. Furthermore, our partial and dynamic reconfigurable hardware design achieved 79 times speedup compared to its software counterpart, and 71% space saving compared to its static reconfigurable hardware design.

Погружная система охлаждения реконфигурируемых вычислительных систем на основе ПЛИС

Погружная система охлаждения реконфигурируемых вычислительных систем на основе ПЛИС

A Communication-aware Scheduling Algorithm for Hardware Task Scheduling Model on FPGA-based Reconfigurable Systems

Task Scheduling is an important aspect of high performance reconfigurable computing. Most of the heuristics of this NP-hard problem are based on a simple abstract model of FPGA and have little investigation into optimizing data communication which influences the system performance importantly. To solve this problem, a Communication-aware Maximum Adjacent Edges (CA-MAE) algorithm based on 2D reconfigurable model is proposed, which could reduce communication distance during scheduling and enhance the system performance. The experimental results show that CA-MAE reduces communication cost by 17%.

Decentralized control for dynamically reconfigurable FPGA systems

The progress in FPGA technology has enabled FPGA-based reconfigurable systems to target increasingly sophisticated applications, which has led to a high control design complexity, resulting in longer design cycles. In this paper, we propose a control design approach for FPGA-based reconfigurable systems aiming at increasing design productivity. This approach is based on a semi-distributed control model that splits different control concerns (monitoring, decision-making and reconfiguration) between autonomous modular controllers and makes use of formalism-oriented design, to decrease the control design complexity and facilitate design verification, reuse and scalability. This model is composed of distributed controllers handling the self-adaptivity of the system reconfigurable regions and a coordinator to respect the system global constraints. To enhance design productivity, the proposed control model is generated automatically using a high-level modeling approach. This approach is based on MDE (Model-Driven Engineering) and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard, allowing to make low-level technical details transparent to designers and to automate code generation from high-level models. Experiments on the generated control systems showed that the proposed semi-distributed control model is more flexible, reusable and scalable than the centralized one, at the cost of a slight increase in required hardware resources.

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

The dynamically reconfigurable Field Programmable Gate Arrays (FPGAs) are most frequently employed for developing adaptive embedded systems. They are also being increasingly used as co-processors in high performance computing applications. For these systems to be fielded in harsh environments such as those encountered in space, extra- terrestrial locations and regions of extreme conditions on the earth, one must adopt fault tolerant design techniques to ensure uninterrupted and reliable operation despite the occurrence of faults. Commercial Off-the-Shelf (COTS) FPGA components offer a cost effective design trajectory where the designer can choose among a rich variety of FT approaches and techniques. This paper compares the various FT techniques and proposes a novel method in which these techniques can work together to provide a synergetic approach for fault tolerant FPGA design.

A Domain Partition Model Approach to the Online Fault Recovery of FPGA-Based Reconfigurable Systems

Field programmable gate arrays (FPGAs) are widely used in reliability-critical systems due to their reconfiguration ability. However, with the shrinking device feature size and increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation. To improve the reliability of FPGA-based reconfigurable systems, a permanent fault recovery approach using a domain partition model is proposed in this paper. In the proposed approach, the fault-tolerant FPGA recovery from faults is realized by reloading a proper configuration from a pool of multiple alternative configurations with overlaps. The overlaps are presented as a set of vectors in the domain partition model. To enhance the reliability, a technical procedure is also presented in which the set of vectors are heuristically filtered so that the corresponding small overlaps can be merged into big ones. Experimental results are provided to demonstrate the effectiveness of the proposed approach through applying it to several benchmark circuits. Compared with previous approaches, the proposed approach increased MTTF by up to 18.87%.

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

Contemporary FPGA-based reconfigurable systems have been widely used to implement data-dominated applications. In these applications, data transfer and storage consume a large proportion of the system energy. Exploiting data-reuse can introduce significant power savings, but also introduces the extra requirement for on-chip memory. To aid data-reuse design exploration early during the design cycle, the authors present an optimisation approach to achieve a power-optimal design satisfying an on-chip memory constraint in a targeted FPGA-based platform. The data-reuse exploration problem is mathematically formulated and shown to be equivalent to the multiple-choice knapsack problem. The solution to this problem for an application code corresponds to the decision of which array references are to be buffered on-chip and where loading reused data of the array references into on-chip memory happen in the code, in order to minimise power consumption for a fixed on-chip memory size. The authors also present an experimentally verified power model, capable of providing the relative power information between different data-reuse design options of an application, resulting in a fast and efficient design-space exploration. The experimental results demonstrate that the approach enables us to find the most power-efficient design for all the benchmark circuits tested.

Fast and compact sequential circuits for the FPGA-based reconfigurable systems

Reconfigurable systems fill the flexibility, performance, power dissipation, and development and fabrication cost gap between the application specific systems implemented with hard-wired application specific integrated circuits and systems based on the standard (general purpose) programmable microprocessors. During the last decade they became the mainstream implementation technology for custom computation and embedded system products in such fields as telecommunication, image processing, video processing, multimedia, DSP, cryptography, embedded control, etc. To efficiently develop, implement and use the reconfigurable systems, adequate computer-aided support tools are necessary. Since most reconfigurable systems are implemented using the look-up table (LUT) field programmable gate arrays (FPGA) technology, the circuit synthesis tools targeting this technology are of primary importance for their effective and efficient implementation. In this paper, a new sequential circuit synthesis methodology is discussed that targets LUT FPGAs and FPGA-based reconfigurable system-on-a-chip platforms. The methodology is based on the information-driven approach to circuit synthesis, general decomposition and theory of information relationship measures that we previously developed. Our synthesis methods considerably differ from all other known methods. The experimental results from the automatic circuit synthesis tools that implement our methods demonstrate that the information-driven approach consistently applied in the whole sequential circuit synthesis chain efficiently produces very fast and compact sequential circuits.

Memory access optimisation for reconfigurable systems

Memory access optimisation for FPGA-based reconfigurable systems with a hierarchy of on-chip and off-chip (external) memory to speed up applications limited by memory access speed are discussed. Most of the techniques are also valid for dedicated embedded systems and system-on-a-chip (SoC) designs. The approach involves two kinds of optimisation: first, methods to reduce the number of accesses by caching repeatedly used values are considered. The notion of vector access equivalence is introduced to form the basis of techniques employing FPGA storage as shift registers for caching. Larger data sets can be stored, if possible, in FPGA on-chip RAMs; RAM inference, a technique to automatically extract small on-chip RAMs to reduce external memory accesses is presented. Secondly, the authors aim to minimise the time spent on accesses to bandwidth-limited external memory, by scheduling as many accesses in parallel as possible. They present a technique which optimally allocates program arrays to memory banks, thereby minimising the overall access time. It also determines the most effective addressing mode for memory which can be accessed using different bitwidths.