Four-quadrant Multiplier Research Articles

Integrated Circuit Design of Fractional-Order Chaotic Systems Optimized by Metaheuristics

Nowadays, a huge amount of research is done on introducing and implementing new fractional-order chaotic systems. In the majority of cases, the implementation is done using embedded hardware, and very seldom does it use integrated circuit (IC) technology. This is due to the lack of design automation tools ranging from the system level down to layout design. At the system level, the challenge is guaranteeing chaotic behavior by varying all parameters while optimizing dynamical characteristics, such as the Lyapunov spectrum and the Kaplan–Yorke dimension. Using embedded hardware, the implementation is straightforward, but one must perform a scaling process for IC design, in which the biases may be lower than 1 volt but the amplitudes of the state variables of the chaotic systems can have values higher than one. In this manner, this paper describes three levels of abstraction to design fractional-order chaotic systems: The first one shows the optimization of a case study, the mathematical model of the fractional-order Lorenz system to find the fractional-orders of the derivatives, and the coefficients that generate better chaotic behavior. The second level is the block description of a solution of the mathematical model, in which the fractional-order derivatives are approximated in the Laplace domain by several approximation methods. The third level shows the IC design using complementary metal–oxide–semiconductor (CMOS) technology. The transfer functions approximating the fractional-order derivatives are synthesized by active filters that are designed using operational transconductance amplifiers (OTAs). The OTAs are also used to design adders and subtractors, and the multiplication of variables is done by designing a CMOS four-quadrant multiplier. The paper shows that the simulation results scaling the mathematical model to have amplitudes lower than ±1 are in good agreement with the results using CMOS IC technology of 180 nm.

Analog Neural Network Model based on Logarithmic Four-Quadrant Multipliers

Analog Neural Network Model based on Logarithmic Four-Quadrant Multipliers

Four-quadrant multiplier using the floating-bulk technique for rail-to-rail input range and insensitivity to different input dc levels

Four-quadrant multiplier using the floating-bulk technique for rail-to-rail input range and insensitivity to different input dc levels

Computational properties of multi-compartment LIF neurons with passive dendrites

Mixed-signal neuromorphic computers often emulate some variant of the LIF neuron model. While, in theory, two-layer networks of these neurons are universal function approximators, single-layer networks consisting of slightly more complex neurons can, at the cost of universality, be more efficient. In this paper, we discuss a family of LIF neurons with passive dendrites. We provide rules that describe how input channels targeting different dendritic compartments interact, and test in how far these interactions can be harnessed in a spiking neural network context. We find that a single layer of two-compartment neurons approximates some functions at smaller errors than similarly sized hidden-layer networks. Single-layer networks with with three compartment neurons can approximate functions such as XOR and four-quadrant multiplication well; adding more compartments only offers small improvements in accuracy. From the perspective of mixed-signal neuromorphic systems, our results suggest that only small modifications to the neuron circuit are necessary to construct more computationally powerful and energy efficient systems that move more computation into the dendritic, analogue domain.

A New Design for Compact Floating-Gate Transistor Based Low-Voltage Four-Quadrant Analog Current Multiplier

A New Design for Compact Floating-Gate Transistor Based Low-Voltage Four-Quadrant Analog Current Multiplier

Four-Quadrant CMOS Analog Current Multiplier Using Frequency Compensation and 1.5 V Supply

This work presents two new CMOS designs of current mode squarer circuits using a 1.5 V supply. The four-quadrant multiplier has also been designed using proposed squarer circuits. To improve bandwidth, the resistive compensation scheme has been exploited. The input and output signals of proposed circuits are of current type and hence exhibit larger dynamic range contrary to voltage mode circuits. Various simulations have been carried out to check performance and validate theoretical analysis. It is observed that range of − 3 dB bandwidth, power consumption and linearity error of the proposed circuits I and II are 542.53 MHz and 1.13 GHz, 0.56 and 0.47 mW and 1.8 and 2%, respectively. In the state of the art, it is noticed that around 10–90% bandwidth is increased while using proposed circuits over most of the conventional circuits. All results are verified using spice tools and 0.18 µm CMOS technology parameters.

A four quadrant high-speed CMOS analog multiplier based on the flipped voltage follower cell

In this work the design and implementation of a High-Speed Four-Quadrant CMOS Analog multiplier is presented. The proposed multiplier uses the Gilbert cell as the main core. However, instead of processing both input and output signals in voltage or current mode, the “x” input signal is applied in voltage mode while the “y” input signal and “o” output signal are processed in current-mode. This approach is achieved by means of using very-low-impedance nodes at the “y” and “o” ports which also helps to enhance the overall bandwidth of the proposed multiplier. Both very-low-impedance nodes are implemented using the Flipped Voltage Follower (FVF) as high-speed high-performance low-voltage current mirror. The implemented circuit shows a bandwidth of 260 MHz for a 50Ω‖30pF load, presents a 1.5% THD at 100 MHz, and consumes 7.5 mV using a ±1 V symmetric power supply. In order to validate theory and simulations, a prototype of the multiplier was fabricated and tested using a 0.5 μm CMOS standard fabrication process; a silicon area consumption of 520 μm × 70 μm was observed. Measurements shows that the proposed multiplier is suitable for its implementation in the low corner of the Very High Frequency (VHF) band.

An Efficient Architecture for Accurate and Low Power CMOS Analog Multiplier

A new analog four-quadrant multiplier in CMOS technology is proposed using translinear loops (TLs). The novelty of the work includes an improved structure resulting in high precision output, low power consumption and low body effect error. The higher accuracy is achieved using a symmetrical arrangement of the proposed multiplier, where the errors on the two sides of circuit are subtracted from each other. The simple structure, as well as the sharing bias branch in the squaring circuits, leads to the low power dissipation of the multiplier circuit. In addition, the proposed circuit is thoroughly analyzed in terms of the body effect error and the results are presented. In order to validate the performance of the circuit, the designed multiplier is used in two useful applications: frequency doubler and amplitude modulator. The post layout simulation results of the circuit are performed using Cadence Virtuoso and HSPICE with level 49 parameters (BSIM3v3) of TSMC 0.18[Formula: see text][Formula: see text]m technology. The results show a nonlinearity of 0.93%, a total harmonic distortion (THD) of 0.98% at a frequency of 1[Formula: see text]MHz, a [Formula: see text]3[Formula: see text]dB bandwidth of 736[Formula: see text]MHz and a maximum power dissipation of 0.0619[Formula: see text]mW.

CMOS Analog AGC for Biomedical Applications

In this paper, we present the design of an analog Automatic Gain Control with a small silicon area and reduced power consumption using a 0.5 μ m process. The design uses a classical approach implementing the AGC system with simple blocks, such as: peak detector, difference amplifier, four-quadrant multiplier, and inversor amplifier. Those blocks were realized by using a modified Miller type OPAMP, which allows indirect compensation, while the peak detector uses a MOS diode. The AGC design is simulated using the Tanner-Eda environment and Berkeley models BSIM49 of the On-Semiconductor C5 process, and it was fabricated through the MOSIS prototyping service. The AGC system has an operation frequency of around 1 kHz, covering the range of biomedical applications, power consumption of 200 μ W, and the design occupies a silicon area of approximately 508.8 μ m × 317.7 μ m. According to the characteristics obtained at the experimental level (attack and release time), this AGC can be applied to hearing aid systems.

Design of low power Teager Energy Operator circuit for Sleep Spindle and K-Complex extraction

This work presents an ultra-low-power subthreshold four-quadrant multiplier and a subthreshold programmable second order Butterworth Gm-C Low-Pass Filter (LPF) targeted for realizing optimized Teager Energy Operator (TEO). The ultra-low-power and low voltage strategies involve weak inversion biasing, reducing multiplier power consumption and eliminating summation block from the general TEO algorithm. The circuits dynamic range and bandwidths are designed for the Sleep Spindle (SS) and K-Complex (K–C) frequency range of the Electroencephalogram (EEG) signal. The ideal TEO response is initially modelled using MATLAB and Simulink in order to verify the theoretical basis. The final circuits are then simulated using Analog Devices’ LTSpice MOSFET models of 90 ​nm BSIM4 version 4.3 level 54. The multiplier simulations prove a dynamic range of ±40 ​mV ​at a supply voltage of 0.6 ​V with a linearity error of 2.6%. The Total Harmonic Distortion (THD) at 16 ​Hz for an input of 20 ​mV AC signal and another fixed input at 1 ​mV is 0.2159%. The LPF is operated at ± 0.6 ​V with a low static power consumption of 1.95 ​nW. Programmability of the LPF has control over both gain and bandwidth, offering the designer a choice over the group delay. The overall transient response of the TEO demonstrates its amplitude and frequency tracking capability in accordance with its theoretical performance. The final TEO circuit achieves the lowest static power consumption reported in the sleep research literature of 53.59 ​nW. This makes the proposed TEO circuit, the lowest power consuming joint EEG waveform detecting Application Specific Integrated Circuit (ASIC).

Highly linear CMOS subthreshold four-quadrant multiplier for Teager Energy Operator based Sleep Spindle detectors

This paper presents a subthreshold four-quadrant multiplier targeted for Teager Energy Operator (TEO) based Sleep Spindle detecting circuits. The proposed highly linear multiplier operates on balanced input-differential output signals at a 1.2 V supply. The multiplier is tested using 90 nm CMOS process of the BSIM3v3.3 model in Cadence Virtuoso. The simulation results prove an input dynamic range of ±240 μV with negligible non-linear deviations and zero offset. The Total Harmonic Distortion (THD) is shown to be less than 5% under 40 μV AC at 11 Hz. The third-order Input Intercept Point (IIP3) is at −22.6849 dB m. The bandwidth of the multiplier is 14.4544 MHz with stand-by power 82.14 nW. The stability of the proposed circuit was also tested using the same technology in LTSpice XVII for PVT variations.

Energy-Efficient Time-Domain Vector-by-Matrix Multiplier for Neurocomputing and Beyond

We propose an extremely energy-efficient mixed-signal ${N} \times {N}$ vector-by-matrix multiplication (VMM) in a time domain. Multi-bit inputs/outputs are represented with time-encoded digital signals, while multi-bit matrix weights are realized with adjustable current sources, e.g., transistors biased in subthreshold regime. The major advantage of the proposed approach over other types of mixed-signal implementations is very compact peripheral circuits, which would be essential for achieving high energy efficiency and speed at the system level. As a case study, we have designed a multilayer perceptron, based on two layers of 10 $ \times $ 10 four-quadrant multipliers, in 55-nm process with embedded NOR flash memory technology, which allows for compact implementation of adjustable current sources. Our analysis, based on memory cell measurements, shows that >6 bit operation can be ensured for larger ( ${N} >$ 50) VMMs. Post-layout estimates for 55-nm 6-bit VMM, which take into account the impact of PVT variations, noise, and overhead of I/O circuitry for converting between conventional digital and time domain representations, show ~7 fJ/Op for ${N} >$ 500. The energy efficiency can be further improved to POp/J regime for more optimal and aggressive designs.

Compact Design of High-Speed Low-Error Four-Quadrant Current Multiplier with Reduced Power Dissipation

In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18[Formula: see text][Formula: see text]m TSMC (level-49) CMOS technology. Simulation results with [Formula: see text]-V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the [Formula: see text][Formula: see text]dB bandwidth (BW) is 903[Formula: see text]MHz, the total harmonic distortion (THD) is 0.3% (at 1[Formula: see text]MHz), and the maximum and static power consumption are [Formula: see text]W and [Formula: see text]W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the [Formula: see text][Formula: see text]dB BW as 657[Formula: see text]MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed work’s performance.

Low power FGMOS-based four-quadrant current multiplier circuits

In this paper, low-power, high-speed four-quadrant analog multiplier circuits have been presented, based on simple current squarer circuits. The squarer circuits consist of a floating-gate MOS transistor, operating in saturation region plus a resistor. These multipliers have a unique property of greatly reduced power as they do not have any bias currents. For performance evaluation, the designs are simulated using HSPICE software in 0.18 µm (level-49 parameters) TSMC CMOS technology. Using ± 0.5 V DC supply voltages for the first design, the simulation resulted in a maximum linearity error of 0.8%, the − 3 dB bandwidth of 635 MHz, the Total Harmonic Distortion of 0.57% (at 1 MHz), and maximum and static power consumption of 40.4 and 5.75 µW, respectively. Corresponding values for the second design with 1 V DC supply voltage are 0.4%, 394.8 MHz, 0.72%, 44 and 11.4 µW, respectively. Furthermore, in order to verify the robustness and reliability of the proposed works, Monte Carlo analysis are performed. For the mentioned analysis, 5% variations in channel width and length, gate oxide thickness and threshold voltage of all transistors and resistance values are considered.

A 750-nW 1-MHz 9-tap analog finite impulse response filter for wireless senor network chip

This paper presents a low power Finite Impulse Response (FIR) filter based on discrete-time analog computing. The analog FIR filter is first presented to deal with analog signal. To improve linearity, two-double boost technique is introduced in the sample and hold cells which are used to achieve delay-time function. Meanwhile, the four-quadrant voltage-mode multiplier consists of PMOS substract cell and combiner cell, which is independent of device parameters. To realize the shift registers function, the rotating switch matrix circuit is adopted controlled by phase shift clocks. All MOS transistors implemented in this architecture are biased in subthreshold region with a supply voltage of 0.6 V to reduce the power consumption. Simulation results show that the analog FIR filter dissipates 750 nW at 1 MHz sample frequency and the effective number of bits of the proposed analog FIR filter is more than 7 bits. Compared to the conventional digital FIR filter, power consumption is reduced by 72.22% at 1 MHz in a 0.18μm CMOS process.

An Offset-free High linear Low Power High Speed Four-Quadrant MTL Multiplier

In this paper a new CMOS current-mode four-quadrant analog multiplier circuit is proposed. The major advantages of this design are high linearity, high speed and low power consumption. Removing dc offset is the most important improvement in this topology. The circuit is designed with 1.8V supply voltage and is simulated using HSPICE simulator by level 49 parameters in 0.18µm standard CMOS TSMC technology. The aspect ratios of the MOSFETs are optimized using Evolutionary algorithm by MATLAB. The simulation results of this analog multiplier demonstrate a maximum linearity error of 2.6%, a THD of 1.77%, maximum power consumption of 157 µW, -3dB bandwidth of 241MHz and almost free from dc offset.

Design of a new CMOS Low-Power Analogue Neuron

In this paper, a low-power analogue complementary metal oxide semiconductor (CMOS) artificial neuron circuit is presented. The analogue neuron is composed of multiplier and programmable activation function circuits. The proposed four-quadrant multiplier has a single ended current output which eliminates the extra summation circuit at the output of the neuron that reduces the chip area as well as power consumption. In addition, programmability of activation function improves the neural network design process while enables the proposed neuron circuit to be used properly in learning algorithms such as back propagation. The most important feature of the proposed circuit is low power consumption and simple circuit topology. The performance of the circuit is confirmed by HSPICE simulations using 0.18 μm CMOS technology parameters. The circuit operates at 1 V supply voltage and consumes only 15 μW. Finally, different neural networks are realized using the proposed neuron circuit, which are successfully used to solve exclusive OR (XOR) problem and region classification problem to verify the accuracy and performance of the proposed circuit.

A MOS translinear cell-based configurable block for current-mode analog signal processing

This paper, proposes a low-voltage/power, high-speed configurable analog block (CAB) for current-mode nonlinear computation. A novel MOS translinear cell (MTC), two local switch networks and PMOS-NMOS arrays are the basic building blocks of the proposed CAB. This MTC consists of two overlapped translinear loops using the MOS transistors operating in weak inversion region. The proposed CAB is capable to implement such current-mode analog computational processors as one- and four-quadrant multipliers, one- and two-quadrant dividers, squarer, full-wave rectifier (absolute-value), RMS to DC converter and much other. Post-layout plus Monte Carlo simulations of the proposed design with 0.18 µm (level-49 parameters) TSMC technology is performed that prove its superiority over some other advanced works and robustness against process, voltage and temperature variations. This superb feature plus many others, mostly, are due to the precise multilateral analysis and optimal compensate of mismatches and second order effects of the proposed circuit that led to proper selection of devices sizes and deliberate arrangement of the layout.

New CMOS Current-Mode Analogue to Digital Power Converter

The paper presents a completely new realization of a current-mode power detector employing a four-quadrant CMOS analogue multiplier, integrator, zero-crossing detectors and a grounded capacitor. Based on the value of the integration of the original input signals, a calculation is performed using the definition formulas. The product of input current signals was directly introduced into the integration circuit, and its digital equivalent was subsequently formed. Signal-processing-related errors and errors bound were investigated and presented in the paper. Simulation, performed using HSPICE with $$0.25\,\upmu \hbox {m}$$0.25μm technology, and experimental results confirmed the performance of the proposed circuit. The obtained results show that the scheme improves the detector's accuracy to over 1 %, while widening the operating frequency range to up to 100 MHz. The maximum power consumptions of converter at ±2.5 V supply voltages amount to approximately 8.37 mW.

Continuous‐time four‐quadrant modulator with inherent PVT cancellation

A continuous-time four-quadrant multiplier in subthreshold region is presented. Besides its simplicity, the structure features inherent process–voltage–temperature (PVT) variation cancellation while working under low voltage supply and dissipating an ultra-low power. The PVT variation was alleviated through an inherent log/anti-log cancellation technique, making it as a good candidate for bio-potential acquisition systems. The input and output signals are currents resulting in a wider bandwidth and larger dynamic range compared with the voltage-mode counterparts. The circuit is versatile and can be configured as a modulator, frequency doubler, and linear variable gain amplifier as shown in theory and simulation results.