Foundry Service Research Articles

MicroLED arrays—A perspective beyond displays

MicroLEDs, particularly when integrated with CMOS microelectronics, represent a significant advancement in nitride technology. While large-area, high-power LEDs for solid-state lighting have seen extensive optimization, microLEDs present unique fabrication and characterization challenges. Utilizing standard CMOS design and foundry services for silicon driver electronics, a new hybrid interconnect technology must be developed for chip–chip or wafer–wafer integration, necessitating much higher lateral resolution than current bonding technologies. Beyond display technology, microLED integration opens avenues for groundbreaking applications such as highly efficient nanosensors, miniaturized optical neuromorphic networks, and robust chip-based microscopy. This paper explores recent advancements in nitride/CMOS hybrid modules, providing an overview of current technologies and future possibilities in this dynamic field.

Suspended nanomembrane silicon photonic integrated circuits

Leveraging the low linear and nonlinear absorption loss of silicon at mid-infrared (mid-IR) wavelengths, silicon photonic integrated circuits (PICs) have attracted significant attention for mid-IR applications including optical sensing, spectroscopy, and nonlinear optics. However, mid-IR silicon PICs typically show moderate performance compared to state-of-the-art silicon photonic devices operating in the telecommunication band. Here, we proposed and demonstrated suspended nanomembrane silicon (SNS) PICs with light guiding within deep-subwavelength waveguide thickness for operation in the short wavelength mid-IR region. We demonstrated key building components, namely, grating couplers, waveguide arrays, micro-resonators, etc., exhibiting excellent performances in bandwidths, back reflections, quality factors, and fabrication tolerance. Moreover, we show that the proposed SNS PICs have high compatibility with the multi-project wafer foundry services. Our study provides an unprecedented platform for mid-IR integrated photonics and applications.

Interdependence and specialization in the global semiconductor industry

Interdependence between the United States (U.S.), European Union (EU) and Asia in the semiconductor industry, driven by specialization, can serve as a preventive measure against disruptions in the global semiconductor supply chain. Moreover, with rising geopolitical tensions, the cost-intensive nature of the semiconductor industry and a slowdown in demand, interdependence and partnership provide countries with opportunities and benefits. Specifically, by analyzing global trade patterns, developing the Interdependence Index within the semiconductor market, and applying the Grubel-Lloyd Index to the U.S., the EU, and Asian countries from 2011 to 2022, our findings reveal that interdependence enhances regional semiconductor supply chains, such as the establishment of semiconductor foundries in the U.S., Japan, and the EU; reduces dependence on a single supplier, such as the U.S. distancing from China; and increases market share in different semiconductor segments, as demonstrated by Taiwan in automobile chips. The evidence indicates that China heavily depends on foreign sources to meet its semiconductor demand, while Taiwan and South Korea specialize as foundry service providers with lower Interdependence Index values. The U.S. maintains a moderate level of dependence on semiconductor imports due to its strong presence in manufacturing and research, while the EU exhibits a relatively higher level of interdependence, emphasizing its reliance on semiconductor imports. The stage-specific analyses indicate that the U.S. and the EU rely on Asia for semiconductor devices, while China and Taiwan have a higher dependence on American intermediate inputs and European lithography machines.

Democratizing digital microfluidics by a cloud-based design and manufacturing platform.

Akin to the impact that digital microelectronics had on electronic devices for information technology, digital microfluidics (DMF) was anticipated to transform fluidic devices for lab-on-a-chip (LoC) applications. However, despite a wealth of research and publications, electrowetting-on-dielectric (EWOD) DMF has not achieved the anticipated wide adoption, and commercialization has been painfully slow. By identifying the technological and resource hurdles in developing DMF chip and control systems as the culprit, we envision democratizing DMF by building a standardized design and manufacturing platform. To achieve this vision, we introduce a proof-of-concept cloud platform that empowers any user to design, obtain, and operate DMF chips (https://edroplets.org). For chip design, we establish a web-based EWOD chip design platform with layout rules and automated wire routing. For chip manufacturing, we build a web-based EWOD chip manufacturing platform and fabricate four types of EWOD chips (i.e., glass, paper, PCB, and TFT) to demonstrate the foundry service workflow. For chip control, we introduce a compact EWOD control system along with web-based operating software. Although industrial fabrication services are beyond the scope of this work, we hope this perspective will inspire academic and commercial stakeholders to join the initiative toward a DMF ecosystem for the masses.

Tower Semiconductor Acquisition: Advancing Intels Presence in the Global Market

With the gradual implementation of the IDM strategy of Intel corporation, Intel moves faster toward its goal of dominating the worldwide foundry services and capacity market by giving it access to one of the most comprehensive portfolios of unique technologies. As a result, acquiring Tower for its specialized technologies and customer-first approach is a necessary step for progression of this strategy. This article aims to illustrate the reasons, analysis, and impact of it. The research unequivocally demonstrates that Intels acquisition of Tower will significantly impact the market competition landscape, technological innovation, and employment opportunities in the industry. This article gives a positive attitude to this acquisition, its a wise and appropriate choice for intel due to technical and military aspects. However, considering towers earnings in recent years have been modest, it could be suggested for leaders to make reasonable arrangements for the allocation of research and development. Facing this competitive race, intel needs to consider the future developing directions.

Study on the Ku band Solid-State Power Amplifier(SSPA) through the 40 W-grade High Power MMIC Development and the Combination of High Power Modules

In this paper, to substitute the existing TWTA(Travailing Wave Tube Amplifier) component in small radar system, we developed the Ku band SSPA(Solid-State Power Amplifier) based on the fabrication of power MMIC (Monolithic Microwave Integrated Circuit) chips. For the development of the 500 W SSPA, the 40 W-grade power MMIC was designed by ADS(Advanced Design System) at Keysight company with UMS GH015 library, and was processed by UMS foundry service. And 70 W main power modules were achieved the 2-way T-junction combiner method by using the 40 W-grade power MMICs. Finally, the 500 W SSPA was fabricated by the wave guide type power divider between the drive power amplifier and power modules, and power combiner with same type between power modules and output port. The electrical properties of this SSPA had 504 W output power, -58.11 dBc spurious, 1.74 °/us phase variation, and -143 dBm/Hz noise level.

Blazed subwavelength grating coupler

Short-wavelength mid-infrared (2–2.5 μm wave band) silicon photonics has been a growing area to boost the applications of integrated optoelectronics in free-space optical communications, laser ranging, and biochemical sensing. In this spectral region, multi-project wafer foundry services developed for the telecommunication band are easily adaptable with the low intrinsic optical absorption from silicon and silicon dioxide materials. However, light coupling techniques at 2–2.5 μm wavelengths, namely, grating couplers, still suffer from low efficiencies, mainly due to the moderated directionality and poor diffraction-field tailoring capability. Here, we demonstrate a foundry-processed blazed subwavelength coupler for high-efficiency, wide-bandwidth, and large-tolerance light coupling. We subtly design multi-step-etched hybrid subwavelength grating structures to significantly improve directionality, as well as an apodized structure to tailor the coupling strength for improving the optical mode overlap and backreflection. Experimental results show that the grating coupler has a recorded coupling efficiency of − 4.53 dB at a wavelength of 2336 nm with a 3-dB bandwidth of ∼ 107 nm . The study opens an avenue to developing state-of-the-art light coupling techniques for short-wavelength mid-infrared silicon photonics.

Japanese Semiconductor Industry’s Collaboration with Taiwan Semiconductor Manufacturing Company

On 17 December 2021, Japan granted administrative approval to Taiwan Semiconductor Manufacturing Co Ltd (TSMC) to build a US$7 billion semiconductor chip-manufacturing foundry in Japan. The collaboration between the Sony Group and the world’s No. 1 Taiwanese chipmaker is named Japan Advanced Semiconductor Manufacturing, Inc. and will provide foundry service with 22/28-nanometre capability. This joint venture has taken off due to mutual commercial interest and support from the Japanese and Taiwanese authorities.

Benchmark Tests of Atom Segmentation Deep Learning Models with a Consistent Dataset.

The information content of atomic-resolution scanning transmission electron microscopy (STEM) images can often be reduced to a handful of parameters describing each atomic column, chief among which is the column position. Neural networks (NNs) are high performance, computationally efficient methods to automatically locate atomic columns in images, which has led to a profusion of NN models and associated training datasets. We have developed a benchmark dataset of simulated and experimental STEM images and used it to evaluate the performance of two sets of recent NN models for atom location in STEM images. Both models exhibit high performance for images of varying quality from several different crystal lattices. However, there are important differences in performance as a function of image quality, and both models perform poorly for images outside the training data, such as interfaces with large difference in background intensity. Both the benchmark dataset and the models are available using the Foundry service for dissemination, discovery, and reuse of machine learning models.

Foundry Services for Quantum Chips

QuantWare launches Foundry Services for superconducting quantum chips

Review of polysilicon thermoelectric energy generators

Among the power generation for micro sensor and actuator in wireless sensor network (WSN), Internet of Things (IoT), and wearable devices applications, thermoelectric energy generators (TEGs) that can convert body heat into electricity without moving parts is considered most promising. With the advent of foundry services in IC industry over the past two decades, standard CMOS/BiCMOS process for microprocessors and micro actuators/sensors can be applied as a perfect platform for semiconductor TEGs. Many TEG designs have therefore adopted the mature, reliable, and high yield process, where the polysilicon layers facilitate high integration density of thermocouples on a wafer. This review aims at summarizing the progress of semiconductor TEGs from tailored MEMS process to commercially available standard CMOS/BiCMOS process. By comparing the reports in the open literature, semiconductor TEGs are shown to achieve performance competitive to the bismuth telluride (BiTe)-based TEGs. The performance of a semiconductor TEG can be improved by exploiting configuration design, thermocouple dimension and materials properties in modern silicon processing technology. State-of-the-art polysilicon TEGs have been shown to achieve power factor about 10 -1 ∼10 -2 μW/cm 2 K 2 and voltage factor 10 1 ∼10 2 V/cm 2 K. A 5 × 5 mm 2 TEG chip is capable of delivering more than 3 μW and over 3 V when operating at 10 K temperature difference in body temperature range.

Integrated Slow-Light Enhanced Silicon Photonic Modulators for RF Photonic Links

An integrated RF-photonic link that consists of a slow-light enhanced silicon (Si) electro-optic modulator, a single mode Si optical waveguide and a silicon-germanium (SiGe) photodetector was fabricated using a Si photonic standard foundry service. The third-order intermodulation distortion (IMD3) of the RF signals and the link spur-free dynamic range (SFDR) were characterized through a two-tone test method. The Si Mach-Zehnder modulator architecture is designed to have unequal arms to operate on a simplified driving scheme. As a result, on-chip thermal heaters can be omitted, and the modulator can configure near its quadrature point by adjusting the wavelength to the modulator. Owning to enhanced light-matter interaction in the slow-light region, an increased slope efficiency is observed in the modulator. By selecting the optimal DC bias to the grating and the reference arms of the modulator, a SFDR of 96 dB/Hz <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2/3</sup> can be obtained in the RF link at the slow light region. The slow-light modulator also displays increased modulation efficiency, allowing for a reduced footprint for large array integration.

Foundry Service of CMOS MEMS Processes and the Case Study of the Flow Sensor

The complementary metal-oxide-semiconductor (CMOS) process is the main stream to fabricate integrated circuits (ICs) in the semiconductor industry. Microelectromechanical systems (MEMS), when combined with CMOS electronics to form the CMOS MEMS process, have the merits of small features, low power consumption, on-chip circuitry, and high sensitivity to develop microsensors and micro actuators. Firstly, the authors review the educational CMOS MEMS foundry service provided by the Taiwan Semiconductor Research Institute (TSRI) allied with the United Microelectronics Corporation (UMC) and the Taiwan Semiconductor Manufacturing Company (TSMC). Taiwan’s foundry service of ICs is leading in the world. Secondly, the authors show the new flow sensor integrated with an instrumentation amplifier (IA) fabricated by the latest UMC 0.18 µm CMOS MEMS process as the case study. The new flow sensor adopted the self-heating resistive-thermal-detector (RTD) to sense the flow speed. This self-heating RTD half-bridge alone gives a normalized output sensitivity of 138 µV/V/(m/s)/mW only. After being integrated with an on-chip amplifier gain of 20 dB, the overall sensitivity of the flow sensor was measured and substantially improved to 1388 µV/V/(m/s)/mW for the flow speed range of 0–5 m/s. Finally, the advantages of the CMOS MEMS flow sensors are justified and discussed by the testing results.

Development of thermoelectric energy generator with high area density stacked polysilicon thermocouples

A semiconductor thermoelectric energy generator (TEG) with thermocouples in high area density is proposed in this work. Different from the common TEGs with co-planar thermocouples, the high area density is achieved by placing the P-thermoleg above the N-thermoleg into a stacked thermocouple, which is then insulated above and below by double cavity to retain sufficient thermal gradient. The TEG voltage factor is therefore increased by a factor of 2. For a TEG implemented by standard CMOS process (TSMC D35 2P4M), simulation shows that the stacked thermocouple of size 58 × 2 × 0.180 µm P-type thermoleg above 64 × 2 × 0.275 µm N-type thermoleg can reach optimal performance. Measurement results of a 5 × 5 mm2 TEG chip by semiconductor foundry service confirm the power factor of 0.075 μW/cm2K2 and the voltage factor of 7.004 V/cm2K are 1.7 x and 2.5 x, respectively, of that in TEG with co-planar thermocouples. This performance is the best of all TEGs with polysilicon thermocouples by standard CMOS process.

A Monolithic CMOS-MEMS Reconfigurable/Tunable Capacitive Accelerometer with Integrated Sensing Circuits

MEMS accelerometers have been widely used in various applications with a wide range of signal levels and bandwidth. Therefore it is desired to have a sensor whose characteristics such as sensitivity and bandwidth can be reconfigured/tuned depending on specific applications. This paper presents a reconfigurable/tunable z-axis accelerometer whose mechanical resonant frequency, sensitivity and sensing bandwidth can be tuned by the electrostatic spring softening effect. The proposed accelerometer was designed using a commercial 0.35 μm CMOS foundry service. The tuning electrodes were implemented in the metal and polysilicon layers in the standard CMOS process. An on-chip chopper stabilized readout circuit was designed to convert the capacitance signal to a voltage readout. The sensing structure was released by post-CMOS wet metal etching. Measurement results showed the proposed accelerometer had a sensitivity of 12 mV/g in the range of 0–5 g. The sensitivity and bandwidth tuning ranges are 50% and 18%, respectively, for an applied tuning voltage of 25 V. The demonstrated device is the first reconfigurable/tunable CMOS-MEMS accelerometer in the literature to our best knowledge.

Platicon microcomb generation using laser self-injection locking

The past decade has witnessed major advances in the development and system-level applications of photonic integrated microcombs, that are coherent, broadband optical frequency combs with repetition rates in the millimeter-wave to terahertz domain. Most of these advances are based on harnessing of dissipative Kerr solitons (DKS) in microresonators with anomalous group velocity dispersion (GVD). However, microcombs can also be generated with normal GVD using localized structures that are referred to as dark pulses, switching waves or platicons. Compared with DKS microcombs that require specific designs and fabrication techniques for dispersion engineering, platicon microcombs can be readily built using CMOS-compatible platforms such as thin-film (i.e., thickness below 300 nm) silicon nitride with normal GVD. Here, we use laser self-injection locking to demonstrate a fully integrated platicon microcomb operating at a microwave K-band repetition rate. A distributed feedback (DFB) laser edge-coupled to a Si3N4 chip is self-injection-locked to a high-Q ( > 107) microresonator with high confinement waveguides, and directly excites platicons without sophisticated active control. We demonstrate multi-platicon states and switching, perform optical feedback phase study and characterize the phase noise of the K-band platicon repetition rate and the pump laser. Laser self-injection-locked platicons could facilitate the wide adoption of microcombs as a building block in photonic integrated circuits via commercial foundry service.

Review of Silicon Photonics Technology and Platform Development

Many breakthroughs in the laboratories often do not bridge the gap between research and commercialization. However, silicon photonics bucked the trend, with industry observers estimating the commercial market to close in on a billion dollars in 2020 <xref ref-type="bibr" rid="ref45">[45]</xref>. Silicon photonics leverages the billions of dollars and decades of research poured into silicon semiconductor device processing to enable high yield, robust processing, and most of all, low cost. Silicon is also a good optical material, with transparency in the commercially important infrared wavelength bands, and is a suitable platform for large-scale photonic integrated circuits. Silicon photonics is therefore slated to address the world&#x0027;s ever-increasing needs for bandwidth. It is part of an emerging ecosystem which includes designers, foundries, and integrators. In this paper, we review most of the foundries that presently enable silicon photonics integrated circuits fabrication. Some of these are pilot lines of major research institutes, and others are fully commercial pure-play foundries. Since silicon photonics has been commercially active for some years, foundries have released process design kits (PDK) that contain a standard device library. These libraries represent optimized and well-tested photonic elements, whose performance reflects the stability and maturity of the integration platforms. We will document the early works in silicon photonics, as well as its commercial status. We will provide a comprehensive review of the development of silicon photonics and the foundry services which enable the productization, including various efforts to develop and release PDK devices. In this context, we will report the long-standing efforts and contributions that previously IME&#x002F;A^&#x002A;STAR and now AMF has dedicated to accelerating this journey.

Packaging of semiconductor thermoelectric energy generators with in-plane thermocouples and isolation cavities

With the advent of semiconductor foundry services, thermoelectric energy generator (TEG) by CMOS/BiCMOS process has been preferable for production yield, cost effectiveness, and device scalability. The thermocouples in semiconductor TEG often have thermal isolation cavity to reduce heat loss. Both die- and wafer-packaging are proposed in this work to seal the cavity, prevent moisture/dirt from contamination, and avoid short circuit condition in the thermocouples for TEG applications in wearable devices. For a TEG design by 3P6M (3 polysilicon layers and 6 metal layers) BiCMOS process, the die-level packaging by aluminum film of thickness 50 μm over the TEG is shown to be effective, though there is about 23 % temperature gradient loss by the packaging. The voltage factor is 18.22 V/cm2K, about 77 % of that before packaging. For a TEG design by 1P6M CMOS process, the wafer-level packaging by bonding two identical TEG device wafers is shown to have about 22 % loss in temperature gradient. Yet the TEG performance is increased significantly on the same footprint because of doubling area density, and hence doubling both the power factor and voltage factor. The power factor and voltage factor is 0.164 μW/cm2 K2 and 24.32 V/cm2K, respectively, on the TEG in series circuit after packaging.

Sensing Characteristic Enhancement of CMOS-Based ISFETs With Three-Dimensional Extended- Gate Architecture

As the CMOS-based ion-sensitive field-effect transistor (ISFET) is scaling down to achieve a compact sensing array with high spatial resolution, reduction of sensing layer capacitance attenuates capacitive coupling efficiency of environmental input signals and decreases sensitivity performance. To address this issue, a concept of three-dimensional (3D) sensing structure is proposed and examined in this study. This can increase the sensing layer capacitance for a given footprint area. Based on our designs, a series of 3D sensing structures can be implemented with a standard CMOS foundry service and CMOS-compatible post processes. Our experimental results show that an 8.5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> footprint design of the 3D sensing structure can obtain approximately 2-fold increase in transconductance compared with a traditional ISFET with the same footprint. This enables pH sensitivity to be improved 1.5-fold in current response and 1.15-fold in voltage response. Therefore, the proposed 3D-structure ISFET can pave the way toward an ISFET sensing array with high sensitivity and high spatial resolution.

Multi-Mode Lasers for Self-Forced Opto-Electronic Oscillators in Compact Frequency Synthesizers

Advanced telecommunication, imaging, and remote sensing systems require reliable ultra-high stability local oscillators. Particularly, coherent detection of digital data signals relies on a low aperture jitter of local oscillators in addition to high signal to noise ratio to achieve a very low bit-error-rate (BER). Frequency stabilized local oscillators are required with phase noise of smaller than −120 dBc/Hz at 10 kHz offset carrier and low aperture jitters of below 50 fs for RF sources of 10 GHz. Self-forced opto-electronic oscillation techniques of self- injection locking (SIL) combined with self-phase locking (SPLL) employ low loss long optical delays for frequency stabilizations through comparison of instantaneous signals and delayed versions. A compact design of multi-mode laser (MML) is presented here by employing self-forced oscillation combined with self-mode locking of an MML. Proof of concept of this novel approach is reported using a custom designed InGaAsP/InP chip using Smart Photonics foundry service, where multi-quantum well semiconductor optical amplifiers (SOA), carrier injection based phase modulator (PM), front and back (a common) distributed Bragg reflectors (DBR), and external electro-absorption modulators (EAM) are designed and physically modeled based on the foundry process design kit (PDK). A compact realization of self-mode locked MML with 5 modes to a fixed inter-modal oscillation frequency is presented, where the beat notes of the inter-modal oscillation are generated over X-band to form a frequency stabilized synthesizer. The PM bias control of two MLL lasers with common DBR is used to tune this opto-electronic oscillator from 11 GHz to 13 GHz with a frequency resolution of 110 kHz. Self-forced oscillation techniques of SILPLL combined with self-mode-locking (SML) has provided frequency synthesis with measured phase noise at 10 kHz offset (and aperture jitter) improved from −36 dBc/Hz (58ps) for the free-running MML to −92 dBc/Hz (68 fs) using SILPLL and SML of only 5 correlated modes. Analytical modeling has predicted that increasing the number of self-mode-locking modes from 5 to 13 will result in 18 dB improvement in phase noise. Performance comparison of this opto-electronic frequency synthesis method is made against various commercially available X-band frequency synthesizers that use full electrical solutions.