Forward Gate Bias Research Articles

Photoresponse of an oxide semiconductor photosensor

The authors investigated the photoresponse of a double-layer oxide semiconductor (GaInZnO–InZnO) thin-film transistor (TFT) under illumination, where the photocurrent in the negative gate bias region increased significantly without a negative shift in the threshold voltage. In particular, in the forward gate bias sweep direction (from −VG to +VG), the hysteresis of the transfer curves of the photosensor TFT became pronounced when the negative gate bias and its duration were increased. Additionally, the photocurrent level of the TFT remained almost the same as the level measured using a DC reverse gate bias sweep mode (from +VG to −VG). An analysis of the transfer curves, capacitance–voltage curves, and energy band diagrams indicates that the hysteresis characteristics can be explained by the competing effects of electrical-stress-induced defect generation and the screening of the negative gate bias by doubly positively charged oxygen vacancies depending on the gate bias polarity. In particular, the origin of the photoresponse of the photosensor TFT under illumination was studied intensively by qualitative analysis.

The Effect of Forward Gate Bias Stress on the Noise Performance of Mesa Isolated GaN HEMTs

This study investigates degradation of gallium nitride (GaN) high-electron mobility transistor (HEMT) noise performance after both dc and RF stress with forward gate current. The results are used to facilitate optimization of the robustness of GaN low-noise amplifiers (LNAs). It is shown that forward biasing the gate of a GaN HEMT results in permanent degradation of noise performance and gate current leakage, without affecting S-parameters and drain current characteristics. The limit of safe operation of the 2 × 50 μm devices in this study is found to be between 10 and 20 mW dissipated in the gate diode for both dc and RF stress. We propose that degradation could be caused by excessive leakage through the mesa sidewalls at the edges of each gate finger. Circuit simulations may be used together with device robustness rating to optimize LNAs for maximum input power tolerance. Using a resistance in the gate biasing network of 10 kΩ, it is estimated that an LNA utilizing a 2 × 50 μm device could withstand input power levels up to 33 dBm without degradation in noise performance.

Role of the dielectric for the charging dynamics of the dielectric/barrier interface in AlGaN/GaN based metal-insulator-semiconductor structures under forward gate bias stress

The high density of defect states at the dielectric/III-N interface in GaN based metal-insulator-semiconductor structures causes tremendous threshold voltage drifts, ΔVth, under forward gate bias conditions. A comprehensive study on different dielectric materials, as well as varying dielectric thickness tD and barrier thickness tB, is performed using capacitance-voltage analysis. It is revealed that the density of trapped electrons, ΔNit, scales with the dielectric capacitance under spill-over conditions, i.e., the accumulation of a second electron channel at the dielectric/AlGaN barrier interface. Hence, the density of trapped electrons is defined by the charging of the dielectric capacitance. The scaling behavior of ΔNit is explained universally by the density of accumulated electrons at the dielectric/III-N interface under spill-over conditions. We conclude that the overall density of interface defects is higher than what can be electrically measured, due to limits set by dielectric breakdown. These findings have a significant impact on the correct interpretation of threshold voltage drift data and are of relevance for the development of normally off and normally on III-N/GaN high electron mobility transistors with gate insulation.

Observation of threshold voltage instabilities in AlGaN/GaN MIS HEMTs

We report the investigation of threshold voltage (Vth) instability of AlGaN/GaN metal–insulator–semiconductor (MIS) HEMTs with SiN gate dielectric under forward gate bias stress. A systematic step stress-recovery experiment is implemented to study the charging and discharging kinetics of pre-existing defects. A two-step trapping process is identified: electron fast trapping into SiN/ GaN interface by tunneling through the thin GaN/AlGaN layer followed by the slow dynamics featuring a logarithmic time-dependence of the Vth shift. Full and fast recovery of the Vth instability is induced when devices are subjected to a large negative gate bias, while a slow and incomplete detrapping process occurs at Vg = 0 V. In addition, pulsed current–voltage measurements are developed to estimate trap densities and monitor defect generation before and after stressing.

Comprehensive Study of the Complex Dynamics of Forward Bias-Induced Threshold Voltage Drifts in GaN Based MIS-HEMTs by Stress/Recovery Experiments

The transient recovery characteristics of the threshold voltage drift (ΔVth) of GaN-based HEMTs with a SiO2 gate dielectric induced by forward gate bias stress are systematically and comprehensively investigated for stress times from 100 ns to 10 ks, recovery times from 4 μs to 10 ks, and stress biases from 1 to 7 V. The measured recovery data are analyzed using the concept of capture emission time maps. It is shown that the observed data cannot be explained by simple first-order defect kinetics. It is revealed that the recovery curves for constant stress times scale with the stress bias. Furthermore, the shape of the recovery curves changes from concave to convex with increasing stress time, independent of the stress bias. For short stress times and low stress bias, a dominant rate limiting effect of the III/N barrier layer is proposed. Defect-related physical processes with a broad distribution of characteristic time constants are discussed to explain the logarithmic time dependency of ΔVth stress and recovery, at which the role of the Coulomb feedback effect, complex defects, and spatially distributed defects are considered.

Atomic layer deposition of ZrO2 as gate dielectrics for AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors on silicon

In this Letter, the device performance of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MISHEMTs) on silicon substrate using 10-nm-thick atomic-layer-deposited ZrO2 as gate dielectrics is reported. The ZrO2 AlGaN/GaN MISHEMTs showed improved maximum drain current density (Idmax) with high peak transconductance (gmmax) as comparison to Schottky-barrier-gate HEMTs (SB-HEMTs). Also compared to SB-HEMTs, reverse gate leakage current was four orders of magnitude lower and forward gate bias extended to +7.4 V. At energy from −0.29 eV to −0.36 eV, low interface trap state density evaluated by AC conductance and “Hi-Lo frequency” methods indicates good quality of atomic-layer-deposited ZrO2 dielectric layer.

Very Fast Dynamics of Threshold Voltage Drifts in GaN-Based MIS-HEMTs

The very fast dynamics of threshold voltage drift (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) of GaN-based metal-insulator-semiconductor-HEMTs induced by forward gate bias stress is investigated with a simple oscilloscope based setup. We show that the logarithmic recovery time dependence of ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> , previously found for recovery times ranging from 10 ms up to 1 ms, extend even to the μs regime. Further, we observed an accumulation of ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> because of repetitive stress pulses of 100 ns. Consequences for device operation and reliability are discussed.

Random telegraph signal noise in gate current of unstressed and reverse-bias-stressed AlGaN/GaN high electron mobility transistors

Random telegraph signal (RTS) fluctuations with relative amplitude up to 50% are observed in forward and reverse gate current of unstressed and reverse-bias-stressed AlGaN/GaN high electron mobility transistors. Measurements of RTS amplitude and mean pulse widths as a function of forward gate bias indicate that the RTS is due to modulation of current along an intrinsic or stress-induced percolation path across the AlGaN-barrier by electron capture and emission on a trap within the barrier. Processes of electron capture from GaN to trap and subsequent tunneling to metal gate or electron exchange between GaN channel and the trap are considered.

A Very Robust AlGaN/GaN HEMT Technology to High Forward Gate Bias and Current

Reports to date of GaN HEMTs subjected to forward gate bias stress include varied extents of degradation. We report an extremely robust GaN HEMT technology that survived—contrary to conventional wisdom—high forward gate bias (+6 V) and current (&gt;1.8 A/mm) for &gt;17.5 hours exhibiting only a slight change in gate diode characteristic, little decrease in maximum drain current, with only a 0.1 V positive threshold voltage shift, and, remarkably, a persisting breakdown voltage exceeding 200 V.

AlGaN/GaN MOS-HEMTs With Gate ZnO Dielectric Layer

The vapor cooling condensation system is used to grow ZnO insulator films of low carrier concentration and high resistivity as the gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs). The saturation drain-source current and the maximum extrinsic transconductance are measured as 0.61 A/mm and 153 mS/mm, respectively. The gate leakage currents, determined with the forward gate bias of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 3.5 V and the reverse gate bias of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = -12 V, applied are 1.21 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> A/mm and 7.16 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> A/mm, respectively. The unit gain cutoff frequency and maximum frequency of the oscillation are also measured as 7.2 and 11.5 GHz, respectively. The low-frequency noise obtained is well fitted with a 1/f function in the linear region. Hooge's coefficient α is extracted as 9.74 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> when the MOS-HEMTs operate at 100 Hz and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = -4 V . The current recoveries of the gate and drain lags are determined to be 61% and 47% for the MOS-HEMTs, respectively.

Drain current enhancement and negligible current collapse in GaN MOSFETs with atomic-layer-deposited HfO 2 as a gate dielectric

Accumulation-type GaN metal–oxide-semiconductor field-effect-transistors (MOSFET’s) with atomic-layer-deposited HfO 2 gate dielectrics have been fabricated; a 4 μm gate-length device with a gate dielectric of 14.8 nm in thickness (an equivalent SiO 2 thickness of 3.8 nm) gave a drain current of 230 mA/mm and a broad maximum transconductance of 31 mS/mm. Owing to a low interfacial density of states ( D it) at the HfO 2/GaN interface, more than two third of the drain currents come from accumulation, in contrast to those of Schottky-gate GaN devices. The device also showed negligible current collapse in a wide range of bias voltages, again due to the low D it, which effectively passivate the surface states located in the gate-drain access region. Moreover, the device demonstrated a larger forward gate bias of +6 V with a much lower gate leakage current.

Organic Thin-Film Transistor Memory with Nanocrystal Carbon Dots

Organic thin-film transistor (OTFT) memory devices were fabricated with nanocrystal carbon (nc-C) dots incorporated into the pentacene/oxide interface in the active layer. The nc-C dots were arranged precisely in order on the OTFT channel region by a focused ion beam (FIB) technique using low-energy Ga + ions and phenanthrene as the carbon source. The structural information of nc-C dot arrays was obtained by scanning ion microscopy (SIM) and atomic force microscopy (AFM). These images indicate that the nc-C dot array was successfully formed on the oxide layer. The density of the two-dimensional nc-C dots was 1.3-1.5A—108 cm-2. The current-voltage (I-V ) characteristics showed that the OTFTs exhibit memory behavior upon the application of forward and reverse gate bias stresses. Depending on the polarity of gate bias, write and erase modes were induced, and a maximum threshold voltage shift I”Vth of 0.97 V was obtained. © The Surface Science Society of Japan.

A 2055-V (at 0.7 $\hbox{mA/cm}^{2}$) 24-A (at 706 $\hbox{W/cm}^{2}$) Normally On 4H-SiC JFET With 6.8- $\hbox{mm}^{2}$ Active Area and Blocking-Voltage Capability Reaching the Material Limit

A normally on 4H-SiC vertical-junction field-effect transistor (VJFET) of 6.8-mm2 active area was manufactured in seven photolithographic levels with no epitaxial regrowth and a single masked ion-implantation event. The VJFET exhibits low leakage currents with very sharp onsets of voltage breakdowns. At a forward gate bias of 2.5 V, the VJFET outputs 24 A (353 A/cm2) at a forward drain-voltage drop of 2 V (706 W/cm2), with a current gain of ID/IG = 21818, and a specific ON-state resistance of 5.7 mOmegaldrcm2. Self-aligned floating guard rings provide edge termination that blocks 2055 V at a gate bias of -37 V and a drain-current density of 0.7 mA/cm2. This blocking voltage corresponds to 94.4% of the VJFET's 11.7-mum/3.46 times 1015-cm3 SiC drift layer limit and is the highest reported blocking-voltage efficiency of any SiC power device under similar drain-current-density conditions.

Charge injection at carbon nanotube-SiO2 interface

Most single-wall carbon nanotube field-effect transistors show significant hysteresis in their transfer characteristics between forward and reverse gate bias sweeps. It was proposed that the hysteresis is due to a dynamic charging process at the carbon nanotube-dielectric interface. We have studied the charge injection and subsequent discharging processes at the carbon nanotube-SiO2 interface using electrostatic force microscopy. It was observed that the water layer assists charge diffusion on the dielectric surface.

AlGaN/GaN Metal–Oxide–Semiconductor High-Electron Mobility Transistors Using Oxide Insulator Grown by Photoelectrochemical Oxidation Method

A photoelectrochemical oxidation method was used to directly grow oxide layer on AlGaN surface. The annealed oxide layer exhibited beta-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and alpha-Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> crystalline phases. Using a photoassisted capacitance-voltage method, a low average interface-state density of 5.1 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> . eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> was estimated. The directly grown oxide layer was used as gate insulator for AlGaN/GaN MOS high-electron mobility transistors (MOS-HEMTs). The threshold voltage of MOS-HEMT devices is -5 V. The gate leakage currents are 50 and 2 pA at forward gate bias of VGS = 10 V and reverse gate bias of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = -10 V, respectively. The maximum value of g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> is 50 mS/mm of VGs biased at -2.09 V.

Nitric acid oxidation method to form SiO 2/3C–SiC structure at 120 °C

3C–SiC(0 0 1) surfaces are considerably rough with the roughness root mean square value ( R ms) of 1.3 nm, but the surfaces become considerably smooth (i.e., R ms of 0.5 nm) by heat treatment in pure hydrogen at 400 °C. Two-step nitric acid (HNO 3) oxidation (i.e., immersion in ∼40 wt% HNO 3 followed by that in 68 wt% HNO 3) performed after the hydrogen treatment can oxidize 3C–SiC at extremely low temperature of ∼120 °C, forming thick SiO 2 (e.g., 21 nm) layers. With no hydrogen treatment, the leakage current density of the 〈Al/SiO 2/3C–SiC〉 metal-oxide-semiconductor (MOS) diodes is high, while that for the MOS diodes with the hydrogen treatment is considerably low (e.g., ∼10 −6 A/cm 2 at the forward gate bias of 1 V) due to the formation of uniform thickness SiO 2 layers. The MOS diodes with the hydrogen treatment show capacitance–voltage curves with accumulation, depletion, and deep-depletion characteristics.

Evaluation of AlGaN/GaN‐HFET with HfAlO gate insulator

AbstractMetal‐insulator‐semiconductor (MIS) heterostructure field‐effect transistors (HFETs) fabricated with HfAlO as a gate insulator with high dielectric permittivity are demonstrated to achieve true enhancement‐mode operation with no gate leakage and high drain current density. Insertion of the HfAlO layer allows for forward gate bias voltages of up to +8 V without gate leakage (maximum gate current density of 1.2×10–5 mA/mm at +8 V gate bias) under direct current operation. Utilizing the extended forward gate bias swing, a maximum drain current density of 767 mA/mm is achieved, substantially higher than that of the non‐insulated HFET (427 mA/mm). A recessed‐gate MIS‐HFET with the HfAlO gate insulator exhibits a threshold voltage of +2.0 V and zero transconductance below a gate bias of +0.9 V, demonstrating true enhancement‐mode operation for the first time in recessed‐gate AlGaN/GaN‐HFETs with a maximum drain current density of 253 mA/mm at +5 V (© 2007 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

High-performance GaAs metal-insulator-semiconductor field-effect transistors enabled by self-assembled nanodielectrics

High-performance GaAs metal-insulator-semiconductor field-effect-transistors (MISFETs) fabricated with very thin self-assembled organic nanodielectrics (SANDs), deposited from solution at room temperature, are demonstrated. A submicron gate-length depletion-mode n-channel GaAs MISFET with SAND thicknesses ranging from 5.5to16.5nm exhibit a gate leakage current density &amp;lt;10−5A∕cm2 at a gate bias smaller than 3V, a maximum drain current of 370mA∕mm at a forward gate bias of 2V, and a maximum intrinsic transconductance of 170mS∕mm. The importance of appropriate GaAs surface chemistry treatments on SAND/GaAs interface properties is also presented. Application of SANDs to III-V compound semiconductors affords more opportunities to manipulate the complex III-V surface chemistry with broad materials options.

Enhancement-Mode$hboxSi_3hboxN_4hbox/AlGaN/GaN$MISHFETs

Enhancement-mode Si3N4/AlGaN/GaN metal-insulator-semiconductor HFETs (MISHFETs) with a 1-mum gate footprint are demonstrated by combining CF4 plasma treatment technique and a two-step Si3N4 deposition process. The threshold voltage has been shifted from -4 [for depletion-mode HFET] to 2 V using the techniques. A 15-nm Si3N4 layer is inserted under the metal gate to provide additional isolation between the gate Schottky contact and AlGaN surface, which can lead to reduced gate leakage current and higher gate turn-on voltage. The two-step Si 3N4 deposition process is developed to reduce the gate coupling capacitances in the source and drain access region, while assuring the plasma-treated gate region being fully covered by the gate electrode. The forward turn-on gate bias of the MISHFETs is as large as 7 V, at which a maximum current density of 420 mA/mm is obtained. The small-signal RF measurements show that the current gain cutoff frequency (fT) and power gain cutoff frequency (fmax) are 13.3 and 23.3 GHz, respectively

Enhancement-Mode High Electron Mobility Transistors Lattice-Matched to InP Substrates Utilizing Ti/Pt/Au Metallization

Enhancement-mode high electron mobility transistors (EHEMTs) were fabricated on In0.52Al0.48As/In0.53Ga0.47As heterostructures lattice-matched to InP substrates. Vertical scaling of device heterostructures was carried out to realize a positive threshold voltage with Ti/Pt/Au gates. Submicron EHEMTs utilizing Ti/Pt/Au were fabricated and their performances were compared with those of conventional EHEMTs with buried-Pt gates. DC I–V characteristics of both devices exhibited excellent pinch-off characteristics and very low output conductance. Output conductance measured for both devices showed that EHEMTs exhibit smaller kink effects than normal depletion-mode HEMTs (DHEMTs) due to the operating mode of EHEMTs with forward gate bias. EHEMTs with 0.18 µm Ti/Pt/Au gates exhibited a threshold voltage of 100 mV, peak transconductance of 810 mS/mm, and unity current-gain cut-off frequency ( fT) of 150 GHz, while those with buried-Pt gates exhibited a threshold voltage of 300 mV, peak transconductance of 880 mS/mm, and unity current-gain cut-off frequency ( fT) of 100 GHz. Studies on the thermal stabilities of the two types of gate metallization have been carried out. The Ti/Pt/Au gates exhibited better thermal stability than Pt/Ti/Pt/Au gates in terms of variation of threshold voltages and maximum transconductance values at elevated temperatures.