Forward Gate Bias Research Articles

Investigation of carrier transport and recombination at type-II band aligned p-NiO/AlGaN interface in p-NiO gate AlGaN/GaN HEMTs under forward bias

In this work, fine carrier transport and recombination processes in p-NiO gate AlGaN/GaN high electron mobility transistors were investigated by analyzing their electroluminescence under forward gate bias, with photoluminescence spectrum as a reference. Red luminescence with a peak of 1.9 eV was captured when the gate bias voltage exceeded 4 V, which was verified to originate from the tunneling enhanced interface recombination of injected holes from the gate metal and spilled electrons from the 2DEG channel at the type-II band aligned p-NiO/AlGaN heterostructure interface. Under higher gate bias voltage, holes were further injected into the GaN buffer layer, producing ultraviolet luminescence and yellow luminescence, corresponding respectively to the band edge emission and defect-assisted radiative recombination of GaN. Threshold voltage shift measurements under forward gate bias were conducted to further investigate the carrier transport and recombination processes.

In-situ S/TEM DC biasing of p-GaN/AlGaN/GaN heterostructure for E-mode GaN HEMT devices

This work describes an in-situ electrical DC bias study of the E-mode GaN high electron mobility transistor (HEMT) device. A single transistor structure is biased and studied in real-time. The sample was made from an E-mode GaN HEMT device using Focused Ion Beam (FIB) milling and upright lift-off. The device lamella is subjected to forward gate bias to understand the device operation and physical changes under the bias. Active device area and micron level changes due to biasing were studied and identified as crucial factors affecting device reliability during continuous operation. Electric bias-induced physical changes are observed at the p-GaN layer and AlGaN interface on the p-GaN and GaN sides. Localized damage and defect formation, along with elemental diffusion, is observed. The formation of new defects over existing growth defects was seen in the p-GaN/AlGaN/GaN heterostructure. The study helped us identify the exact location of the failure, the region affected under bias, and the occurrence of physical changes due to the electrical bias on the in-situ device. Based on the study, gate breakdown failure and its location at the metal/p-GaN interface are understood to result from physical changes activated by electrical bias.

Evaluation of p-GaN HEMTs degradation under high temperatures forward and reverse gate bias stress

In this study, the degradation behavior and physical mechanism of the p-GaN HEMT devices under high-temperature gate bias (HTGB) with +5 V and −5 V were investigated. The DC characteristics show that the device after forward HTGB stress exhibits an obvious negative threshold voltage (Vth ) shift, while the device after reverse HTGB exhibits a negligible shift. The following explanations could be given for the deterioration mechanism: a portion of the two-dimensional hole gas (2DHG) accumulated in the p-GaN layer at the p-GaN/AlGaN interface under long-term forward bias may fill the trap in the AlGaN layer through the tunneling effect. In addition, the drain-source on-resistance of the device had increased after +5 V HTGB stress, and a distinct decrease of accumulated capacitance was observed in the Cg -Vg curve. It indicates a degradation of the gate quality of the device after applying a forward-biased HTGB stress.

Investigation of time-dependent gate dielectric breakdown in recessed E-mode GaN MIS-HEMTs using ferroelectric charge trap gate stack (FEG-HEMT)

The aim of achieving E-mode operations has led to the proposal of novel hybrid ferroelectric charge trap gate stack schemes. These schemes involve utilizing a combination of the charge trapping layer (CTL) and the ferroelectric laminated layer to positively shift the threshold voltage to a normally-off margin after initializing the gate pulse, thus achieving the Enhancement-mode (E-mode) characteristic. This study focuses on the forward gate bias time-dependent dielectric breakdown (TDDB) gate reliability in the E-Mode GaN MIS-HEMTs using ferroelectric charge trap gate stack (FEG-HEMT) with and without recess and investigates the impact of temperature on TDDB. The gate voltages required for operation with a 1 % failure rate over a 10-year period are 12.95 V and 10.22 V at 25 °C and 150 °C for both samples, respectively. Also, the examination of the stability of the recessed process by calculating the activation energies (0.7 eV) of both samples are demonstrated. The article also investigates the relationship between long-term reliability and short-term initialization by examining the transition point of the time-dependent failure curve.

Investigation of the time dependent gate dielectric stability in SiC MOSFETs with planar and trench gate structures

In this work, the time-dependent dielectric breakdown (TDDB) analysis is performed to understand the gate oxide reliability in SiC MOSFETs with two different structures, i.e., planar and trench gate structures. We have discovered different gate leakage current behaviors between the SiC MOSFETs with planar gate (Sample A) and trench gate (Sample B) during the forward gate bias stress. Notably, the slight increase of the gate current during the stress and the negative activation energy (Ea = −0.07 eV) observed in Sample A suggest that the hole generation caused by the impact ionization can be occurred during the forward gate TDDB tests. Furthermore, the SiC MOSFETs with trench gate structure (Sample B) exhibit the operation voltage of 55.7 V (exponential law) and 57.3 V (power law) for the 0.001 % failure of 30 years under 175 °C, indicating that SiC trench gate MOSFETs with enough thick gate dielectric (87.1 nm (bottom) and 77.9 nm (sidewall)) can have the promising forward gate TDDB stability.

New Methodology for Parasitic Resistance Extraction and Capacitance Correction in RF AlGaN/GaN High Electron Mobility Transistors

This paper presents a novel approach to the efficient extraction of parasitic resistances in high electron mobility transistors (HEMTs). The study reveals that the gate resistance value can be accurately determined under specific forward gate bias conditions (Vg = 1.0 V), although the gate resistance value becomes unreliable beyond this threshold (Vg > 1.0 V) due to potential damage to the Schottky contact. Furthermore, by examining the characteristics of the device under a cold-FET bias condition (Vds = 0 V), a linear correlation between the gate and drain current is identified, enabling an estimation of the interdependence between the drain and source resistance using the proposed method. The estimation of parasitic pad capacitance (Cpg and Cpd) from Dambrine’s model is refined by incorporating the depletion layer capacitance on the gate side during the pinch-off condition. To validate the accuracy of the extracted parasitic capacitance and resistance values obtained from the new method, small-signal modeling is performed on a diverse range of measured devices.

Persistent charge storage and memory operation of top-gate transistors solely based on two-dimensional molybdenum disulfide

We fabricate top-gate transistors on the three-layer molybdenum disulfide (MoS2) with three, two, and one layers in the source and drain regions using atomic layer etching (ALE). In the presence of ALE, the device at zero gate voltage can exhibit high and low levels of drain current under the forward and reverse gate bias, respectively. The hysteresis loop on the transfer curve of transistor indicates that two distinct charge states exist in the device within a range of gate bias. A long retention time of the charge is observed. Unlike conventional semiconductor memories with transistors and capacitors, the two-dimensional (2D) material itself plays two parts in the current conduction and charge storage. The persistent charge storage and memory operation of the multilayer MoS2 transistors with thicknesses of a few atomic layer will further expand the device application of 2D materials with reduced linewidths.

A distributed small signal model extraction method based on FW-EM simulation for InP HEMT

In this paper, a method for 0.1 µm InP HEMT parameters extraction using Full-wave Electromagnetic(FW-EM) simulation is proposed. The parasitic capacitances are divided into pad and electrode capacitances to describe the distributed effects. Based on the extrinsic equivalent circuit, five standards are proposed to determine the parasitic capacitances and inductances using FW-EM simulation. Additionally, as ohmic contact resistance cannot be acquired using FW-EM simulation, parasitic resistances are determined using a Cold-Fet method without forward gate bias. Multi-bias extraction for various device sizes has been used to validate the accuracy and robustness of the suggested extraction approach, and the results indicate good agreement from 0.1 to 40 GHz.

Design of normally-off p-GaN/AlGaN/GaN heterojunction field-effect transistors with re-grown AlGaN barrier

In this paper, a novel p-GaN/AlGaN/GaN HFET with re-grown AlGaN is designed by using Silvaco TCAD. It demonstrates that a thin AlGaN barrier with relatively small Al content beneath the p-GaN positively shifts the threshold voltage and helps to obtain normally-off operation, while it also degrades the drain current obviously due to the low 2DEG concentration. On the other hand, the re-grown AlGaN barrier in the access regions can recover the 2DEG concentration and enhance the drain current partially. In addition, the field plate structure formed during the AlGaN re-growth process is beneficial to suppress the electric filed crowding and premature breakdown effectively under forward gate bias. By optimizing the device parameters, normally-off p-GaN/AlGaN/GaN HFET with balanced output current, threshold voltage and breakdown voltage is designed.

Current transport dynamics and stability characteristics of the NiO x based gate structure for normally-off GaN HEMTs

The application of p-type oxide typified with NiO x as cap layer in AlGaN/GaN high electron mobility transistor for normally-off operation has specific benefits, including etching free fabrication process, high hole density and elimination of Mg dopants diffusion effects. This work presents a device configuration exploration combining the p-NiO x gate cap layer and a thin AlGaN barrier layer. Calculation method for the threshold voltage has been discussed, which obtains good consistence with the experimental measurements. In addition, a nitrogen based post-annealing process was developed to improve the film stoichiometry for elevated gate controllability, realizing normally-off operation with enhanced channel conduction capability. The current transport dynamics in the gate stack as coupled with the NiO x /AlGaN interface states have also been studied, where a deep level trap was recognized in dominating the gate current characteristics and the gate stability performance under different forward gate bias conditions.

Impact of the Low Temperature Ohmic Contact Process on DC and Forward Gate Bias Stress Operation of GaN HEMT Devices

In AlGaN/GaN high electron mobility transistors (HEMTs), high temperature processes (such as ohmic annealing with >800°C value) could deform the crystal structure and induce trap states within the bulk and surface. Expanded defect densities cause crucial problems, such as threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula> ) instability, current collapse, and high leakages. In this work, a low temperature ohmic contact process (630°C, 10 minutes) is adopted with recess etch, and contact resistances <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; 0.1\Omega ~\cdot $ </tex-math></inline-formula> mm with low sheet resistances are achieved. The positive impact of this low thermal budget process on surface morphology, DC operation, long-term stability, and forward gate bias stress of the device is studied.

Low-temperature characteristics and gate leakage mechanisms of LPCVD-SiNx/AlGaN/GaN MIS-HEMTs

In this paper, we systematically investigated the static properties and gate current mechanism of low-pressure chemical vapor deposition-SiNx/AlGaN/GaN metal–insulator–semiconductor-high-electronmobility-transistor (MIS-HEMTs) at cryogenic temperature range from 10 K to 300 K. It is found that the threshold voltage of the device shows a positive shift due to the decreased carrier concentration at low temperature, and both the maximum transconductance and ON-resistance are improved at the low temperatures because of the enhanced electron mobility. Under very low electric field, the gate leakage exhibits ohmic conduction. With increasing forward gate bias, the dominant gate leakage mechanism at temperature below150 K gradually transits into trap-assisted tunneling, participating with a deep trap energy level of 0.73 eV in the SiNx dielectric, to Fowler–Nordheim (FN) tunneling. In contrast, the dominant gate leakage mechanism at temperature above 150 K transits from Poole–Frenkel emission, showing a low trap barrier height of 56 meV in the SiNx dielectric, to Fowler–FN tunneling with increasing forward gate bias. Under high reverse gate bias, carrier-limited gate current becomes the dominated gate leakage mechanism.

Gate-Bias Induced Threshold Voltage (V TH) Instability in P-N Junction/AlGaN/GaN HEMT

In this work, we studied the threshold voltage ( <formula> <tex>$V_{TH}$</tex> </formula> ) instability in E-mode p-n junction (PNJ)/AlGaN/GaN high-electron-mobility transistor (HEMT) using pulsed-I/V measurement and positive bias temperature instability (PBTI) test. <formula> <tex>$V_{TH}$</tex> </formula> shifts positively under forward gate bias, which is ascribed to electron trapping in the gate-stack region. Benefiting from the special p-GaN/n-GaN junction, reduced electric field suppresses electron trapping in the PNJ gate, resulting in more stable <formula> <tex>$V_{TH}$</tex> </formula> compared with the conventional Schottky-type p-GaN gate. Specifically, less positive threshold voltage shift ( <formula> <tex>$V_{TH}$</tex> </formula> ) is observed under higher temperatures, or after being stressed for a prolonged period with gate bias exceeding 6 V. The decrease in positive <formula> <tex>$V_{TH}$</tex> </formula> results from enhanced hole injection and especially hole trapping in the p-GaN/n-GaN interdiffusion region, which compensates for electron trapping and reduces positive <formula> <tex>$V_{TH}$</tex> </formula> .

Method to Distinguish Between Buffer and Surface Trapping in Stressed Normally-ON GaN GITs Using the Gate-Voltage Dependence of Recovery Time Constants

Drain current recovery transients are analyzed in normally-ON (NON) gate injection transistors (GITs) subjected to different kinds of stress. The recovery is measured as a function of forward gate bias, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}$ </tex-math></inline-formula> , which controls the number of holes injected from the gate and speeds up the recovery. Unlike conventional normally-OFF GITs, the newly designed NON GIT test structures allow simple characterization of buffer trapping during back-gating. By comparing the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}$ </tex-math></inline-formula> -dependence of recovery time constants for OFF-state and semi- ON state stress with those obtained from back-gating experiments we are able to distinguish between buffer and surface trapping. Our approach is simple and does not require time-consuming temperature-dependent measurements. It is found that OFF-state stress causes negative charge accumulation in the buffer, while semi- ON state stress leads to accumulation in both, buffer and surface. The use of NON GITs enables to measure the recovery time constants related to the buffer over a wide span of six orders of magnitude ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{4}}$ </tex-math></inline-formula> –100 s).

Time-Resolved Threshold Voltage Instability of 650-V Schottky Type p-GaN Gate HEMT Under Temperature-Dependent Forward and Reverse Gate Bias Conditions

A research on time-resolved threshold voltage instability of 650-V Schottky type p-GaN gate Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.2</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.8</sub> N/GaN high electron mobility transistor (HEMT) under high-temperature gate bias (HTGB) conditions has been carried out. Both forward and reverse bias conditions are applied. We found that the threshold voltage of p-GaN AlGaN/GaN HEMT shifts negatively under high-temperature forward gate bias (HTFB), while shifts positively under high-temperature reverse gate bias (HTRB). Negative threshold voltage shifts under forward gate bias are largely due to the trapped positive charges (holes) caused by existing defects in the AlGaN layer. The holes are from the accumulated 2-D hole gas (2DHG) in the p-GaN layer near the p-GaN/AlGaN interface, which may be partially filled into the AlGaN layer by tunneling effect. Therefore, negative threshold voltage shifts under HTFB are temperature-independent. Positive threshold voltage shifts under reverse gate bias are from the hole emission in the p-GaN layer and the trapped negative charges (electrons) in the AlGaN layer. The electrons are trapped by defects resulted from the created hot holes in high temperature. The positive threshold voltage shift under HTRB is temperature-dependent, where higher temperature leads to a larger positive threshold voltage shift.

Investigation of the threshold voltage instability in normally-off p-GaN/AlGaN/GaN HEMTs by optical analysis

A normally-off p-GaN/AlGaN/GaN high-electron-mobility transistor (p-GaN HEMTs) with a semitransparent gate electrode was investigated. Under forward gate bias, electroluminescence (EL) emission was observed which demonstrated the hole injection in the gate heterostructure. The hole injection emerged at a gate bias of 3.5 V and was significantly enhanced when the gate bias was larger than 6 V, the corresponding EL emission intensity was increased by approximately 100 times. It was also found that the electron injection and trapping in the p-GaN resulted in the threshold voltage (V TH) instability of the p-GaN HEMTs, while the hole injection resulted in the electron–hole recombination and the suppression of electron trapping. The carrier injection dynamics in the p-GaN gate region were quantitatively identified at different temperatures. Finally, the GaN band-edge ultraviolet emission with an energy of 3.4 eV was demonstrated as the most effective component in EL emission for V TH instability suppression in the p-GaN HEMTs.

Electroluminescence from a Schottky-type p-GaN gate structure

In this paper, we fabricate a Shcottky-type Ni/p-GaN/AlGaN/GaN device, and investigate its electroluminescence characteristics under the different forward bias voltages and at different temperatures. We find that when a forward gate bias is greater than 4 V, the electroluminescence comes from the p-GaN layer, indicating that electrons are injected from the channel into the p-GaN layer. While the forward gate bias is higher than 6 V, the GaN band edge emission emerges, indicating that the holes start to be injected into the channel region. As the temperature increases, the intensity of electroluminescence increases significantly, which reveals that the hole injection at the Ni/p-GaN interface is thermally enhanced. This work is essential for comprehensive understanding and improving the stability and reliability of the p-GaN gate power devices.

High voltage carrier stored trench bipolar transistor with common anode polysilicon diodes gate structure for low Miller capacitance and low electromagnetic interference noise

A novel 3300 V high voltage carrier stored trench bipolar transistor (CSTBT) with common anode polysilicon diodes gate structure (CAPD-CSTBT) is proposed. The PN junctions and N+ emitter region in the polysilicon gate structure are beneficial for reducing the Miller capacitance by 88.1% and the input capacitance by 26.0%, while due to the polysilicon PN junction barrier, the forward and reverse gate bias voltage will not be affected. As a result, the transient energy loss could be decreased by 32.2% with the same range of R g. Since the displacement current is shielded by the embedded emitter on the bottom of the CAPD gate structure, the (dI CE /dt)max/I Load is lower than that of the Fin-P-CSTBT by 81.8% on average with the same range of turn-on energy loss. Furthermore, the proposed structure features a 58.7% lower (dV KA /dt)max/V cc value for the free-wheeling diode on average. By Fourier transformation, the proposed structure represents lower amplitudes for the I CE and V KA spectrums during the turn-on period, which is a drastic suppression of electromagnetic interference noise.

High‐Current‐Density Enhancement‐Mode Ultrawide‐Bandgap AlGaN Channel Metal–Insulator–Semiconductor Heterojunction Field‐Effect Transistors with a Threshold Voltage of 5 V

Enhancement‐mode ultrawide‐bandgap Al0.65Ga0.35N/Al0.4Ga0.6N metal–insulator–semiconductor heterojunction field‐effect transistors are demonstrated using fluorine‐plasma treatment for threshold voltage control and Al2O3 as gate dielectric. The device exhibits a threshold voltage of 5 V, a maximum drain current density of 105 mA mm−1, and a transconductance of 19 mS mm−1. In addition, the capability to achieve low off‐state current density at 3–4 × 10−9 mA mm−1, an exceptionally low gate leakage current density of 1.4 × 10−8 mA mm−1 even at a high forward gate bias of VGS = 12 V, and a current on/off ratio &gt;1010 is shown. Small signal measurement shows that the device has a unity current gain cutoff frequency fT of 3.8 GHz and power gain cutoff frequency fmax of 4.5 GHz.

Electron transport of perovskite oxide BaSnO3 on (110) DyScO3 substrate with channel-recess for ferroelectric field effect transistors

We report an electron transport study of an La-doped perovskite oxide BaSnO3 thin film grown by molecular beam epitaxy on (110) DyScO3 as a function of electron concentration, by etching the film step-by-step with nanometer precision. Inductively coupled plasma-reactive ion etching with BCl3/Ar plasma is used for etching depth control. The local doping and electron density are experimentally determined after each etching step. The results show that the electron mobility is dominated by threading dislocations if the electron concentration is below 7.8 × 1019 cm−3, while ionized impurities and phonon scattering become more dominant at electron concentrations greater than 1.2 × 1020 cm−3. The charging state of thread dislocations is estimated to be 6.2. Furthermore, using the etch process to control the electron concentration and channel thickness, a gate-recessed ferroelectric field effect transistor is fabricated with 10 nm HfO2 as a gate dielectric. The device exhibits a saturation current of 29.9 mA/mm with a current on/off ratio of Ion/Ioff = 8.3 × 108 and a ferroelectric polarization charge density of 1.9 × 1013 cm−2. Under the forward gate bias sweep, the device operates in the enhancement mode with a threshold voltage of 3 V. Under the reverse gate sweeping bias, the device operates in the depletion mode with a threshold voltage of –1.5 V.