Forward DCT Research Articles

A fast and concise parallel implementation of the 8x8 2D forward and inverse DCTs using halide

The Discrete Cosine Transform (DCT) is commonly used for image and video coding and very efficient implementations of the forward and inverse transforms are of great importance. The popular libjpeg-turbo library contains handwritten, highly-optimised assembly language DCT implementations utilizing SIMD instruction sets for a variety of architectures. We present an alternative approach, implementing the 8x8 IDCT and FDCT written in the functional image processing language Halide. We show how less than 200 lines of Halide can replace over 20,000 lines of code the libjpeg-turbo library to perform JPEG encoding and decoding. The Halide implementation is compared for ARMv8 NEON and x86-64 SIMD extensions and shows a 5–25 percent performance improvement over the SIMD code in libjpeg-turbo for decoding and a 10–40 percent improvement for encoding. The Halide code is significantly easier to maintain and port to new architectures than the existing code.

A Structured Fast Algorithm for the VLSI Pipeline Implementation of Inverse Discrete Cosine Transform

The forward and inverse DCT has many applications in digital signal processing area, but, due to its high arithmetic complexity, it is necessary to find efficient software implementations or even to find VLSI implementations for them. Existing fast algorithms for IDCT or DCT have a SFG graph that is not very regular and modular and, even more importantly, the topology of the interconnection network is not easy to implement in VLSI due to the so-called retrograde indexing. Due to this problem, there are few pipeline implementations for IDCT and DCT, although pipelining is an efficient engineering solution that allows high speed performance with a reduced hardware complexity and power consumption. In this paper, we present an efficient solution to successfully reformulate the IDCT algorithm with a focus on developing a modular and regular computation structure that can be easily implemented using a pipelined VLSI architecture. Using new restructuring input sequences that can be computed in parallel with the new SFG graph in a pipeline manner, a novel efficient fast algorithm for the computation of inverse discrete cosine transform is presented. The obtained SFG graph has the best structure that can be obtained for IDCT, avoiding the so-called retrograde indexing and being highly regular and modular. Moreover, the obtained SFG graph is scalable, being easy to extend to larger values of N that is a power of 2. It can also be used to obtain a generalization of a radix-2 algorithm for length $$N = p \cdot 2^{m}$$ , where “p” is a prime number. This algorithm is based on a recursive decomposition of the computation of the inverse DCT that requires a reduced number of arithmetic operations and has a regular and simple computational structure that can be easily implemented in VLSI in a pipeline manner. Its main advantages are its simple, regular and modular computational structure and its high potential to be pipelined so that it can be used to obtain an efficient pipeline VLSI implementation.

Watermark Visibility Adjustable RVW Scheme for JPEG Images

In digital images, visible watermarks are embedded to convey the ownership information directly to the world so that copyright violations can be prevented. The removable visible watermarking (RVW) techniques allow the authorized user to remove the watermark from the watermarked image and restore the host image with permissible loss. Usually the visibility of the watermark can’t be increased or decreased based on the application requirement. In most of the commercial communication, JPEG images are used over the internet because of its reduced size. In this paper a RVW scheme is proposed for JPEG images which allows the user to embed watermark in the host image with variable visibility levels. In this scheme, the watermark embedding is performed by modifying the frequency coefficients of host image during forward Discrete Cosine Transform phase of JPEG compression. Inverse operation is performed to remove the watermark and to recover the host image. Watermark key is used to enhance the security of watermarking scheme. Quality metrics of visible watermarking technique are confirmed through experiments.

Implementation of computation-reduced DCT using a novel method

The discrete cosine transform (DCT) performs a very important role in the application of lossy compression for representing the pixel values of an image using lesser number of coefficients. Recently, many algorithms have been devised to compute DCT. In the initial stage of image compression, the image is generally subdivided into smaller subblocks, and these subblocks are converted into DCT coefficients. In this paper, we present a novel DCT architecture that reduces the power consumption by decreasing the computational complexity based on the correlation between two successive rows. The unwanted forward DCT computations in each 8 × 8 sub-image are eliminated, thereby making a significant reduction of forward DCT computation for the whole image. This algorithm is verified with various high- and less-correlated images, and the result shows that image quality is not much affected when only the most significant 4 bits per pixel are considered for row comparison. The proposed architecture is synthesized using Cadence SoC Encounter® with TSMC 180 nm standard cell library. This architecture consumes 1.257 mW power instead of 8.027 mW when the pixels of two rows have very less difference. The experimental result shows that the proposed DCT architecture reduces the average power consumption by 50.02 % and the total processing time by 61.4 % for high-correlated images. For less-correlated images, the reduction in power consumption and the total processing time is 23.63 and 35 %, respectively.

OpenCL-based optimization methods for utilizing forward DCT and quantization of image compression on a heterogeneous platform

Recent computer systems and handheld devices are equipped with high computing capability, such as general purpose GPUs (GPGPU) and multi-core CPUs. Utilizing such resources for computation has become a general trend, making their availability an important issue for the real-time aspect. Discrete cosine transform (DCT) and quantization are two major operations in image compression standards that require complex computations. In this paper, we develop an efficient parallel implementation of the forward DCT and quantization algorithms for JPEG image compression using Open Computing Language (OpenCL). This OpenCL-based parallel implementation utilizes a multi-core CPU and a GPGPU to perform DCT and quantization computations. We demonstrate the capability of this design via two proposed working scenarios. The proposed approach also applies certain optimization techniques to improve the kernel execution time and data movements. We developed an optimal OpenCL kernel for a particular device using device-based optimization factors, such as thread granularity, work-items mapping, workload allocation, and vector-based memory access. We evaluated the performance in a heterogeneous environment, finding that the proposed parallel implementation was able to speed up the execution time of the DCT and quantization by factors of 7.97 and 8.65, respectively, obtained from 1024 × 1024 and 2084 × 2048 image sizes in 4:4:4 format.

A High-Throughput and Area-Efficient Video Transform Core With a Time Division Strategy

In this paper, a 2-D forward discrete cosine transform (FDCT) and inverse DCT (IDCT) core are presented. The proposed DCT core uses a single 1-D transform core and a transpose memory in order to achieve an area-efficient design. By exploiting the even and odd symmetrical properties of the FDCT and IDCT computations, the DCT core can share hardware resources. Furthermore, first-dimensional (1st-D) and second-dimensional (2nd-D) operations can be run simultaneously (1st-D FDCT, 2nd-D FDCT, 1st-D IDCT, 2nd-D IDCT) in the proposed 1-D core by using the proposed time division strategy, which shares hardware resources achieving a high-throughput design. Measurement results show that the DCT core achieves a throughput of 250 MP/s when simultaneously operating FDCT and IDCT, consuming only 19650 logic gates when fabricated using the TSMC 0.18-μm CMOS process. The DCT core achieves superior hardware efficiency compared to the existing cores.

Adaptive discrete cosine transform-based image compression method on a heterogeneous system platform using Open Computing Language

Discrete cosine transform (DCT) is one of the major operations in image compression standards and it requires intensive and complex computations. Recent computer systems and handheld devices are equipped with high computing capability devices such as a general-purpose graphics processing unit (GPGPU) in addition to the traditional multicores CPU. We develop an optimized parallel implementation of the forward DCT algorithm for the JPEG image compression using the recently proposed Open Computing Language (OpenCL). This OpenCL parallel implementation combines a multicore CPU and a GPGPU in a single solution to perform DCT computations in an efficient manner by applying certain optimization techniques to enhance the kernel execution time and data movements. A separate optimal OpenCL kernel code was developed (CPU-based and GPU-based kernels) based on certain appropriate device-based optimization factors, such as thread-mapping, thread granularity, vector-based memory access, and the given workload. The performance of DCT is evaluated on a heterogeneous environment and our OpenCL parallel implementation results in speeding up the execution of the DCT by the factors of 3.68 and 5.58 for different image sizes and formats in terms of workload allocations and data transfer mechanisms. The obtained speedup indicates the scalability of the DCT performance.

Low cost high throughput pipelined architecture of 2-D 8 × 8 integer transforms for H.264/AVC

In this article, we present the implementation of high throughput two-dimensional (2-D) 8 × 8 forward and inverse integer DCT transform for H.264. Using matrix decomposition and matrix operation, such as the Kronecker product and direct sum, the forward and inverse integer transform can be represented using simple addition operations. The dual clocked pipelined structure of the proposed implementation uses non-floating point adders and does not require any transpose memory. Hardware synthesis shows that the maximum operating frequency of the proposed pipelined architecture is 1.31 GHz, which achieves 21.05 Gpixels/s throughput rate with the hardware cost of 42932 gates. High throughput and low hardware makes the proposed design useful for real time H.264/AVC high definition processing.

Simulation of Vedic Multiplier in DCT Applications

This paper illustrates the simulation of Vedic multiplier in 2D DCT. The input data is first divided into NxN blocks, each block s of 8x8 size and 2-D DCT is applied on each of these 8x8 block and 2-D DCT is applied to reconstruct the image. The proposed 2-D DCT design uses Urdhva Tiryagbhyam a Vedic multiplication sutra and the Simulations with MATLAB prove that the proposed design is compared to that of conventional design. Performing DCT computations using Vedic multiplication sutras gives a significant performance even compared to a DCT using conventional. To illustrate our approach, the sample code implements part of JPEG compression routine, performs forward DCT on 8x8 blocks, quantizes coefficients, and performs inverse DCT.

A new hybrid fuzzy biometric-based image authentication model

Watermarking is one of the most known techniques for authentication, tampering detection, privacy control, etc. Concerning privacy protection of patients' medical records, efforts have been devoted to guarantee the confidentiality of data and medical images during storage and transmission via an untrustworthy channel. Our developed watermarking system, aims at fulfilling such demands through the utilization of a biometric authentication code sender physician's iris code, encrypted patient data and a fuzzy-based Region-of-Interest ROI segmentation algorithm. In this paper, a new hybrid DCT fuzzy biometric-based watermarking scheme has been introduced for privacy protection and source verification of medical and non-medical images. The proposed scheme integrates forward DCT transform with enhanced fuzzy-based ROI regions segmentation. To comply with the imperceptibility and high image quality requirements, the coefficients selection decision depends on perceptual visibility threshold estimation, based upon characteristics of the human visual system HVS. The inclusion of a just-noticeable distortion JND profile, computed for DCT coefficients, is proved to outperform the traditional DCT model, with the major contributions of a new formula for luminance adaptation adjustment and the incorporation of block classification for contrast masking. A block classification has been utilized to differentiate edge regions and thus effectively avoid over-estimation of JND in the selected regions. Moreover, several enhanced fuzzy-based clustering models have been suggested for extraction of ROI regions in medical patterns, which aim at increasing the robustness to noise and yield more homogeneous regions with less spurious blobs. The proposed hybrid fuzzy-based ROI extraction scheme integrates the effect of the local neighborhood and allow it to influence the membership value of each pixel. A new Hybrid FCM H-FCM algorithm is proposed, which integrates spatial information with a 2D adaptive noise removal SS-FCM model. Experiments have been conducted to verify the proposed model. Several attacks have been applied to the proposed scheme and the experiments revealed promising results in terms of visual quality and extracted watermark distortion.

A High Throughput Multiple Transform Architecture for H.264/AVC Fidelity Range Extensions

In this paper, a high throughput multiple transform architecture for H.264 Fidelity Range Extensions (FRExt) is proposed. New techniques are adopted which (1) regularize the 8×8 integer forward and inverse DCT transform matrices, (2) divide them into four 4 × 4 sub-matrices so that simple fast butterfly algorithm can be used, (3) because of the similarity of the sub-matrices, mixed butterflies are proposed that all the sub-matrices of 8 × 8 and matrices of 4×4 forward DCT (FDCT), inverse DCT (IDCT) and Hadamard transform can be merged together. Based on these techniques, a hardware architecture is realized which can achieve throughput of 1.488Gpixel/s when processing either 4×4 or 8×8 transform. With such high throughput, the design can satisfy the critical requirement of the real-time multi-transform processing of High Definition (HD) applications such as High Definition DVD (HD-DVD) (1920x1080@60Hz) in H.264/AVC FRExt. This work has been synthesized using Rohm 0.18um library. The design can work on a frequency of 93MHz and throughput of 1.488Gpixel/s with a cost of 56440 gates.

Arbitrary-ratio image resizing using fast DCT of composite length for DCT-based transcoder

We propose a fast arbitrary-ratio image resizing method for transcoding of the compressed images. The downsizing process in the discrete cosine transform (DCT) domain can be implemented by truncating high-frequency coefficients, whereas the upsizing process is implemented in the DCT domain by padding zero coefficients to the high-frequency part. The proposed method combines a fast inverse and forward DCT of composite length for arbitrary-ratio upsizing or downsizing. According to the resizing ratio, truncating the high-frequency coefficients and padding zeros are appropriately considered by combining the inverse DCT and forward DCT. The proposed method shows a good peak signal-to-noise ratio and less computational complexity compared with the spatial-domain and previous DCT-domain image resizing methods.

Scalable Variable Complexity Approximate Forward DCT

The discrete cosine transform (DCT) is one of the major components in most of image and video compression systems. The variable complexity algorithm framework has been applied successfully to achieve complexity savings in the computation of the inverse DCT in decoders. These gains can be achieved due to the highly predictable sparseness of the quantized DCT coefficients in natural image/video data. With the increasing demand for instant video messaging and two-way video transmission over mobile communication systems running on general-purpose embedded processors, the encoding complexity needs to be optimized. In this paper, we focus on complexity reduction techniques for the forward DCT, which is one of the more computationally intensive tasks in the encoder. Unlike the inverse DCT, the forward DCT does not operate on sparse input data, but rather generates sparse output data. Thus, complexity reduction must be obtained using different methods from those used for the inverse DCT. In the literature, two major approaches have been applied to speed up the forward DCT computation, namely, frequency selection, in which only a subset of DCT coefficients is computed, and accuracy selection, in which all the DCT coefficients are computed with reduced accuracy. These two approaches can achieve significant computation savings with minor output quality degradation, as long as the coding parameters are such that the quantization error is larger than the error due to the approximate DCT computation. Thus, in order to be useful, these algorithms have to be combined using an efficient mechanism that can select the "right" level of approximation as a function of the characteristics of the input and the target rate, a selection that is often based on heuristic criteria. In this paper, we consider two previously proposed fast, variable complexity, forward DCT algorithms, one based on frequency selection, the other based on accuracy selection. We provide an explicit analysis of the additional distortion that each scheme introduces as a function of the quantization parameter and the variance of the input block. This analysis then allows us to improve the performance of these algorithms by making it possible to select the best approximation level for each block and a target quantization parameter. We also propose a hybrid algorithm that combines both forms of complexity reduction in order to achieve overall better performance over a broader range of operating rates. We show how our techniques lead to scalable implementations where complexity can be reduced if needed, at the cost of small reductions in video quality. Our hybrid algorithm can speed up the DCT and quantization process by close to a factor of 4 as compared to fixed-complexity forward DCT implementations, with only a slight quality degradation in PSNR.

An effective method for still image compression/decompression for transmission on PSTN lines based on modifications of Huffman coding

This paper presents an effective compression method suitable for transmission the still images on public switching telephone networks (PSTN). Since compression algorithm reduce the number of pixels or the gray levels of a source picture, therefore this will lead to the reduction of the amount of memory needed to store the source information or the time necessary for transmitting by a channel with a limited bandwidth. First, we introduced some current standards and finally the lossy DCT-based JPEG compression method is chosen. According to our studies, this method is one of the suitable methods. However, it is not directly applicable for image transmission on usual telephone lines (PSTN). Therefore, it must be modified considerably to be suitable for our purposes. From Shannon’s Information Theory, we know that for a given information source like an image there is a coding technique which permits a source to be coded with an average code length as close as to the entropy of the source as desired. So, we have modified the Huffman coding technique and obtained a new optimized version of this coding, which has a high speed and is easily implemented. Then, we have applied the DCT 1 Discrete Cosine Transform. 1 and the FDCT 2 Forward DCT. 2 for compression of the data. We have analyzed and written the programs in C++ for image compression/decompression, which give a very high compression ratio (50:1 or more) with an excellent SNR. 3 Signal to Noise Ratio. 3 In this paper, we present the necessary modifications on Huffman coding algorithms and the results of simulations on typical images.

An Efficient IDCT Processor Design for HDTV Applications

This paper proposes a high performance and low cost inverse discrete cosine transform (IDCT) processor for high definition Television (HDTV) applications by using cyclic convolution and hardwired multipliers. By properly arranging the input sequence, we formulate the one-dimensional (1-D) IDCT into cyclic convolution that is regular and suitable for VLSI implementation. The hardwired multiplier that implements multiplication with IDCT coefficients are first scaled and optimized by using the common sub-expression techniques. Based on these techniques, the data-path in the proposed two-dimensional (2-D) IDCT design costs 7504 gates plus 1024 bits of memory with 100 M pixels/sec throughput according to the cost estimation based on the cell library of COMPASS 0.6 μm SPDM CMOS technology. Also, we have verified that the precision analysis of the proposed 2-D 8 × 8 IDCT meets the demands of IEEE Std. 1180-1990. Due to the good performance in the computing speed as well as the hardware cost, the proposed design is compact and suitable for HDTV applications. This design methodology can be applied to forward DCT as well as other transforms like discrete sine transform (DST), discrete Fourier transform (DFT), and discrete Hartley transform (DHT).

On computing the 2-D discrete cosine transform using rotations

A two-stage algorithm for the computation of DCT and IDCT using rotations is introduced. Architectures implementing this algorithm using distributed arithmetic and redundant signed digit representations, are then presented. Among the advantages of these architectures we note the following: 1. The forward and inverse DCT can be easily combined into a unified processor. 2. The architectures can be built using registers, adders and ROMs only, yielding regular structures, suitable for VLSI implementation. 3. The ROM requirements are less than 10% of those of the typical distributed arithmetic DCT/IDCT implementations, and, 4. A performance of 100 Mpixels/sec, sufficient even for the processing of HDTV signals can be achieved if these architectures are implemented in 0.8μ CMOS technology.