Forward Body Bias Technique Research Articles

Design of Concurrent Dual Band Low Noise Amplifier for WLAN Applications

This paper presents a dual band LNA CMOS designed for a Wireless Local Area Network (WLAN) application using CMOS 0.13-µm Silterra technology. The proposed design incorporates forward body bias technique with cascode and notch filter configuration to achieve both low power consumption and high gain. The simulation results demonstrate a total power consumption of 2.39 mW at a low supply voltage of 0.5 V, with a gain of 16 dB at 2.4 GHz and 12 dB at 5.2 GHz. Additionally, input return loss of -12.3 dB and -14.2 dB with noise figures of 2.93 dBm and 4.23 dBm were obtained at 2.4 GHz and 5.2 GHz, respectively. Overall, this research contributes to the development of dual band LNA designs for WLAN applications.

A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC

A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).

PVT-compensated low voltage LNA based on variable current source for low power applications

In this paper, a new compensation technique for the low noise amplifier (LNA) with the high capability and efficiency for low power applications is proposed. The supply voltage and bias of the LNA are near the sub-threshold voltage, which has excellent effect on reducing power consumption. At this voltage level, the gain decreases and the various circuit parameters become extremely sensitive to process, voltage and temperature (PVT) changes. To overcome the problem, a compensating circuit with variable current source to control the LNA bias voltage is used. The output of the compensator circuit is adjusted according to changes in temperature, voltage and five process corners, and produces a variable voltage. The temperature compensator consists of two current sources that produce a current proportional to temperature changes. Regarding process and voltage compensator, according to the state created in the circuit, the appropriate amount of current is injected through the output and finally stabilizes the main parameters of the LNA circuit. In LNA circuit, for proper performance at supply voltage near the sub-threshold and attaining the gain improvement, forward body bias and gm-boosting techniques are employed, respectively. The LNA circuit along with the PVT compensator at supply voltage of 0.35 V, consumes about 567 µW power consumption that here 91 µW is caused by the PVT compensator circuit. In the proposed circuit, the rate of noise figure (NF) and gain (S21) changes compared to temperature changes in the five corners have decreased by 4.3 and 12.1 times versus LNA with constant bias, respectively. In this case, with 20% changes of VDD, NF and S21 changes decreased by 23 and 11.35 times, respectively. The results are provided by Cadence software using 65 nm CMOS technology.

PVT ‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with gm boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.

Bias-stabilized inverter-amplifier: an inspiring solution for low-voltage and low-power applications

A bias stabilization scheme for inverter is introduced. The conventional inverter structure has lent itself as a power-efficient amplifier block for low-power, low-voltage applications. However, its application is restricted due to the limits in its biasing method. This letter introduces an efficient biasing scheme based on forward body bias technique. The proposed biasing scheme relaxes most of the problems associated with the unreliable conventional biasing method. Spectre simulation utilizing TSMC 180 nm technology are utilized to compare the performance of the proposed circuit with that’s of conventional inverter and also with well-known common-source amplifier. All three versions are biased with 0.4 V power supply and 3 µA bias current. In addition to the performance examination, full process, voltage, and temperature analysis is also conducted through Monte Carlo and corner simulations. The results validate the well-performance of the proposed structure under various operating conditions.

A 26.1–38.2 GHz injection-locked frequency divider with current phasor synthesis technique

This paper proposes a 26.1–38.2 GHz millimeter-wave (mm-wave) injection-locked frequency dividers (ILFDs) with current phasor synthesis (CPS) technique. The principle of the conventional ILFDs is analyzed to prove that the limited LR is mainly attributed to the maximum phase shift between the total current injected into LC tank and the current injected by cross-coupled pairs. The CPS technique produces a greater phase shift for total current to enhance the LR. Besides, the forward body bias (FBB) technique is employed to lower supply voltage and thus the power consumption. With the proposed CPS technique, a single inductor CPS-ILFD is implemented in 55 nm CMOS process. The proposed CPS-ILFD achieves an LR of 37.6% from 26.1 to 38.2 GHz at 0 dBm injection power. The divider core dissipates 5.6 mW power consumption from 0.8 V supply voltage with an area of 210 × 130 μm2.

Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor networks using 0.13-m technology

This paper describes the design topology of a ultra-low power low noise amplifier (LNA) for wireless sensor network (WSN) application. The proposed design of ultra-low power 2.4 GHz CMOS LNA is implemented using 0.13-μm Silterra technology. The LNA benefits of low power from forward body bias technique for first and second stages. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The simulation results show that the total power consumed is only 0.45 mW at low supply voltage of 0.55 V. The power consumption is decreased about 36% as compared with the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input third order intercept point (IIP3) of -2 dBm are achieved. The input return loss (S11) and the output return loss (S22) is -17.6 dB and -12.3 dB, respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1.

Ultra-Low Power 0.55 mW 2.4 GHz CMOS Low-Noise Amplifier for Wireless Sensor Network

This paper describes the design topology of two-stage ultra-low power low noise amplifier (LNA) using the forward body bias technique for wireless sensor network (WSN) application. The proposed design employs CMOS 0.13-µm technology at 2.4 GHz frequency. The LNA consumes low power from the forward body bias technique at the first and the second stages. The threshold voltage of the transistor can be lowered using the forward body bias technique. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The measurement results show that the LNA consumes a total power of 0.55 mW at supply voltage 0.55 V. The input return loss (S11) and the output return loss (S22) is 10 and 12 dB, respectively. A gain of 12 dB, noise figure (NF) of 5.9 dB and input third-order intercept point (IIP3) of −3 dBm are achieved.

A $${\mathbf{g}}_{{\mathbf{m}}}$$-boosted highly linear fully differential 3–5 GHz UWB LNA employing noise and distortion canceling technique

A novel structure is presented to optimize the noise and linearity performance of a $${\text{g}}_{\text{m}}$$ -boosted common gate (CG) ultra-wide-band low noise amplifier (LNA) by exploiting noise and distortion canceling technique. The $${\text{g}}_{\text{m}}$$ -booster common source amplifier provides a degree of freedom to eliminate the limitation on the noise figure (NF) improvement, at a lower transconductance for the CG transistor. The applied noise and distortion canceling technique to the $${\text{g}}_{\text{m}}$$ -boosted topology is used to minimize the dominant noise contribution and the second and third order non-linearity coefficients of the first stage components. The proposed LNA is configured in a differential topology to compensate the $$IIP_{2}$$ of the structure. The Forward body bias technique is utilized for operating the LNA at a lower supply voltage and power consumption. The post-layout simulation results of the LNA, including bonding and electrostatic discharge circuits, with 90 nm TSMC RF CMOS technology show a power gain of 14.5 ± 05 dB, flat NF of 2.2 ± 0.1 dB, and $$S_{11}$$ less than − 9.5 dB for 3–5 GHz frequency at a power consumption of 13.8 mW from 0.7 V supply voltage. The $$IIP_{3}$$ and $$IIP_{2}$$ measures are obtained as + 5.2 dBm and 55 dBm, respectively.

A Forward-Body-Bias CMOS LNA With Ultra-Low Device Junction Leakage Using Intrinsic Self-Balanced Pseudo Resistor

A fully differential LNA with forward-body-bias (FBB) technique using an intrinsic self-balanced MOSFET is presented in this brief for low-impact device junction leakage and process, voltage, and temperature (PVT) variations. A proposed natural back-to-back connected diode directly from the source-bulk and bulk-drain junctions of a MOSFET performs as a stable and balanced pseudo resistor for minimizing leakage current at the transconductance stage of a FBB LNA. In addition, the FBB voltage is injected into the bulk of the MOSFET to allow a full-swing operation, in particular simultaneously at a gate-driven and body-driven input stage. In comparison to the conventional topologies of pseudo resistor, the simulated and measured results show that the proposed FBB technique applied at the LNA with the dual cross coupling configuration can indeed extend the overall dynamic range of the pseudo resistor and relief PVT variations under the same extreme condition, with a larger forward bias voltage close to the breakdown leakage current transition corner of the P-N junction.

A Low Power 2.4 GHz CMOS Mixer Using Forward Body Bias Technique for Wireless Sensor Network

Wireless sensor network (WSN) is a highly-demanded application since the evolution of wireless generation which is often used in recent communication technology. A radio frequency (RF) transceiver in WSN should have a low power consumption to support long operating times of mobile devices. A down-conversion mixer is responsible for frequency translation in a receiver. By operating a down-conversion mixer at a low supply voltage, the power consumed by WSN receiver can be greatly reduced. This paper presents a development of low power CMOS mixer using forward body bias technique for wireless sensor network. The proposed mixer is implemented using CMOS 0.13 μm Silterra technology. The forward body bias technique is adopted to obtain low power consumption. The simulation results indicate that a low power consumption of 0.91 mW is achieved at 1.6 V supply voltage. Moreover, the conversion gain (CG) of 21.83 dB, the noise figure (NF) of 16.51 dB and the input-referred third-order intercept point (IIP3) of 8.0 dB at 2.4 GHz are obtained. The proposed mixer is suitable for wireless sensor network.

Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes

Spin-transfer torque magnetic RAM (STT-MRAM), which uses a magnetic tunnel junction to store binary data, is a promising memory technology. With many benefits, such as low leakage power, high density, high endurance, and nonvolatility, it has been explored as an SRAM replacement for cache design or a DRAM replacement for main memory. Meanwhile, along with the continuous shrinking of CMOS process technology, the bias temperature instability (BTI) effect has become a major reliability issue. Prior work has investigated the influence of the BTI effect on the SRAM sense amplifier, but no investigation has been done for the STT-MRAM sense amplifier. Therefore, this paper investigates the BTI effect on STT-MRAM sense amplifiers. We propose a majority-based technique and an alternative sensing technique to reduce circuit degradation. To further improve sensing delay, we propose using forward body bias (FBB) on an access transistor with a positive voltage. Extensive simulation results are done to show the effectiveness of the proposed techniques. The sensing delay for reading zeros and ones can be reduced by 10.61% and 4.35%, respectively, on average, with the majority-based technique. The sensing delay for reading zeros and ones can be reduced by 4.42% and 1.83%, respectively, on average, using the alternative sensing technique. The sensing delay for reading zeros and ones can be reduced by 15.37% and 6.25%, respectively, on average, by using both techniques simultaneously. When using the majority-based and alternative sensing techniques with the FBB technique, the sensing delay for reading zeros and ones can be improved by 29.93% and 57.67%, respectively, on average. We also analyze the BTI-induced degradation of a high-performance sense amplifier and a low power sense amplifier with the proposed techniques. The simulation results show that our proposed technique and simulation flow can be easily extended to other sense amplifiers.

A Fully-integrated Highly Efficient CMOS Class-E Power Amplifier Using Cascode Class-E Drivers for WLAN Applications

This paper presents a modified class-E single-ended power amplifier (PA) for WLAN application. The proposed class-E PA consisting of two stages, all driver stages adopts bias voltage technique to simplify the structure and improves RF performance. The driver stage adopts the forward body bias technique to lower threshold voltage and realize high efficiency with low operation voltage; the power stage utilizes cascode topology with a self-biasing voltage technique to reduce device stress. The proposed PA is simulated by cadence IC in TSMC 0.18-μm CMOS technology. With a 2.3 V supply voltage, the fully integrated CMOS PA achieves maximum output power of 27.8 dBm and power-added efficiency (PAE) of 48.3% at 2.4GHz. It achieves high power gain of 31.5 dB and large output power with low input signal. The chip area of the proposed class-E PA is 0.90 mm2.

A 0.35-V 520- $\mu \text{W}$ 2.4-GHz Current-Bleeding Mixer With Inductive-Gate and Forward-Body Bias, Achieving >13-dB Conversion Gain and >55-dB Port-to-Port Isolation

An ultralow voltage micropower 2.4-GHz current-bleeding active mixer for energy-harvesting Bluetooth low energy/ZigBee applications is reported. It features a double-balanced mixer topology combining nMOS current-bleeding transistors with a pMOS local oscillator switching quad, and forward-body bias and inductive-gate bias techniques to secure an adequate performance at a supply voltage down to 0.35 V. Fabricated in 0.13- $\mu \text{m}$ CMOS, the prototype exhibits a conversion gain of 13.77 dB, a third-order intercept point of −3.5 dBm, and a noise figure of 18 dB. The power consumption is $520~\mu \text{W}$ , and port-to-port isolation is >55 dB. The achieved figure of merit compares favorably with the state of the art.

A 0.6‐V sub‐mW X‐band RFSOI CMOS LNA with novel complementary current‐reused technique

SummaryA fully integrated 0.6 V low‐noise amplifier (LNA) for X‐band receiver application based on 0.18 μm RFSOI CMOS technology is presented in this paper. To achieve low noise and high gain with the constraint of low voltage and low power consumption, a novel modified complementary current‐reused LNA using forward body bias technique is proposed. A diode connected MOSFET forward bias technique is employed to minimize the body leakage and improve the noise performance. A notch filter isolator is constructed to improve the linearity of low voltage. The measured results show that the proposed LNA achieves a power gain of 11.2 dB and a noise figure of 3.8 dB, while consuming a DC current of only 1.6 mA at supply voltage of 0.6 V. Copyright © 2017 John Wiley & Sons, Ltd.

A Low Power High Gain CMOS LNA with Multiple-Feedback Network for Low Voltage UWB Receiver

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18[Formula: see text][Formula: see text]m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1[Formula: see text]GHz UWB LNA accomplishes a maximum gain of 14.26[Formula: see text]dB with only 2.33[Formula: see text]mW power consumption at 0.8[Formula: see text]V supply voltage, while Noise Figure (NF) is 1.49–3.41[Formula: see text]dB and the chip area is 0.46[Formula: see text]mm2 including test pads (core area is 0.23[Formula: see text]mm2).

A 0.3 mW 2.4 GHZ LOW POWER LOW NOISE AMPLIFIER USING FORWARD BODY BIAS TECHNIQUE FOR WIRELESS SENSOR ARD BODY BIAS TECHNIQUE FOR WIRELESS SENSOR NETWORK

This paper presents a 0.3 mW 2.4 GHz low-power low-noise amplifier (LNA) using a forward-body bias technique for a wireless sensor network. The proposed LNA is implemented using CMOS 0.13-µm Silterra technology. The forward-body bias technique with a cascode configuration has been adopted in order to obtain low power consumption. A low supply voltage of 0.5 V is used to optimize the trade-offs between the LNA performances. The post-layout simulation results indicate that a power consumption of 0.3 mW is achieved. The simulated input return loss (S11) is less than -17.71 dB while the output return loss (S22) is below -14.83 dB. Moreover, the gain (S21) of 9.86 dB, the noise figure (NF) of 5.11 dB and the input-referred third-order intercept point (IIP3) of -7.5 dBm at 2.4 GHz is obtained with the calculated figure of merit (FOM) of 4.64 (1/mW).

Design and Optimization of Ultra Low Power Low Noise Amplifier using Particle Swarm Optimization

In this paper, an Inductively Degenerated Cascode Low Noise Amplifier (IDCLNA) is designed using TSMC 0.13 μm RF CMOS technology. For improving the performances of LNA, modifications are done in conventional IDCLNA. They are 1. Forward Body Bias (FBB) technique is applied to reduce the supply voltage. 2. The inductor is added between main and cascode transistors for increasing the gain. 3. To reduce the noise factor of cascode stage, an inductor is inserted at the gate of cascode stage. 4. For improving the stability factor, the modified resistive and capacitive shunt feedback is used. The proposed LNA produces 10.7 dB voltage gain, 3.27 dB noise figure, -9.1 dBm IIP3 and 957 μW power consumption. For optimizing the design parameters of proposed LNA, the popular optimization technique like Particle Swarm Optimization (PSO) algorithm is used to improve the performance measures. The optimized LNA achieves 12.6 dB voltage gain, 3.19 dB noise figure and consumes 869 μW power. The optimized results produce the good Figure of Merit (FOM) of 6.6. Keywords: Figure of Merit, LNA, Power Consumption and PSO

A 3.0–10.0 GHz UWB Low-Noise Amplifier with Forward Body bias Technique

ABSTRACTAn ultra-wideband (UWB) low-noise amplifier (LNA) based on cascaded common source stage with shunt–shunt resistive feedback architecture is proposed. The wideband input impedance matching is accomplished by shunt–shunt resistive branch with inductor degeneration and parallel resistor-inductor-capacitor (RLC) load, forming two parallel RLC branches having inherently two wideband band-pass filter characteristics, resonating both at lower frequency and higher frequency. The output matching is achieved via a shunt inductor and a series resistor without the use of a buffer. Additionally, both series and shunt-inductive peaking techniques are employed in the proposed UWB LNA circuit design for bandwidth extension. To reduce the supply voltage headroom consumption, the forward body bias technique is also employed in the proposed topology. The resistor-capacitor (RC)-extracted results obtained in this paper are competitive in comparison with recent reported work in appreciating good noise figure (NF) performance as well as low-voltage headroom consumption. In the post-layout simulation results, the proposed complementary-metal-oxide-semiconductor (CMOS) UWB LNA dissipates only 13 mW while achieving the S11 below −11.4 dB, S22 below −11.7 dB, a flat S21 of 11.5 ± 0.6 dB, a maximum NF of 3.48 dB, within the range of 3.04 – 3.48 dB over the 3.0–10.0 GHz band of interest. Moreover, the IIP3 is within the range of −6.3 to −7.8 dBm, P1 dB of −14.7 to −16.8 as well as the K-factor of above 1 throughout the entire bandwidth operation, attesting the fact that the resistive feedback circuit is stable. The chip area consumption is approximated to 0.997 × 0.933 mm2.

Design and analysis of a 3.1–10.6 GHz UWB low noise amplifier with forward body bias technique

A low power and high gain 3.1–10.6GHz UWB low noise amplifier (LNA) is presented in this paper. The first stage of the UWB LNA employs a resistive shunt feedback topology in conjunction with a parallel LC load to achieve wideband input matching and low noise figure simultaneously. By incorporating the modified current reused cascade configuration and forward body bias technique in the second stage, the proposed UWB LNA can operate at reduced supply voltage and power consumption while maintaining high gain and high reverse isolation. Post-layout simulation results show that the UWB LNA has an average power gain S21 of 14.4dB with gain ripple of ±1.4dB, a high reverse isolation S12 of −83 to −51dB, an input return loss S11 and output return loss S22 of respectively −10.6 to −19.2dB and −12.1 to −16.4dB. An excellent noise figure of 2.2–3.2dB is obtained in the required band with a power dissipation of 9.0mW under a supply voltage of 1.5V. The input 1dB compression point and input third-order intercept point are −15.5dBm and −6.0dBm, respectively, at 6GHz. The chip area including testing pads is only 0.65mm×0.82mm.