Flash Converter Research Articles

Heat and mass transfer characteristics of non-equilibrium flash at start stage

Our experiments showed that a V shape pressure drop appeared at start stage of non-equilibrium flash. V shape pressure drop firstly denoted the generating of superheat degree, which should be the starting force driving the non-equilibrium flash. Then evaporated vapor made up the pressure drop. Finally, a dynamic equilibrium was reached between the flash rate and the outflow rate, and the pressure behaved decreasing gradually. However, few published references focus on this start stage of the non-equilibrium flash. In this paper, experiments of the flash were conducted to investigate the heat and mass characteristics during V shape start stage. Dimensionless flash conversion coefficient (FCC) was proposed to normalize the flash with different initial liquid mass at start stage. The effects of initial temperature and the valve opening degree on the heat and mass characteristics of flash during the V drop start stage were studied. The results showed that the pressure of the working fluid changed dramatically during the V drop start stage. The peak of instant liquid superheat was proportional to the opening degree of the valve, which controlled the outflow rate. The flash rate increased with increasing initial temperature and valve opening degree, which had an approximately linear relationship with the flash time. FCC increased with valve opening degree. It could be deduced that flash intensity or flash rate would be higher for an expander with larger outlet area or higher working temperature.

Implementation of Background Calibration for Redundant FLASH ADC

Flash converters are suitable analog-to-digital converter architectures for high-speed applications. However, the benefits in terms of the frequency of smaller technology nodes are hampered by variability, which necessitates the use of large transistors. Comparator redundancy was introduced to overcome this trade-off; the best comparators were selected upfront (either at start-up or in the factory), and the unused comparators could be switched off. This work studies the possibility of performing comparator selection in the background concurrently with normal conversion to increase the converter lifetime. Thus, the system can automatically recover its performance from drifts or failures due to aging, temperature, etc. This paper proposes an embedded solution that includes a calibration stimulus generator (which only requires some external passive elements) and develops system design requirements. In addition, mathematical equations and error sensitivities of the system elements were derived. A 6b flash converter is implemented in UMC180nm technology, and transistor-level simulations of the system are provided to demonstrate the feasibility of the proposed system.

Black-Box Optimization of Superconducting Circuits Using Reduced-Complexity Neural Networks

Single-flux quantum (SFQ) logic based high-speedperiodic-threshold flash converter circuits require multiple non-linear and correlated parameters tuned precisely to function optimally. These parameters cannot be pre-determined from simulations and change with the clock frequency, thus requiring manual optimization every time the clock frequency is changed. In this work, we demonstrate automated bias optimization of an 8-bit superconducting SFQ flash ADC for the first time. A closed-loop 4X lower computational complexity hybrid particle-swarm-gradient-descent-optimization is demonstrated that first uses particle swarm optimization (PSO) to coarse tune the ADC biases and then applies gradient descent (GD) optimization for fine tuning. This results in a 12X reduction in the blind calibration time from several days manually, to a few hours using the proposed optimization scheme, with a resultant performance 2 dB better than an optimization done by a highly skilled human.

12 bit 3.072 GS/s 32‐way time‐interleaved pipelined ADC with digital background calibration for wideband fully digital receiver application in 65 nm complementary metal–oxide–semiconductor

The performance of a wideband receiver is highly dependent on the performance of the analogue-to-digital converter (ADC) used. Such applications require ADCs to operate at ultra-high speeds with high accuracy for inputs ranging from 40 MHz - 1 GHz. Conventional solutions either use filters and mixers to extract the frequency of interest and convert it using a low-speed ADC or use a single ultra-high-speed flash converter. Both of these solutions consume ultra-high power and require complex circuitry, which expands exponentially with the converter resolution. In this work, a 12 bit 3.072 GS/s time-interleaved pipeline ADC is proposed. In total, 32 pipeline ADCs, each with a sampling rate of 96 MS/s, are interleaved in the time domain to achieve an overall sampling rate of 3.072 GS/s. In addition to the potential energy-saving capabilities of a time-interleaving structure, the circuit adopts amplifier sharing in sample-and-hold circuits, further improving the power efficiency. To account for interleaving mismatch, the circuit uses a pure background calibration technique, maintaining the system linearity and spectral efficiency. The proposed design achieves signal-to-noise-and-distortion ratio of 53.65 dB and spurious-free dynamic range (SFDR) of 69.04 dB while consuming 820 mW of power at a 1.2 V supply, resulting in a figure-of-merit of 0.67 pJ/conv-step.

A 7-GS/s 5-Bit Continuous-Time Pipelined Binary-Search Flash ADC in 28-nm CMOS

A novel ADC architecture is introduced with a sampling rate comparable to flash converters, but with reduced power consumption. Broadband active delay circuits pass the input along with a clock through a continuous-time pipeline. Efficient internal buffers eliminate the need for an external driver by providing 15 fF of kickback-free input capacitance. The 5-bit prototype has a 2.5-bit first stage, 1.5-bit second stage, and 2-bit final stage allowing for digital correction of interstage errors. It consumes 47 mW at 7 GS/s in 28-nm CMOS.

Re-creating the sigsaly quantizer: This 1943 analog-to-digital converter gave the allies an unbreakable scrambler - [Resources

In the years before World War II, German Intelligence Could Decode Band-Scrambled U.S. radiotelephone conferences. After Pearl Harbor, an unbreakable speech scrambler was developed with top priority, and by 1943, it was deployed. Known as SIGSALY, the device pioneered many advances critical to modern digital media technologies, including spread-spectrum communications and the first use of pulse-code modulation (PCM) to transmit speech. • SIGSALY was top secret, so even today information about the details of its construction are hard to come by. I've spent 20 years researching the history of digital technology and digital media, especially SIGSALY. I searched IEEE and U.S. National Security Agency (NSA) journals, and Bell Telephone Laboratories patents. Finally, I found Lieut. Donald Mehl, a WWII SIGSALY technician, who gave me invaluable assistance. In 2015, I realized that it might be possible to re-create a key element of SIGSALY—the quantizer—using vintage parts. • SIGSALY was unbreakable because, unlike earlier analog systems, it scrambled voices by using a one-time random digital encryption key. Before a digital key can be applied, a speaker's voice must first be converted from analog to digital, thus the quantizer. • Modern analog-to-digital conversion makes it easy to capture the entire audio spectrum. With the technology available at the time, the creators of SIGSALY used 12 speech parameters that best encoded speech. SIGSALY used vocoders to analyze incoming speech and classify them into 10 frequency sub-bands; a pitch parameter; and a bit that indicated whether the speech sound was voiced or unvoiced. • SIGSALY had 72 identical quantizers to digitize the 12 vocoder parameters and the encryption key (stored as a vinyl recording of noise). The digitized voice and key were enciphered by modulo six addition. Each quantizer employed five VT-109/2051 thyratrons. Thyratrons are a type of electronic tube, but they differ from conventional ones in that they don't respond in a linear way: They are off until the grid voltage exceeds a trigger; then an arc forms and they latch up and conduct until the anode current falls to zero, resetting them. The five thyratrons formed a flash converter, in which an incoming signal is compared to a reference voltage at a number of tap points in the circuit. In SIGSALY, the analog input voltage is fed into a five-tap logarithmic resistor divider ladder, whose taps drive the thyratron grids. As the input voltage increases, the five thyratrons thus trigger in sequence (producing not binary but a logarithmic thermometer code). These five outputs were sampled every 20 milliseconds to form a six-level quantized output signal (it's a six-level output, not five, because zero is one level).

A CT ΔΣ modulator using 4-bit asynchronous SAR quantizer and MPDWA DEM

The current paper aims at presenting a low-power second-order input-feedforward continuous-time (CT) ΔΣ modulator for audio applications. It uses a 4-bit asynchronous successive approximation register (SAR) quantizer which is more power efficient than the usual flash converter. Furthermore, in order for the proposed modulator to reduce the noise stemming from the component mismatches of the feedback digital-to-analog converter (DAC), it applies a modified partitioned data weighted averaging (MPDWA) dynamic element matching (DEM) so as to solve the DWA DEM-in band-tone problem. Despite the implementation of MPDWA, no further delay caused in the ΔΣ feedback loop compared to the conventional DWA. The implementation of the above-mentioned DEM in the modulator and required reforms have led to a new design with better performance and favorable figure of merit (FOM) value. The designed modulator which is simulated using 0.18 µm CMOS technology, achieves 84.17 dB SNDR for 20 kHz signal bandwidth and dissipates 54 µW while its FOM is obtained about 143 fJ/conv.-step.

1-bit quantization and oversampling at the receiver: Sequence-based communication

Receivers based on 1-bit quantization and oversampling with respect to the transmit signal bandwidth enable a lower power consumption and a reduced circuit complexity compared to conventional amplitude quantization. In this work, the achievable rate for systems using such analog-to-digital conversion with different modulation schemes is studied. The achievable rate and the spectral efficiency with respect to a given power containment bandwidth are considered. The proposed sequence-based communication approach outperforms the existing methods known from the literature on noisy channels with 1-bit quantization and oversampling at the receiver. It is demonstrated that the utilization of 1-bit quantization and oversampling can be superior in terms of the spectral efficiency in comparison to conventional amplitude quantization using a flash converter with the same number of comparator operations per time interval.

Flash Converted Graphene for Ultra‐High Power Supercapacitors

Supercapacitors are known for their rapid energy charge–discharge properties, often ten to a hundred times faster than batteries. However, there is still a demand for supercapacitors with even faster charge–discharge characteristics to fulfill the requirements of emerging technologies. The power and rate capabilities of supercapacitors are highly dependent on the morphology of their electrode materials. An electrically conductive 3D porous structure possessing a high surface area for ions to access is ideal. Using a flash of light, a method to produce highly interconnected 3D graphene architectures with high surface area and good conductivity is developed. The flash converted graphene is synthesized by reducing freeze‐dried graphene oxide using an ordinary camera flash as a photothermal source. The flash converted graphene is used in coin cell supercapacitors to investigate its electrode materials properties. The electrodes are fabricated using either a precoating flash conversion or a postcoating flash conversion of graphene oxide. Both techniques produce supercapacitors possessing ultra‐high power (5–7 × 105 W kg−1). Furthermore, optimized supercapacitors retain >50% of their capacitance when operated at an ultrahigh current density up to 220 A g−1.

Refining Slag Treatment with Flotation Cell

In past years, the exploitation of mineral resource in our country was stressed on capacity and the solid waste recycle and innocent treatment was ignored. Much valuable metal is associated and coexist with waste, it is in difficult position for present technology to recycle valuable composition in that waste, which leads to valuable component loss and environment pollution. Therefore, the development and utilization of copper refining slag is in significance. In this paper, the advantages and difficulties to process refining slag by flotation method are discussed based on property analysis of copper refining slag. The refining slag is featured by high specific gravity, high concentration, and its particles distributing at both ends of small and large size. A flotation cell with special structure of barrier grid plate and multi-loop channel is developed for refining slag processing, which provides a proper way to solve the sediment problem during refining slag flotation. The application of CLF-40(effective volume,40m3) flotation cell for processing slag mixture from flash furnace and converter is expounded, the production index shows that the Cu grade is up to 27.18% at recovery of 83.93% when slurry concentrate being 70%

Microwave-assisted flash conversion of non-edible polysaccharides and post-harvest tomato plant waste to levulinic acid

A microwave-assisted protocol for the conversion of non-edible polysaccharides and tomato plant waste to levulinic acid has been developed. Full conversion has been achieved in all cases at 2 min irradiation and clean levulinic acid was obtained without any purification in high yields (63–95%).

A high-speed differential resistor ladder

This paper describes the implementation of a novel high speed differential resistor ladder. In this paper it is shown that the novel ladder yields, theoretically, up to a sixteen fold reduction of the propagation delay with respect to the conventional differential ladder. In order to ease the design process, an accurate analytical model for the ladder INL is also derived in the paper.Simulation results, for a BiCMOS 0.25μm technology, show that the novel ladder results in a fivefold increase of the maximum sampling frequency when employed to design an 8bit Flash converter. A 65% higher speed is also highlighted when the ladder is employed in a Folding and Interpolating 8bit converter. Graphical abstract [Display omitted] Highlights► High-speed Differential Resistor Ladder suited for Flash and Folding and Interpolating A/D Converters. ► Theoretical sixteen fold reduction of the propagation delay with respect to the conventional differential ladder. ► Accurate analytical model of the INL presented in the paper. ► Simulated fivefold increase of the maximum sampling frequency in an 8bit Flash converter using proposed ladder. ► Simulated 65% higher maximum sampling frequency when proposed ladder is used in a Folding and Interpolating 8bit converter.

Computational Thermodynamics Modeling of Minor Element Distributions During Copper Flash Converting

Continuous copper converting processes are replacing traditional Peirce-Smith converters because they overcome most of the difficulties associated with this old batch technology. Most notably, they offer much improved environmental control of emissions. The Kennecott-Outotec flash converting process is attractive because it decouples smelting and converting, as well as offers high levels of sulfur capture. The success of a copper smelter depends on the way it controls the many minor elements that enter with the concentrate feed, and an understanding of the factors that control minor element distributions is essential. In this work, a computational thermodynamics model of the flash converter was developed and validated against published performance data. It was then used to predict the distribution behavior of lead, arsenic, bismuth, and cadmium, and the results matched the published data closely. It is suggested that the flash converter can be considered to approximate an equilibrium reactor and that minor elements distribute between the phases in a way that depends mostly on their thermodynamic properties.

A termination scheme using intended asymmetric spatial filter response for averaging flash A/D converter

Averaging network is adopted to reduce the front-end amplifier's offset in the flash analog-to-digital converter (ADC) commonly at the cost of the boundary threshold error. Such error worsens the integral-nonlinearity and introduces distortion. An averaging termination scheme using intended asymmetric spatial filter response is proposed to overcome this problem. It matches the impulse response window width, W IR, to the active zero-crossing response window width, W ZX at the boundary of network. Analysis and simulation show that by tuning the ratio between termination resistor R T and averaging resistor R 1, the boundary error is reduced as close as to 1%. This method provides sufficient reliability since the resistance matching can be fabricated as high as 1% in modern CMOS technology. Its feasibility for the flash ADC has been validated by a 1GS/s 4-bit flash converter.

Design of Data Acquisition and Storage System Based on the FPGA

Aiming at a storage system of high-speed data acquisition, it is designed with 6 channel,16-bit AD converter chip AD7656 and a programmable logic device EP2S90F102.The K9W8G08U1M chip made in SAMSUNG is selected as storage unit, and FPGA controls the needed logic for FLASH and AD converter. At the end of data acquisition, the stored data can be transmitted to the host through the USB2.0 interface. Because of the importance of the power supply, the designs of power supply controller are given.

A Volterra Series Nonlinear Model of the Sampling Distortion in Flash ADCs Due to Substrate Noise Coupling

This brief presents a Volterra series model to evaluate the impact of substrate noise on Flash analog-to-digital converters. The proposed approach first relates substrate noise to the induced timing uncertainty of the comparator by means of an analytical linear model. The analysis then expresses the resulting sampling distortion power by also considering the comparator's nonlinearities and thus models the signal-to-noise-and-distortion ratio (SNDR) of the converter. In particular, it is shown that substrate noise causes an FM modulation of the clock, and the resulting timing error is a joint effect of AM-FM modulation of the input signal and the coupled noise. The derivation of the analytical expression is also valid for any multitone ground perturbation and is validated on a high-resolution Flash converter. The developed nonlinear model for the SNDR is found to almost double the noise amplitude range compared with the linear model, thus predicting the impact of realistically large noise signals.

A 16 bit 20 kHz bandwidth discrete-time ΣΔ modulator with VCO-based quantizer

In this paper the design of a 3rd-order 16 bit 20 kHz-bandwidth discrete-time ΣΔ modulator with voltage-controlled oscillator (VCO)-based quantizer is presented. This design is motivated by the trends towards die size and power consumption reduction together with performance robustness. In this direction, the flash converter embedded in a multi-bit ΣΔM is here replaced by a VCO and digital counter, resulting in a compact fully-digital quantizer implementation. This solution would greatly exploit the technology scaling. Moreover in the proposed feed-forward architecture all feed-forward paths are summed within the last integrator of the ΣΔ loop filter, thereby eliminating the need for an analog summation amplifier at the quantizer input The presented 3rd-order ΣΔM features 110 dB-SNR, 104 dB-SNDR (i.e. 16 bit-ENOB).

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.

A Power Efficient 12-bit and 25-MS/s Pipelined ADC for the ILC/Ecal Integrated Readout

The design of full integrated electronics readout for the future ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate the very front-end stages with an analog to digital converter. We present here a 12 bit 25 MHz analog to digital converter using a pipelined architecture. It is composed of ten 1.5 bit sub-ADCs along with a final 2 bit flash converter. A CMOS 0.35 μm process is used. The dynamic range is 2 V over a 3.3 V power supply and the total power dissipation is 37 mW. The analog part of the converter can be switched to a standby mode in only a couple of μs. This power management helps to reduce the DC power dissipation by three orders of magnitude. Therefore by switching the DC bias following the beam cycle time (1% of duty cycle), an average power consumption of only 0.2 μW is measured. The converter prototype occupies an active die area of 1.7 mm *0.6 mm.

Analyzing and modeling the performance degradation of flash A/D converters due to substrate noise coupling

This paper presents a model to evaluate the impact of substrate noise on a CMOS regenerative comparator and moreover to predict the resulting performance degradation of a flash analog-to-digital (A/D) converter. The proposed approach initially relates substrate noise to the induced timing uncertainty of the comparator by means of an analytical linear model. In particular, the analysis first focuses on analyzing and expressing the resulting non-uniform sampling distortion in regenerative comparators in the presence of a deterministic ground bounce. Two sources of distortion are identified and evaluated: the input-dependent and the substrate noise-dependent one. For each error contributor, the analysis investigates two cases of timing error, based on the frequency correlation of the interfering signal with the sampling clock. The properties (number and power of distortion tones) of the sampling error spectrum are found to be highly dependent on the spectral content of the interfering signal and the sampling clock, while the model captures accurately the induced distortion. Subsequently, the linear model is extended to estimate the degradation of flash A/D converters and is utilized to predict the performance of practical flash and time-interleaved converters in the presence of substrate noise.