Fixed-point DSPs Research Articles

Control with floating- and fixed-point DSPs of a low-cost Flexible Platform for a Photovoltaic Grid-Connected System working as an agent in a Distributed Generation Structure

In this paper, a low-cost flexible platform for photovoltaics is developed with a DSP-microcontroller arrangement for doing industrial control in an easy way, and the communication process between them is carried out with the McBSP bus. The control of the DC/DC boost converter and the d-q control approach of the 3-phase Voltage Source Inverter (VSI) have been established: the mathematical model of the plant is described and a decoupled control of the instantaneous active and reactive powers fed to the utility grid is achieved, allowing unitary power factor operation. Several measurements of the involved variables in the platform are described in order to evaluate the performance of the exerted control algorithms with the DSP-microcontroller arrangement, and the development of future complex algorithms and high computational tasks is validated.

Performance Evaluation of A Multi-Sensor System Using Fixed Point DSP For Water Leak Detection

<p>DSPs (Digital Processors Signal) are processors specifically designed for digital signals processing. The fixed-point DSPs are processors operating in integer arithmetic whose characteristics are often limited but not less powerful with respect to floating-point DSPs. In this article, it is a question of checking the performances provided by the fixed-point DSP, the TMS320C541. This one is used in a detection and remote locating system ensuring a control of water leaks on the pipes. The acoustic correlation technique used as means of detection of these leaks represents the key element of the suggested system. In fact the DSP which deals the acquisition and processing of the signals emanating from the leaks. The had aim consists in initially to confirm the choice of such a processor for such an application. A simulation study to evaluate its performances as regards of computational accuracy and computing speed is carried out. A floating-point DSP of last generation, more accurate and faster, taken as reference element, is used for this purpose.</p>

Estimation of crossover DPD using orthogonal polynomials in fixed point arithmetic

This paper deals with the fixed point implementation of crossover digital predistortion (DPD). The implementation of digital predistortion linearization technique on DSPs poses major challenges, regarding cost, power consumption, speed, precision and volume. Depending on resource availability and design restrictions, fixed-point DSPs may be considered as a suitable solution. Least squares estimation of crossover DPD for multiple-input, multiple-output (MIMO) applications using conventional polynomial models face numerical instability for fixed-point processing. Orthogonal polynomials on the other hand are robust to matrix inversion. Fixed point matrix inversion was implemented using LU decomposition and triangular matrix inversion. This paper examines crossover DPD design for MIMO applications, while using fixed-point arithmetic. It also compares the linearization of 2×2 MIMO transmitters in the presence of radio frequency crosstalk using both orthogonal and memory polynomial models. The performance of the two crossover DPDs has been evaluated using a 3GPP standard: orthogonal crossover DPD decreased the measured adjacent channel power ratio of the signal from −42dBc to −52dBc.

An Adaptive Synchronous-Reference-Frame Phase-Locked Loop for Power Quality Improvement in a Polluted Utility Grid

The proper operation of grid-connected power electronics converters needs using a synchronization technique to estimate the phase of the grid voltage. The performance of this synchronization technique is related to the quality of the consumed or delivered electric power. The synchronous-reference-frame phase-locked loop (SRF-PLL) has been widely used due to its ease of operation and robust behavior. However, the estimated phase can have a considerable amount of unwanted ripple if the grid voltage disturbances are not properly rejected. The aim of this paper is to propose an adaptive SRF-PLL which strongly rejects these disturbances even if the fundamental frequency of the grid voltage varies. This is accomplished by using several adaptive infinite-impulse-response notch filters, implemented by means of an inherently stable Schur-lattice structure. This structure is perfectly suited to be programmed in fixed-point DSPs (i.e., it has high mapping precision, low roundoff accumulation, and suppression of quantization limit cycle oscillations). The proposed adaptive SRF-PLL has been tested by means of the TI TMS320F2812 DSP. The obtained experimental results show that the proposed synchronization method highly rejects the undesired harmonics even if the fundamental harmonic frequency of a highly polluted grid voltage abruptly varies.

Design and Implementation on a Sub-band based Acoustic Echo Cancellation Approach

This paper describes the design and implementation of a sub-band based acoustic echo cancellation approach, which incorporates the normalized least mean square algorithm and the double talk detection algorithm. According to the simulation, the proposed approach works well in the modest linear noisy environment. Since the proposed approach is implemented in fix-pointed C, it can be easily ported into fixed-point DSPs to cancel acoustic echo in real systems.

프랙탈 알고리즘 기반의 실시간 영상 부호화기의 설계 및 구현

이 논문에서는 범용 DSP칩인 ADSP2181를 사용하여 프랙탈 알고리즘 기반의 영상 부호화기를 설계 제작하였다. 제작된 부호화기는 고정소수점을 지원하는 Analog Device사의 ADSP2181 두 개를 사용하여 구현되었고, 영상부호화는 3단계의 파이프라인 구조에 의해 이루어진다. 첫 번째 파이프라인단인 영상 획득부는 NTSC표준 영상 신호로부터 디지털 영상 데이터를 획득하여 프레임 메모리에 저장한다. 두 번째 단에서의 주제어부에서는 영상 데이터를 프랙탈 알고리즘을 이용하여 부호화를 수행한다. 마지막 단인 출력 제어부는 부호화된 영상 계수를 RS422 포트를 통하여 출력하도록 한다. 설계 제작된 프랙탈 영상 부호화기의 성능은 QCIF 영상 포맷에서 정지영상에 대하여 초당 10프레임 이상의 부호화 속도를 얻었다. 프랙탈 알고리즘을 이용하여 프레임간 중복성을 이용한 영상 부호화시에는 초당 평균 30 프레임 이상의 부호화속도를 얻을 수 있었다. In this paper, we construct real-time moving picture encoder based on fractal theory by using general purpose digital signal processors. The constructed encoder is implemented using two fixed-point general DSPs (ADSP2181) and performs image encoding by three stage pipeline structure. In the first pipeline stage, the image grabber acquires image data from NTSC standard image signals and stores digital image into frame memory. In the second stage, the main controller encode image dada using fractal algorithm. The last stage, output controller perform Huffman coding and result the coded data via RS422 port. The performance tests of the constructed encoder shows over 10 frames/sec encoding speed for QCIF data when all the frames are encoded. When we encode the images using the interframe and redundency based on the proposed algorithms, encoding speed increased over 30 frames/sec in average.

Graph-based code selection techniques for embedded processors

Code selection is an important task in code generation for programmable processors, where the goal is to find an efficient mapping of machine-independent intermediate code to processor-specific machine instructions. Traditional approaches to code selection are based on tree parsing which enables fast and optimal code selection for intermediate code given as a set of data-flow trees. While this approach is generally useful in compilers for general-purpose processors, it may lead to poor code quality in the case of embedded processors. The reason is that the special architectural features of embedded processors require performing code selection on data-flow graphs, which are a more general representation of intermediate code. In this paper, we present data-flow graph-based code selection techniques for two architectural families of embedded processors: media processors with support for SIMD instructions and fixed-point DSPs with irregular data paths. Both techniques exploit the fact that, in the area of embedded systems, high code quality is a much more important goal than high compilation speed. We demonstrate that certain architectural features can only be utilized by graph-based code selection, while in other cases this approach leads to a significant increase in code quality as compared to tree-based code selection.

High-performance DSPs

The processing delay is a serious constraint for speech communication. A one-way end-to-end delay of more than 150 ms can severely degrade the quality of real-time conversations. The components of the total system delay includes the speech frame size, the look ahead, other algorithmic delays, multiplexing delay, processing delay for computation, and transmission delay. At the transcoder rate adaptor unit (TRAU), the only delay that can be manipulated is the processing delay. The TRAUs are generally positioned remote to the base transceiver station (BTS). The channel codec units (CCUs) are located in the BTS. In general, 16 kbit/s traffic channels can be used for full rate speech between the TRAU and BTS. By putting the TRAU remote to the BTS, DSPs for speech coding can be utilized more efficiently to cut system cost. High performance DSPs, such as the Lucent DSP16000, can be used to further cut the cost per speech channel. This article presents an implementation of GSM enhanced full rate (EFR) codec on the Lucent Technologies' DSP16000. The original European Telecommunications Standards Institute (ETSI) C code has been restructured to address the issues of MIPS (million instructions per second), RAM usage, and processing delay. We give a performance overview of vocoder implementations on some existing fixed-point DSPs and discuss the architecture of the DSP16000. Details on how the ETSI C code is restructured are presented. The DSP16210 implementation results are then discussed.

DSP based OFDM demodulator and equalizer for professional DVB-T receivers

This work treats the design of base-band processing subsystems for professional DVB-T receivers using 1600 MIPS, fixed point DSPs. We show the results about the implementation of OFDM demodulation, channel estimation and equalization functional blocks, for the 2k/8k modes. The adoption of general purpose DSPs provides a great flexibility in the development of different configurations of the receiver. Furthermore it enables the feasibility of adaptive equalization schemes, where the quality of the channel estimation varies according to both channel characteristics and speed of the channel variations. The 16/32 bit fixed point architecture leads to a very low implementation loss, and a careful optimization of the pipeline architecture of the processor allows the receiver to obtain short processing delays. The flexibility of the software approach along with the obtained performance make the proposed implementation very interesting in professional and high-end receivers for interactive, multimedia applications of DVB-T.

Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths

Many software compilers for embedded processors produce machine code of insufficient quality. Since for most applications software must meet tight code speed and size constraints, embedded software is still largely developed in assembly language. In order to eliminate this bottleneck and to enable the use of high-level language compilers also for embedded software, new code generation and optimization techniques are required. This paper describes a novel code generation technique for embedded processors with irregular data path architectures, such as typically found in fixed-point DSPs. The proposed code generation technique maps data flow graph representation of a program into highly efficient machine code for a target processor modeled by instruction set behavior. High code quality is ensured by tight coupling of different code generation phases. In contrast to earlier works, mainly based on heuristics, our approach is constraint-based. An initial set of constraints on code generation are prescribed by the given processor model. Further constraints arise during code generation based on decisions concerning code selection, register allocation, and scheduling. Whenever possible, decisions are postponed until sufficient information about a good decision has been collected. The constraints are active in the "background" and guarantee local satisfiability at any point of time during code generation. This mechanism permits to simultaneously cope with special-purpose registers and instruction level parallelism. We describe the detailed integration of code generation phases. The implementation is based on the constraint logic programming (CLP) language ECLiPSe. For a standard DSP, we show that the quality of generated code comes close to hand-written assembly code. Since the input processor model can be edited by the user, also retargetability of the code generation technique is achieved within a certain processor class.

A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library

We address the problem of code generation for embedded DSP systems. Such systems devote a limited quantity of silicon to program memory, so the embedded software must be sufficiently dense. Additionally, this software must be written so as to meet various high-performance constraints. Unfortunately, current compiler technology is unable to generate dense, high-performance code for DSPs, due to the fact that it does not provide adequate support for the specialized architectural features of DSPs via machine-dependent code optimizations. Thus, designers often program the embedded software in assembly, a very time-consuming task. In order to increase productivity, compilers must be developed that are capable of generating high-quality code for DSPs. The compilation process must also be made retargetable, so that a variety of DSPs may be efficiently evaluated for potential use in an embedded system. We present a retargetable compilation methodology that enables high-quality code to be generated for a wide range of DSPs. Previous work in retargetable DSP compilation has focused on complete automation, and this desire for automation has limited the number of machine-dependent optimizations that can be supported. In our efforts, we have given code quality higher priority over completed automation. We demonstrate how by using a library of machine-dependent optimization routines accessible via a programming interface, it is possible to support a wide range of machine-dependent optimizations, albeit at some cost to automation. Experimental results demonstrate the effectiveness of our methodology, which has been uses to build good-quality compilers for three fixed-point DSPs.

Low-power multimedia RISC

Battery-powered multimedia systems challenge designers to pack enormous signal-processing power into a low-power chip. The V830 chip achieves this by combining a special instruction set and fast, 32-bit parallel multiply-adder with internal RAM for quicker memory accesses. This gives the newest entry in the V800 series signal-processing capabilities as fast as the latest fixed-point DSPs.