Finite Open-loop Gain Research Articles

Circuit Techniques to Suppress Crosstalk Due to Circuit Nonidealities in Zero-Potential-Biasing Method for Resistive Sensor Matrix

Crosstalk between the sensor element to be read and the other sensor elements in the sensor matrix constitutes a critical problem in reading passive matrix resistive sensors. Various zero-potential-biasing readout circuits have been proposed to solve the crosstalk problem, but crosstalk remains due to circuit nonidealities, such as the offset and finite open-loop gain of the amplifiers and the ON-resistance of the switches used in the readout circuit. Therefore, we propose a novel low crosstalk zero-potential-biasing readout circuit that can suppress crosstalk caused by these nonidealities of circuits. The main ideas of the proposed readout circuit to suppress crosstalk are: 1) including the unaddressed sensors and switches into the feedback loop that is formed by the biasing amplifier to remove crosstalk resultant from the finite open-loop gain of the amplifiers and the ON-resistance of the switches and 2) applying the correlated double sampling method to remove crosstalk caused by the offset of the amplifiers. In the measurement of the proposed readout circuit composed of actual commercial amplifiers and switches, the maximum readout error of the proposed readout circuit for an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> 8 resistor matrix is reduced to lpzrptPlus51.82% from the errors of −81.32% and −88.68% of the previous readout circuits selected for comparison.

A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier

This article presents a 14-b 130-MS/s two-stage pipelined-SAR analog-to-digital converter (ADC) using a distributed averaging correlated level shifting (DACLS) ring amplifier as its residue amplifier (RA). Compared to the prior CLS and ACLS techniques that reduce the RA gain error due to their finite open-loop gain, the proposed DACLS ring amplifier no longer requires an extra level-shifting capacitor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {LS}}$ </tex-math></inline-formula> ) at the RA output, such that the RA bandwidth can be improved. Furthermore, instead of a single-level shift in the prior arts, the DACLS ring amplifier provides an option for multiple level shifts and thereby accomplishes a greater RA gain error reduction. In addition, a customized bypass-window scheme is applied, which can skip some power-wasting digital-to-analog converter (DAC) switchings by window detection and thus reduces the power consumption of the ADC. To reduce the bit-cycling time of the SAR conversion, a delay-reduced (DR) SAR logic is introduced to increase the ADC speed. The ADC chip is fabricated in 28-nm CMOS technology and occupies an active area of 0.013 mm2. At 130-MS/s and the Nyquist-rate input frequency, the measured SNDR is 72.5 dB, while the power consumption is only 0.82 mW. Without any calibration, the proposed ADC achieves a Walden and a Schreier figure-of-merit (FoM) of 1.8 fJ/conversion step and 181.5 dB, respectively. Compared to the prior-art ADCs with an input bandwidth ≥ 40 MHz and a SNDR > 68 dB, this work shows the best FoMs.

Self-Calibrated AC Zero Potential Circuit for Two-Dimensional Impedimetric Sensor Matrices

Zero potential circuits (ZPC) can be used for reducing cross-talk effects within the 2-Dmatrices. ZPC using AC excitation signals (AC-ZPC) with different frequencies in every row can address all the sensors in a matrix simultaneously. The main challenge thereby is the remaining deviations. To analyze the reasons for this, an analytical model of the column-side output voltages is elaborated, which takes into account the non-ideal characteristics of the operational amplifiers, including the input impedance, finite open-loop gain factor, leakage current, output impedance, and load impedance. Based on this model, a novel method is proposed to realize a higher AC measurement accuracy by suppressing the matrix row side impedance through voltage followers and compensating the matrix column side non-ideal amplifiers through reference units. For compensation, one row and one column of given impedimetric units are included in the target matrix as reference elements. The measurement deviations are reduced by comparing the output differences between the targeted sensor and the reference elements. In a simulation for a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times 4$ </tex-math></inline-formula> impedimetric sensor matrix composed of RC elements from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.9\,k\Omega \vert \vert 361.7\,pF$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$100.4\,k\Omega \vert \vert 7.3\,pF$ </tex-math></inline-formula> , this new method achieves measurement deviations below 0.1%, which is a significant improvement over previous works that reached deviations above 1%.

Combined Finite Element and Electronic Circuit Model of a Wire-Mesh Sensor

A new wire-mesh sensor model based on electric field and circuit simulations is presented. In our approach, the excitation and amplification stages of the capacitance WMS are created as macromodels and coupled to the electrodes of a 3D geometry of the sensor. Thus, the effects caused by nonideal characteristics of the amplifiers are considered (e.g. finite open-loop gain and bandwidth). In order to evaluate the performance of the model, a static validation based on phantom measurement was performed. The phantoms were created with paraffin to emulate typical flow regimes, i.e. annular, slug and bubble flow. A mapping containing the position and the electrical properties of the patterns was obtained by image processing and incorporated to the field simulation. Hence the numerical simulations could be directly compared to the experimental data. The results show that coupling the external circuits to the capacitance WMS model is crucial to provide reliable synthetic data.

Optimal design of a fractional order immittance in the second quadrant with wide CPZ

This paper presents a design technique to realize fractional order (FO) immittance in the second quadrant of the impedance plane, using Bruton’s generalized immittance converter (GIC). Design guidelines are developed based on a sub-optimal analysis of phase error resulted by non-ideal op amps. The analysis takes into account finite open-loop dc gain and finite unity-gain frequency of practical op amps and aim to maximize the constant phase zone for a given phase band specification. The fractance of the realized fractor can also be tuned to a desired value by varying one of the GIC resistances. Several simulations and experimental validations are demonstrated. Also, high Q, FO bandpass filter with wide tuning range is presented as an application of the designed obtuse angle fractor.

A high sensitivity low-power capacitive front-end for insulin injection pens

A low-power 14-bits first order incremental Analog-to-Digital Converter (ADC) is presented. Based on the charge balancing principle, this switched-capacitor (SC) circuit integrates the input signal multiple times to reach the targeted resolution, linearity and noise performances. The sensitivities to non-ideal effects usually plaguing analog CMOS SC circuits, such as amplifier finite open-loop gain, offset, noise, parasitic capacitances and charge-injection of the switches are discussed. Their impact on the conversion accuracy and speed are evaluated, and corresponding design constraints are deduced. The ADC is implemented in an Application Specific Integrated Circuit (ASIC) in an AMS0.35 μm process and is aimed for a high accuracy capacitance sensing to monitor the insulin injection in pens for diabetics. A minimum resolution of 0.3 fF, proportional to a third of an injectable insulin unit is targeted. The ADC is made low-power, allowing thus to perform many measurements per day considering its implementation in a lithium battery powered injection pen system of six months' life cycle.

High‐speed analogue sampled‐data signal processing for real‐time fault location in electrical power networks

The emulation of low-loss or lossless one-dimensional (1D) or 2D transmission mediums using analogue sampled-data signal processing is presented. Based on discrete-time wave propagation simulation, transmission lines are emulated with many elementary identical delay elements, implemented by simple equivalent switched-capacitor (SC) circuits. The accuracy and limitations of this discrete time model are studied in the frame of power network fault location using electromagnetic time-reversal principle. The sensitivities to non-ideal effects usually plaguing analogue CMOS SC circuits, such as amplifier finite open-loop gain, offset, and parasitic charge injection due to clock feedthrough, are evaluated in the same context. It is shown that the SC line emulation is well suited to the presented fault location technique and considerably reduces the fault location time (by a factor up to 100) in comparison to standard digital solutions, allowing fault location resolutions of typically 1% within a few hundred milliseconds. These expectations are confirmed by measurements realised on the presented line model integrated-circuit, implemented in an AMS 0.35 μm CMOS process. The speed improvement obtained through the presented method is essential, potentially allowing real-time fault management in power grids.

Design of a 10-bit 1 MS/s pipelined SAR ADC for CZT-based imaging system

A 10-bit 1 MS/s pipelined SAR ADC for CZT-based imaging system is presented. The ADC is composed of three pipeline stages which are two 4-bit SAR-based Multiplying Digital Analog Converters (MDACs) and a 4-bit SAR ADC. In order to improve the performances of the proposed ADC, several techniques were proposed. Firstly, a novel 4-bit MDAC circuit which can eliminate the offset voltage of residue amplifier is proposed here. Secondly, digital correction technique is adopted for eliminating the error induced by offset voltage of comparator. As long as the offset voltage is less than 1/16 Vref, the offset voltage can be corrected. Thirdly, digital calibration technique is used to calibrate the gain errors due to capacitor mismatch, finite open-loop gain and finite gain band width (GBW) of residue amplifier and so on. The prototype chip was fabricated in a 0.35µm CMOS process and occupies a core area of 960×1260µm2. The proposed pipleined SAR ADC achieves 55.6dB SNDR at 1MS/s sampling rate and consumes 8.2mW power. The FOM of the proposed ADC is 17.2pJ/conversion-step.

A calibration technique based on sub-stages’ weights of pipelined ADC

This paper describes an efficient background calibration technique for pipelined analog-to-digital converters (ADCs). This technique calibrate the interstage gain errors, capacitor mismatches and finite opamp open-loop gain by updating the weights of sub-stages that carry the information about these errors. A weight-based errors model is built to simplify calibration algorithm. The errors are merged into the weight of the corresponding stage. The first seven stages of every signal path are calibrated to achieve high resolution and eliminate errors. Two extra sub-stages are used in the calibration process to implement background calibration. The improved technique is used in a 14-bits 80 MS/s pipelined ADC. The results demonstrate that it can decrease errors, increase the effective number of bits by 2.04, and SFDR is 90.12 dB and ENOB is 13.2 bits. The ADC implemented in chartered 0.18 μm CMOS process consumes 260 mW, occupying a chip area of 7.16 mm2.

OTA-C based high-speed analog processing for real-time fault location in electrical power networks

This paper explores the potential and limitations of analog integrated circuit techniques for the simulation of low-loss or lossless 1D or 2D transmission mediums. In this approach, a transmission line is mapped into a ladder consisting of N identical LC elements, each modeling a finite length increment of the line. Inductors are then emulated by a gyrator-capacitor combination, yielding a classical transconductor-capacitor (gm-C) circuit, suitable for integration. The validity of this approximation is discussed in the context of fault location in power networks, an application based on the electromagnetic time-reversal method. Design constraints on gm-C circuits are derived and non-ideal effects such as finite open-loop gain and component mismatches are evaluated. It is shown that a simple analog implementation can locate the fault within 1 % accuracy with a significant speed advantage over classical computational methods, reducing the processing time to <100 ms.

Non-Foster Matching of a Resistively Loaded Vee Dipole Antenna Using Operational Amplifiers

A non-Foster matching network using negative impedance converters (NICs) is proposed for a resistively loaded vee dipole antenna (RVD). The RVD suffers from considerable reflection at the feeding transmission line at low frequencies because of its large negative input reactance. To reduce the reflection, a non-Foster matching network, which is composed of NICs based on operational amplifiers (op-amps), is proposed. For the practical design, the effects of input parasitic capacitances of the op-amp and the finite open-loop gain are considered. The stability analysis is performed according to the Barkhausen stability criterion. The non-Foster matching network is implemented with the RVD as a load. The measured impedance demonstrates that the matching network significantly reduces the input reactance of the RVD. In the time-domain analysis, the matched RVD is shown to reflect significantly less incident pulse. A target was imaged through a series of radar echo experiments. The images show that the non-Foster matching network enhances the performance of the RVD as an antenna for the ground-penetrating radar.

Non-Ideal Op-Amp Circuit Analysis

Op-amps are commonly used by instrumentation engineers. In the ideal case, the open-loop gain of an op-amp is regarded as infinite, the input impedance as infinite, and the output impedance as zero. In many cases, however, it is necessary to estimate the performance of an op-amp circuit with consideration of non-ideal parameters, and therefore it is necessary to analyse the non-ideal characteristics of the op-amp circuit. This paper discusses the effect on circuit performance of non-ideal parameters, i.e. finite open-loop gain, finite input impedance and non-zero output impedance of op-amps. A concept ‘loop gain’ is introduced and the dynamic behaviour, i.e. the frequency response, is analysed based on a first-order dynamic model.

Behavioral modeling of delta–sigma modulators

This paper presents an overview of DelSi, a MATLAB toolbox developed for the design and simulation of delta–sigma modulators. The DelSi toolbox can synthesize a stable noise-transfer function for complex network structures. The modelling tool consists of two c/ c ++ programs, sdMod.c, a single stage delta–sigma modulator and firfilt.c, a decimating FIR filter. Cascaded modulators can be constructed using the programs as building blocks. The simulation tools support the inclusion of nonideal effects caused by circuit imperfections, such as amplifier finite open-loop gain, incomplete settling and saturation as well as capacitor ratio mismatches. Two design examples are presented: one for a 1–1–1 cascade and the other for a single-stage fifth modulator.

A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller

This paper describes the design and implementation of a fully monolithic 16-b, 1 Msample/s, low-power A/D converter (ADC). An on-chip 32-b custom microcontroller calibrates and corrects the pipeline linearity to within 0.75 LSB integral nonlinearity (INL) and 0.6 LSB differential nonlinearity (DNL). High speed and low power are achieved using a pipelined architecture. Errors resulting from capacitor mismatches, finite op-amp open loop gain, charge injection and comparator offset are removed through self-calibration. Coefficients determined during calibration are stored on chip, digitally correcting the pipeline ADC in real time during normal conversion, Full-scale errors are removed through self-calibration and an-chip multiplication. Linearity errors due to capacitor voltage coefficients are reduced using a curve fit algorithm and on-chip ROM. Digital cross-talk errors resulting from the microcontroller running at a rate of ten times the analog sampling rate have prevented implementations of fully monolithic converters of this performance class in the past. Mismatches in cross-talk due to different digital timing between calibration and correction lead to linearity errors at critical correction points. Experimental analysis and circuit techniques which overcome these problems are presented.

Nonideality consideration for high-precision amplifiers-analysis of random common-mode rejection ratio

Nonideal factors which play a key role in performance and yield in high-precision applications of operational amplifiers are rigorously investigated. The combined effects of both deterministic and statistical parameters must be incorporated. The statistical characteristics of the common-mode rejection ratio (CMRR) and the offset of two-stage CMOS op-amps are investigated. The op-amp errors associated with finite open-loop gains, finite CMRRs, and nonzero offset voltages are analyzed. It is shown that the random common-mode gain as determined by the mismatch of paired devices is comparable to the deterministic common-mode gain. It is shown that the probability density function of the CMRR is distributed similarly to that of a Gaussian random variable, but the mean is finite and the symmetry is skewed somewhat, as contrasted with the probability density function of the offset voltage which has a Gaussian distribution with zero mean. It is also shown that a nonideal finite CMRR can actually reduce the op-amp errors caused by a finite open-loop gain. >

A model of op-amp circuits

In stability analysis, op-amp circuits are often modeled as single-loop feedback systems, as shown with a finite open-loop gain A in the forward path and beta in the feedback path. The author proposes a different model that has two feedback loops. The model is useful in stability of op-amp circuits and in determining the oscillation conditions of Wien-bridge oscillators. The model has one positive feedback loop and one negative loop. The model is easy to develop and offers better insight into op-amp circuits than the single-loop model. >

A switched-capacitor charge-balancing analog-to-digital converter and its application to capacitance measurement

An analog-to-digital converter is developed based on the charge-balancing principle. It consists of a switched-capacitor integrator, comparator, and digital logic circuit. Driven by the two phase clock, the integrator accumulates consecutively the incremental signal charge while extracting the quantized reference charge from the accumulated signal charge each time its output becomes positive, to keep their charge balance. The ratio between the accumulated and extracted frequencies for a given period of time then provides the digital representation of an input analog signal. A conversion accuracy higher than 14 bits can be expected from its integrated realization because the offset voltage and the finite open-loop gain of an op-amp and the parasitic capacitance have no effect upon the conversion process. It also features a small device-count integrate onto a very small chip area. Some applications are also presented to demonstrate its validity.

Low-noise In-Sb photodetector preamp for the infrared

A low-noise, cryogenically cooled preamplifier has been designed and built for indium antimonide detectors used in IR astronomy. General noise and frequency response equations for the transimpedance amplifier are derived. The effects of finite open-loop gain and bandwidth and of photodetector parameters on circuit performance are shown. A current-injecting background cancellation scheme based on optical feedback and synchronous filtering is described. Total electrical NEP figures as low as 10/SUP -16/ W (at 5 /spl mu/m) and background rejection ratios higher than 3000:1 have been measured using a 0.5 mm diameter detector.

A novel passive compensated inverting weighted summer

It is well known that the finite and complex open loop gain nature of the op-amp degrades significantly the performance of the inverting voltage controlled voltage sources (VCVS) employing them.*” Wilson’ has proposed a passive compensation method for the inverting VCVS using two compensating capacitors. Recently3 it has been found that the addition of only one compensating capacitor instead of two results in less phase and magnitude errors than in Wilson’s compensation.’ The compensation of an m input inverting weighted summer using the recently proposed method by the authors3 requires m capacitors. The purpose of this contribution is to introduce a novel passive compensation method for the inverting weighted summer which requires only a single capacitor, regardless of the number of input ports. Moreover, the new compensation circuit has smaller phase and magnitude errors than those obtained using other passive compensation methods. Figure 1 represents the new passive compensated inverting weighted summer. Compensation is achieved here by using two passive circuit components, a capacitor C and a resistor r. Let the open loop gain of the op-amp be represented in the form

Dynamic characteristics of a simple constant-temperature hot-wire anemometer

A simple constant-temperatue hot-wire anemometer has been analyzed and tested in a shock tube and by electronic tests. In the derivation of the governing equations, the finite open-loop gain of an operational amplifier is considered. The measured values of the natural frequency and the damping coefficient for the anemometer system are in satisfactory agreement with the theory. For short probe cables, the frequency response is found to be limited by the finite open-loop gain of the amplifier.