Finite Opamp Gain Error Research Articles

CFCS calibration circuit design for multi-bit pipelined ADC architectures

Design of high resolution ADCs in scaled CMOS technology is challenging due to increased component mismatch, comparator offset, and finite op-amp gain error. In this work, a commutated feedback capacitor switching calibration technique has been proposed to improve the ENOB and linearity of ADCs with multi-bit pipeline architecture. During normal operation of ADC, the fixed sampling capacitor is swapped in the feedback capacitor. We have distributed the sampling capacitor and swap the feedback capacitor with the sampling capacitor(s) in the MDAC of each pipeline stage ADC. The mismatches of different pipeline stages are concurrently corrected in the digital domain. Proposed technique requires digital calibration circuits and requires no extra calibration phase cycles. The prime objective of this work is to achieve high linearity and ENOB in pipeline architectures with low power consumption. Behavioral simulation of 16-bit 5Ms/s pipeline ADC in UMC 0.18 µm double poly triple metal processes with proposed calibration shows significant improvement in DNL with σ = 0.25% capacitor mismatch with correct 16-bit digital output. The design is implemented using HSPICE simulation. The robustness of the proposed technique has been verified by process, temperature and voltage variation simulations and Monte Carlo analysis.

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter (RSD-ADC) is presented featuring a high signal to noise ratio (SNR), spurious free dynamic range (SFDR) and signal to noise plus distortion (SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC (residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.

A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR

An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 /spl mu/m CMOS process, achieves 77-dB SFDR at 0.9 V and 5MSPS (30 MHz clocking) after calibration. The measured SNR, SNDR, DNL, and INL at 80 kHz input are 50 dB, 50 dB, 0.6 LSB, and 1.4 LSB, respectively. The total power consumption is 12 mW, and the active die area is 1.4 mm/sup 2/.

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

A time-shifted correlated double sampling (CDS) technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. An efficient common-mode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18-/spl mu/m CMOS process, the prototype 10-bit pipelined ADC occupies 2.5 mm/sup 2/ of active die area. With 1-MHz input signal, it achieves 65-dB SFDR and 54-dB SNDR at 100MS/s. For 99-MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8-V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline.

True background calibration technique for pipelinedADC

A digital background calibration technique for a pipelined analogue-to-digital converter (ADC) is presented. The calibration technique involves the use of a slow, but accurate, ADC in conjunction with a least-mean squares (LMS) algorithm to find the parameters, which correct for residue errors such as finite op-amp gain error, capacitor ratio mismatch and charge injection error in a non-ideal pipeline stage, resulting in a significant improvement in the INL and the DNL of the ADC.