FinFET Technology Research Articles

Performance Analysis of 8x4 Barrel Shifters in CMOS and FINFET Technology

Shifters are essential components in digital circuits, enabling data manipulation and routing for a wide range of computational tasks. This study presents a comprehensive performance analysis of 8x4 barrel shifters implemented in two distinct semiconductor technologies: Complementary Metal-Oxide-Semiconductor (CMOS) and FinFET. This study compares and evaluates the important parameters for these shifters at both technological nodes, such as power consumption. Additionally, we examine the effects of scaling on CMOS barrel shifters. Conversely, FinFET technology, recognized for overcoming certain limitations of CMOS, is assessed for its potential to enhance performance while preserving energy efficiency. Through detailed simulation and analysis, this study offers valuable insights into the benefits and limitations of CMOS and FinFET implementations for 8x4 barrel shifters. The circuit is implemented using Cadence Virtuoso and optimized to leverage the unique features and address the limitations of 45nm CMOS and 22nm FinFET technologies. Furthermore, the study offers recommendations for selecting the appropriate technology based on specific performance criteria and application needs. The findings aim to guide future design decisions and improvements in shifter technology.

Research of Gate-All-Around Field-Effect Transistors

This report provides an overview of GAA FETs also known as Gate-All-Around FETs, focusing on their introduction and limitations, based on a comprehensive review of current literature and online resources. GAA FETs represent an evolution of FinFET technology, which itself was developed from traditional MOSFET designs. Each iteration has aimed to improve performance and overcome limitations of its predecessor. The GAA architecture offers superior electrostatic control, resulting in higher drive currents, reduced leakage, and improved subthreshold swing, making it ideal for high-performance, low-power applications. Despite these advantages, GAA FETs still face challenges with short-channel effects (SCEs) as device dimensions shrink. Gate-All-Around (GAA) is a transistor architecture designed to address the limitations of the FinFET design. Unlike FinFET, where the channel is surrounded on three sides by the gate, GAA surrounds the channel on all four sides by turning the FinFET structure sideways, making the channels horizontal. This design provides enhanced control over the transistor switch. The fabrication of GAA transistors involves a series of highly precise processes, which enable improved transistor scaling with reduced variability, resulting in increased performance and lower power consumption.

FinFET-Based Feedback Control Assisted Near-Threshold SRAM Cell

This paper presents a single-ended 12-transistor SRAM cell capable of operating at near-threshold voltage in FinFET technology. This cell employs Schmitt trigger-based inverters and feedback cut write assist technique to improve performance properties. The simulations have been done through HSPICE using 10 nm FinFET technology at a supply voltage of 0.45 V and a temperature of 25°C under 5000 Monte Carlo tests. The proposed cell improves the read static noise margin by at least 1.01 times. The write static noise margin is also increased by at least 1.07. The proposed single-ended cell leads to a reduction of α BL by 50% and offers low dynamic write power. The leakage power is also reduced by 1.03 times due to the use of single bitline in the cell structure, stack transistors in the write path and elimination of leakage in the read path.

Analysis of voltage mode quadrature oscillator based on fin field-effect transistor

This study introduces a new voltage mode sinusoidal quadrature oscillator (V-M.S.Q.O.) that employs multioutput Z copy voltage differencing transconductance amplifiers (M-Zc-VDTA) as an active filter based on FinFET transistor. The suggested circuits have low passive and active sensitivities, and they may be constructed as integrated circuits using only two M-Zc-VDTAs and three grounded capacitors. The circuits produce two (VM) sinusoidal quadrature oscillator voltage results by adjusting the electronic base current and frequency of the oscillation condition separately. FinFET technology lowers power consumption while improving circuit performance. They can also produce amplitude shift keying-amplitude modulation signals for communication electronics systems and provide electrical basis control of output current amplitude. Using the Cadence Virtuoso tool with a 7 nm parameter, simulation results were obtained for the suggested circuits.

Comprehensive Review of FinFET Technology: History, Structure, Challenges, Innovations, and Emerging Sensing Applications.

The surge in demand for 3D MOSFETs, such as FinFETs, driven by recent technological advances, is explored in this review. FinFETs, positioned as promising alternatives to bulk CMOS, exhibit favorable electrostatic characteristics and offer power/performance benefits, scalability, and control over short-channel effects. Simulations provide insights into functionality and leakage, addressing off-current issues common in narrow band-gap materials within a CMOS-compatible process. Multiple structures have been introduced for FinFETs. Moreover, some studies on the fabrication of FinFETs using different materials have been discussed. Despite their potential, challenges like corner effects, quantum effects, width quantization, layout dependencies, and parasitics have been acknowledged. In the post-planar CMOS landscape, FinFETs show potential for scalability in nanoscale CMOS, which leads to novel structures for them. Finally, recent developments in FinFET-based sensors are discussed. In a general view, this comprehensive review delves into the intricacies of FinFET fabrication, exploring historical development, classifications, and cutting-edge ideas for the used materials and FinFET application, i.e., sensing.

Single-Event Effect Characterization of 16 GHz Phase-Locked Loop in Sub-20 nm FinFET Technology

Single-Event Effect Characterization of 16 GHz Phase-Locked Loop in Sub-20 nm FinFET Technology

An energy and area-efficient spike frequency adaptable LIF neuron for spiking neural networks

As Moore's law approaches its limit, conventional computing methods face energy efficiency challenges, prompting the exploration of alternative information processing methods like spiking neural networks (SNNs). Neurons, the fundamental unit of the nervous system, are crucial for efficiently implementing SNNs in hardware, requiring energy and area-efficient design. This paper presents novel circuit designs for the leaky integrate-and-fire (LIF) neuron model at 7 nm FinFET technology, including 8T FinFET LIF Neuron 1, 7T FinFET LIF Neuron 2, 7T FinFET LIF Neuron 3 and 6T FinFET LIF Neuron 4. In the proposed configurations of LIF neuron, the energy per spike is reduced by 95.80 %, 95.89 %, 95.89 %, 96.76 %, and 96.65 % in the 8T FinFET LIF neuron 1 (case 1), 8T FinFET LIF neuron 1 (case 2), 7T FinFET LIF Neuron 2, 7T FinFET LIF Neuron 3, and 6T FinFET LIF Neuron 4, respectively, compared to the lowest energy per spike reported in the literature, with the minimum known energy per spike being 0.67 fJ. The proposed FinFET neurons offer attractive hardware acceleration (spiking frequency in the MHz range), minimal energy per spike (fJ range), simplicity, and area efficiency, making them more biologically plausible due to their adaptable spiking frequency.

Aggravated NBTI reliability due to hard-to-detect open defects

FinFET technology has become an attractive candidate for high-performance and power-efficient applications. In the other hand, the behavior of FinFET devices is influenced by self-heating effect (SHE) due to its 3D structure, low thermal coupling and quantum confinement effect, among others. SHE degrades the device’s performance and could worsen reliability mechanisms like NBTI. In addition, some hard-to-detect open defects in FinFET based-circuits using logic gates designed with multi-fin and multi-finger techniques may escape the test and present abnormal static currents, which may increase the impact of self-heating effect and make the NBTI degradation more severe. Hence, it is crucial to accurately determine the temperature profiles of those chips passing the test and presenting abnormal static currents. This paper investigates the reliability of chips passing the test with abnormal static currents using Sentaurus Technology Computer-Aided Design (TCAD). FinFET transistors are calibrated with Intel 14-nm FinFET technology. Our TCAD simulation framework determines accurately the temperature and NBTI degradation. Using the TCAD information, the device degradation over time can be predicted. Moreover, the delay penalization of a critical logic path of an ISCAS benchmark circuit is investigated. The delay penalization of logic paths, attributed to the defect and NBTI, is analyzed with varying logic depths, emphasizing the importance of addressing critical paths with different logic depths. Our study leads to new considerations for improving the prediction of circuit reliability and taking countermeasures.

(Invited) Material Engineering for the GAA and Post-GAA Transistors and Interconnects

Feature scaling in advanced CMOS technology has been slowing down starting at 10 nm node and is expected to stop completely in the next few years. Nevertheless, transistor density scaling is continuing at a Moore’s law pace, driven by DTCO and 3D IC.Transistor dimensions and minimum metal pitch are expected to be massaged down only by 10% to 20% during the next decade. However, both the transistor and the interconnect will continue to evolve and improve both in performance and in variability.Currently, the industry is transitioning from FinFET technology to GAA (Gate All-Around) technology. The next transition, from GAA to the NMOS and PMOS GAA transistors stacked on top of each other (often referred to as CFET (Complementary Field Effect Transistor)) is expected in 8 to 10 years from now.The main methodology for GAA and CFET transistor engineering comes down to bandstructure engineering, where material composition, shape and thickness of different layers, and mechanical stress are engineered to tailor a bandstructure of the channel that maximizes on-state driving strength and minimizes off-state leakage and variability. The key methodology for bandstructure engineering is ab-initio analysis of transistor components and then transfer of the obtained bandstructure to transistor scale analysis to characterize its behavior.For the interconnect engineering, the tight metal pitches and increasingly tall and narrow vias dictate transition from copper to alternative metals, with a preference for the metals that can be etched and selectively grown. The key methodology for interconnect engineering is ab-initio analysis of electron scattering at the interfaces and grain boundaries. The scattering is then converted into interconnect resistance that defines speed and power consumption of the advanced CMOS circuits.This work introduces the concepts of transistor band structure engineering and interconnect scattering engineering and provides illustrations of these methodologies applied to GAA and post-GAA technologies.

Effects of driving capability on single-event transient of inverter in bulk FinFET Technology

Effects of driving capability on single-event transient of inverter in bulk FinFET Technology

ANN-based framework for modeling process induced variation using BSIM-CMG unified model

In this work, we present a machine-learning augmented compact modeling framework for modeling process induced variations in advanced semiconductor devices. The framework employs BSIM-CMG unified compact model at the core and can be used for any advanced devices like GAA nanosheets and nanowires, FinFETs etc. We have validated the model with extensive numerical simulations and experimental data such as 14nm technology FinFET and 24nm technology Nanowire. Our results show excellent accuracy in modeling variability in key electrical parameters of the device including off-current (Ioff), on-current (Ion), threshold voltage (Vth), subthreshold swing (SS) etc. We observe that the overall accuracy of the ML-based framework strongly depends on the nature and physical behavior of the core model used for modeling the nominal device.

A Compact, Low-Power, and Low-Jitter Fractional-N Phase-Locked Loop with a Single-Ended Ring Voltage-Controlled Oscillator in a 12 nm CMOS FinFET

PLLs with small areas, low power consumption, and low jitter are crucial for mobile applications. Hence, achieving a balance between the area, power consumption, and noise of a PLL is a significant issue. In this work, a compact, low-power, and low-jitter fractional-N PLL using Ring-VCO is introduced. In order to reduce area and power consumption, a single-ended Ring-VCO is implemented. Additionally, novel resistance matrixes are proposed to decrease phase noise. The resistor matrix creates 13 frequency tuning curves with close VCO gain and different initial frequencies, reducing the VCO gain and thus the overall noise while maintaining high tuning linearity. The proposed PLL is fabricated based on 12 nm FinFET technology with a 0.078 mm2 area. It achieves a 2.702 ps RMS jitter at 5.76 GHz while consuming 6.4 mW. Moreover, it maintains a low power consumption and a low RMS jitter across the entire frequency range.

Advantages, manufacturing processes and challenges of FinFET technology

Abstract As an emerging cutting-edge integrated circuit technology, Fin Field Effect Transistor (FinFET) has not only successfully broken through the limitations of the 22nm node since its development in 1998, but it still maintains considerable vitality and is developing into smaller sizes. As an improvement over traditional MOSFET technology, FinFET offers many technical advantages, which practically solve the challenges encountered by traditional MOSFET. The FinFET process technology is incompatible with planar MOSFET process technology. Moreover, since the development of Finfet technology, there have been many technical challenges. The first half of this article mainly introduces the differences and advantages between FinFET and traditional Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), and briefly outlines its manufacturing process. The second half explains the challenges and hopes on the development path of FinFET technology. I believe this article can provide a reference for integrated circuit designers when understanding FinFET technology, and provide guidance and reference for beginners.

Design of low delay low power hybrid logic based flip-flop using FinFET

The need for a low-power and high-speed technology for computation of digital signals is rising due to the fast growth of technological innovations. Flip-flops serve as fundamental elements in signal processing technologies. Hybrid logic has great potential for constructing flip-flop circuits because of its minimal transistor count as well as low-power properties.The present investigation presents a design for a tiny and low-power hybrid flip-flop that operates fully statically. The design has been developed by utilizing different circuitry-reduction techniques. It incorporates a hybrid logic approach combining pass transistor logic to decrease circuit complexity. The ongoing work utilizes a hybrid logic with low delay and low power to generate flip-flops. The proposed flip-flop design significantly decreases latency compared to the existing master-slave flip-flops. This flip-flop remains immune to clock overloading, resulting in reduced power consumption. Reducing the quantity of PFET (P-channel Field Effect Transistor) transistors enhances the circuit's delay, area, and power consumption. Implementing these circuit optimization techniques yields several benefits, such as reduced CLOCK-to-OUT and DIN-to-OUT node delays, decreased average power consumption, lower leakage power, and a transistor count of only 18. The results were achieved using Cadence Virtuoso at 18 nm finFET technology, with varied process corners, supply voltages ranging from 0.7 V to 1 V, and temperatures ranging from -50 °C to 75 °C. This study also presents a Monte Carlo simulation of power consumption, leakage, and delay for the suggested flip-flop. According to the simulations, the recommended flip-flop exhibits exceptional stability. The recommended flip-flop has lower power usage by at least 17.95 % compared to standard architectures due to the lower number of PFET transistors.

[formula omitted] IO buffer with [formula omitted] devices considering hot-carrier and gate-oxide reliability issues

This paper presents circuit for 2×VDD signaling I/O buffer to solve the gate-oxide and hot-carrier reliability issues without consuming any active static power. The design is verified for a range of loads varying from 4 pF to 200 pF with operating speed ranging from 12 Mbps to 500 Mbps. The proposed circuit is implemented in 16 nm FinFET technology using 1.8 V thick gate devices. The design can be used in any CMOS technology for 2×VDD signaling I/O buffer to reduce hot-carrier effect and to avoid gate-oxide reliability issues.

Analysis and design of a 0.9 V 1 GHz-BW 14.6 dBm-OIP3 broadband receiver with current-mode analog baseband in 12 nm FinFET CMOS

This study introduces a wideband LNTA-based receiver employing full current mode (FCM) signal transmission, leveraging a broadband and highly linear current-mode analog baseband (CMAB). The CMAB module comprises a shunt feedback low pass filter and a programmable gain amplifier (PGA) with wide bandwidth, utilizing a regulated CG current mirror design, enriched by gm-boosting methodology and positive feedback capacitance reutilization through an identical boost amplifier. Fabricated in 12 nm FinFET CMOS process, the FCM receiver attains notable characteristics including a baseband bandwidth of 1 GHz, a conversion gain of 30 dB, a noise figure of 5.2 dB, and an OIP3 of 14.6 dBm, while operating with a low supply voltage of merely 0.9 V. Simulation results validate the efficacy of this FCM receiver for wideband communication, effectively addressing the linearity constraints associated with low supply voltages and maximizing the advantages of FinFET technology in current-mode signal transmission. The total layout area is 0.484 mm2.

A novel high-performance TG-based SRAM cell with 5 nm FinFET technology

In this study, we investigate the performance and reliability of a novel static random-access memory (SRAM) cell utilizing advanced 5 nm FinFET technology. Our research aims to address critical challenges in SRAM design by integrating transmission gates and power gated transistors. Through extensive simulations using the Cadence Virtuoso tool, we optimize the SRAM cell’s read and write paths, resulting in substantial improvements in both functionalities. Additionally, our study unveils temperature-dependent variations in the read current and write margin, emphasizing the influence of temperature on SRAM performance. Compared to conventional FinFET SRAM circuits of equivalent bit-cell area and read latency, our innovative design showcases remarkable improvements across various parameters. Specifically, we achieve a commendable increase of 6.16% in the write static noise margin (WSNM) and 5.86% in the hold static noise margin (HSNM). Moreover, our findings reveal a substantial boost in read stability, increasing from 14.75% to 18.35%. These advancements underscore the promising potential of our approach in paving the way for future innovations in high-performance memory architectures. By leveraging state-of-the-art technology and meticulous optimization techniques, our research sets a new standard for SRAM design, offering enhanced performance, reliability, and efficiency in memory systems.

Design and Analysis of High Performance FinFET-Based Linear Feedback Shift Register for Cryptography Applications

Nowadays, all the elements of our surrounding is occupied by electronics. Electronics occupies major role on our day today life. Electronics device integration on a single chip enhances performance in terms of speed, low-power circuits, and area. Integration of VLSI provides better scalability and reliability. This research paper focused on the implementation of Linear feedback shift registers (LFSR) using FinFET techniques at the layout level for various applications, including cryptography. FinFETs are highlighted as a replacement for CMOS technology, offering advantages such as improved performance in terms of speed, low-power circuits, and area. Linear feedback shift registers are commonly used in digital systems and cryptography for generating pseudo-random sequences. The use of FinFET technology in the layout level suggests an interest in exploring advanced semiconductor technologies to enhance the performance of these circuits. The paper appears to cover different design methods of LFSRs, which could include aspects like circuit optimization, power efficiency, and reliability. The integration of electronics on a single chip, particularly with FinFET technology, is noted for its potential to provide better scalability and reliability. The first architecture is created using bulk CMOS techniques; whereas the second is constructed using two fin FinFET LFSRs. Using the Microwind designing tool, the third technique is developed with a 3-fin FinFET LFSR. It provides a solution for a novel FinFET architecture that implements LFSR. When comparing CMOS and FinFET circuit designs for LFSR, the latter achieves superior performance in terms of area and power efficiency. An analysis is conducted on the design techniques and performance of CMOS LFSR, 2 fin FinFET based LFSR, and 3 fin FinFET. According to the experimental findings, the CMOS-based LFSR uses 1.243 mW of power; the FinFET-based LFSR uses 90.47 μW, and the two fin FinFET LFRS uses 0.254 mW.

Squaring Circuit Using 14nmFinFET Technology with Vedic Mathematics Approach

FinFET technology is an alternative to CMOS technology as in this technology device has higher drive current, speed, and low-power consumption. FinFET has better mobility and scaling than CMOS technology. A dedicated Squaring circuit is needed by many digital signal processors (DSP) and arithmetic and logical units (ALU). So fast, power-efficient, and compact squaring circuits can be designed with Vedic sutras. Vedic mathematics has 16 sutras and 13 sub-sutras that touch almost all different chapters of mathematics. Out of these sutras, Dwandwayoga has a duplex property that is used to find a square of an N-bit number. Also, Yavadunam is a special case for finding the square of a number that is closer to the base. This work targets a comparative analysis of these two square circuits having a Vedic approach with a conventional array multiplier. The proposed designs are implemented in micro-wind 3.9 electronic design automation tool (EDA) with 14 nm deep submicron technology post-layout. The values of model parameters are used from the current Berkeley 4 short channel model (BSIM4). It is observed that the proposed square architecture design using the Dwandwayog sutra and Yavadunam sutra achieves 185%, 272.45% delay depletion and a 122.22%, and 46.52% reduction in transistor requirements compared to the conventional array multiplier, respectively.

High-Throughput Polar Code Decoders with Information Bottleneck Quantization.

In digital baseband processing, the forward error correction (FEC) unit belongs to the most demanding components in terms of computational complexity and power consumption. Hence, efficient implementation of FEC decoders is crucial for next-generation mobile broadband standards and an ongoing research topic. Quantization has a significant impact on the decoder area, power consumption and throughput. Thus, lower bit widths are preferred for efficient implementations but degrade the error correction capability. To address this issue, a non-uniform quantization based on the Information Bottleneck (IB) method is proposed that enables a low bit width while maintaining the essential information. Many investigations on the use of the IB method for Low-density parity-check code) LDPC decoders exist and have shown its advantages from an implementation perspective. However, for polar code decoder implementations, there exists only one publication that is not based on the state-of-the-art Fast Simplified Successive-Cancellation (Fast-SSC) decoding algorithm, and only synthesis implementation results without energy estimation are shown. In contrast, our paper presents several optimized Fast-SSC polar code decoder implementations using IB-based quantization with placement and routing results using advanced 12 nm FinFET technology. Gains of up to 16% in area and 13% in energy efficiency are achieved with IB-based quantization at a Frame Error Rate (FER) of 10-7 and a polar code of N=1024,R=0.5 compared to state-of-the-art decoders.