Fine Pitch Solder Research Articles

Undissolved gold in fine-pitch BGA solder joint under thermal cycling test

Undissolved gold in fine-pitch BGA solder joint under thermal cycling test

Development of novel single-die hybridisation processes for small-pitch pixel detectors

Hybrid pixel detectors require a reliable and cost-effective interconnect technology adapted to the pitch and die sizes of the respective applications. During the ASIC and sensor R&D phase, especially for small-scale applications, such interconnect technologies need to be suitable for the assembly of single dies, typically available from Multi-Project-Wafer submissions. Within the CERN EP R&D programme and the AIDAinnova collaboration, innovative hybridisation concepts targeting vertex-detector applications at future colliders are under development. Recent results of two novel interconnect methods for pixel pitches of 25 µm and 55 µm are presented in this contribution — an industrial fine-pitch SnAg solder bump-bonding process adapted to single-die processing using support wafers, as well as a newly developed in-house single-die interconnection process based on Anisotropic Conductive Film (ACF). The fine-pitch bump-bonding process is qualified with hybrid assemblies from a recent bonding campaign at Frauenhofer IZM. Individual CLICpix2 ASICs with 25 µm pixel pitch were bump-bonded to active-edge silicon sensors with thicknesses ranging from 50 µm to 130 µm. The device characterisation was conducted in the laboratory as well as during a beam test campaign at the CERN SPS beam-line, demonstrating an interconnect yield of about 99.7%. The ACF interconnect technology replaces the solder bumps by conductive micro-particles embedded in an epoxy film. The electro-mechanical connection between the sensor and ASIC is achieved via thermocompression of the ACF using a flip-chip device bonder. The required pixel pad topology is achieved with an in-house Electroless Nickel Immersion Gold (ENIG) plating process. This newly developed ACF hybridisation process is first qualified with the Timepix3 ASICs and sensors with 55 µm pixel pitch. The technology can be also used for ASIC-PCB/FPC integration, replacing wire bonding or large-pitch solder bumping techniques. This contribution introduces the two interconnect processes and presents preliminary hybridisation results with CLICpix2 and Timepix3 sensors and ASICs.

Electrochemical Express Analysis of Organic Additives in Lead-Free Wafer Level Packaging Plating Baths

Semiconductor packaging migrated from wire bond to flip chip level interconnect to meet size, weight and electrical performance requirements. Lead-free alloys for flip chip attachment has become a common material in electronics. Alloys containing Sn and Ag as well as pure Sn are the most common ones. The mechanical strength, wetting, and fatigue resistance of these alloys and pure Sn is either comparable or surpass lead contained alloys. Electroplating with lead-free alloys is the most desirable technique due to its low cost and usefulness in building fine pitch solder bumps [1].The new generation of lead free plating systems targeting faster deposition rates, better uniformity with-in die and longer bath life. The co-deposition of elements may be complicated by the large difference in the electrode potentials of tin and alloying metals (e.g. silver, bismuth). To produce uniform and dense deposits, these plating baths include organic additives that are typically separated for two groups with different functions: polarizers that significantly affect the plating rate and control the uniformity of deposit; and grain refiners [2]. For desired properties of deposit, the bath components must be kept within specific concentration ranges. In some cases, the analytical results for bath components should be available more frequently in order to provide feedback to dosing system [3]. To develop most accurate and repeatable analytical methods, the interactions between lead free plating bath components were previously investigated and understood [2]. That allowed to develop efficient analytical techniques for analysis of lead free plating bath components. However, faster analytical methods are required for control of high speed plating baths. The effect of changes in the concentration of organic components on the structure of deposit were studied more recently and will be reported in this work.When the speed of analyses increases, it is critical to keep reproducible state of all electrodes. Therefore, new regeneration method for electrodes was developed. For development of new express analytical methods, we utilized an electrochemical cell with three electrodes connected to a potentiostat/galvanostat. RDE working and counter platinum electrodes were used as well as Ag/AgCl double junction reference electrode. It has been found that multiple factors can reduce the speed of electrochemical analysis. One of the most potent parameters that affect speed of analysis was a scan rate. Fig. 1 shows the electrochemical responses of polarizer at different scan rates.Other parameters and steps of analysis were also evaluated for potential reduction the analysis time. This presentation will provide more information related to the electrochemical behavior of organic additives at specific conditions when the analysis is performed with different speed. Results for other bath components will be also presented. The concentration of inorganic components and silver complexing agent can be determined via non-reagent and virtually real time spectroscopic analytical methods. The presentation will be concluded with a discussion of analytical results for several organic additives at different concentration levels.

Temperature Dependence of Elastic–Plastic Properties of Fine-Pitch SAC 0307 Solder Joint Using Nanoindentation Approach

This paper highlights the advantages of using the nanoindentation approach over the conventional method for the mechanical characterization of components used in electronic packaging. The limitation of the conventional method has become more critical with the miniaturization of electronic packages, giving inadequate information regarding the mechanical properties of metallurgical interconnections. The load–displacement approach via nanoindentation was used in this study to determine the micromechanical properties of a fine-pitch solder joint subjected to aging for 1000 hours. This approach is more advantageous than tensile testing, as it focuses on the elastic behavior unlike that in conventional mechanical testing. The nanoindentation analysis results showed that the elastic–plastic behavior before failure can be assessed in a wide range of temperatures and thus help study the temperature dependence on the mechanical properties of fine-pitch solder joints. The characterization was done beyond the elastic range beforehand of conventional method. The modulus and hardness of the fine-pitch SAC 0307 solder joint decreased while its plastic and elastic behaviors became pronounced at higher aging temperatures. This implies that solder joints become weaker and less resilient with increasing temperature, at least for a duration of 1000 hours.

HV-SoP Technology for Maskless Fine-Pitch Bumping Process

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip-chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine-pitch solder bumping has been widely studied. In this study, high-volume solder-on-pad (HV-SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are , , and , respectively. It is expected that the HV-SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine-pitch flip-chip bonding.

Characterization and Estimation of Solder-on-Pad Process for Fine-Pitch Applications

Popular solder-bumping mechanisms such as electroplating and stencil printing suffer from either high process costs or technical limitations. A low-cost solder-on-pad (SoP) process has been developed to meet the requirements of fine-pitch solder bumping. This paper focuses on the characterization and estimation of the SoP process. To form a solder bump without soldering defects, optimum process conditions should be carefully designed. A model to estimate the bump volume and predict the bump height is suggested. By optimizing the composition of solder paste material called solder-bump-maker, and by adjusting the process conditions, Sn-Ag-Cu solder bumps with different heights are obtained. The experiments and analysis to understand the impact of parameters were based on test vehicles with 80 μm pitch size. Then, the measured heights of solder bumps are compared with the model to see how they fit the estimation. Finally, a similar process has been conducted to test vehicles with pitch sizes of 150 and 40 μm, to confirm the scalability of the SoP process in different pitch sizes.

Simulation and measurement of the flip chip solder bumps with a Cu-plated plastic core

With the aim to miniaturize and to reduce the cost, the increasing demand, regarding to advanced 3D-packages as well as high performance applications, accelerates the development of 3D-silicon integrated circuits. The trend to smaller and lighter electronics has highlighted many efforts towards size reduction and increased performance in electronic products. The radio frequency (RF) performances are limited by parasitic effects due to the resistor–inductor–capacitor (RLC) network, between the wire bond connections from the dies to the lead frame. The use of flip-chip bonding technology for very fine pitch packaging allows high integration and limits parasitic inductances. Electromigration (EM) and thermomigration (TM) may have serious reliability issues for fine-pitch Pb-free solder bumps in the flip-chip technology used in consumer electronic products. A possibility to extend the reliability is the use of plastic ball in the solder bumps. Bumps containing a plastic solder balls have an excellent reliability. Using a plastic ball with a low Young modulus, the solder hardness is moderated and the stress on a ball is relaxed. Due to this, the stress does not concentrate on the solder joint which prolongs the lifetime. In this investigation, the thermal–electrical–mechanical coupling of electromigration on bumps containing a plastic solder is studied.

Stencil printing behavior of lead-free Sn-3Ag-0.5Cu solder paste for wafer level bumping for Sub-100 μm size solder bumps

Stencil printing for flip chip packaging using fine particle solder pastes is a low cost assembly solution with high throughput for fine pitch solder joint interconnects. The manufacturing challenges associated with both solder paste printing increases as electronic device size decreases due to trend of miniaturization in electronic components. Among multiple parameters, the two most important stencil printing parameters are squeegee pressure and printing speed. In this paper, the printing behavior of Pb free Sn-3Ag-0.5Cu solder paste with a particle size distribution of 2–12 μm for wafer level bumping using a stencil printing method (stencil opening dimension −30 μm) was evaluated by varying the printing speed and squeegee pressure to fabricate solder bumps with a sub 100 μm size. The optimal squeegee pressure and print speed for the defect free printing behavior and fairly uniform size distribution of reflowed paste were found to be 7 kgf and 20 mm/s, respectively. The average size of the reflowed printed paste decreased with the increasing squeegee pressure.

Study of Intermetallic Growth and Kinetics in Fine-Pitch Lead-Free Solder Bumps for Next-Generation Flip-Chip Assemblies

With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 μm to 150 μm. With this reduction in pitch size, and thus in bump height and diameter, the interaction between die pad metallurgy and substrate pad metallurgy becomes more critical due to the shorter diffusion path and greater stress. Existing literature has not addressed such metallurgical interaction in actual fine-pitch flip-chip assemblies. This work studies intermetallic growth and kinetics in fine-pitch lead-free solder bumps through thermal aging of flip-chip assemblies. Based on this study, it is seen that Ni from the die pad diffuses to the substrate pad region and Cu from the substrate pad diffuses to the die pad region, thus the resulting intermetallic compounds at the die and substrate pad regions are influenced by the other pad as well. Such cross-pad interaction is much stronger in fine-pitch solder bumps with smaller standoff height. It is seen that the die pad region contains Ni3P and (Cu,Ni)6Sn5 after thermal aging, while the substrate pad region contains Cu3Sn and (Cu,Ni)6Sn5. By digitally measuring the thickness of the interfacial phases, the kinetics parameters and the activation energy were calculated for the growth of (Cu,Ni)6Sn5 on the substrate side. The Cu diffusion coefficient through the intermetallic compound (IMC) layer was found to be 0.03370 μm2/h, 0.1423 μm2/h, and 0.4463 μm2/h at 100°C, 125°C, and 150°C, respectively, and the apparent activation energy for the growth of compound layers was 67.89 kJ/mol.

Creep and Mechanical Properties of Cu6Sn5 and (Cu,Ni)6Sn5 at Elevated Temperatures

Cu6Sn5 is the most common and important intermetallic compound (IMC) formed between Sn-based solders and Cu substrates during soldering. The Cu6Sn5 IMC exhibits significantly different thermomechanical properties from the solder alloys and the substrate. The progress of high-density three-dimensional (3D) electrical packaging technologies has led to increased operating temperatures, and interfacial Cu6Sn5 accounts for a larger volume fraction of the fine-pitch solder joints in these packages. Knowledge of creep and the mechanical behavior of Cu6Sn5 at elevated temperatures is therefore essential to understanding the deformation of a lead-free solder joint in service. In this work, the effects of temperature and Ni solubility on creep and mechanical properties of Cu6Sn5 were investigated using energy-dispersive x-ray spectroscopy and nanoindentation. The reduced modulus and hardness of Cu6Sn5 were found to decrease as temperature increased from 25A degrees C to 150A degrees C. The addition of Ni increased the reduced modulus and hardness of Cu6Sn5 and had different effects on the creep of Cu6Sn5 at room and elevated temperatures.

Wafer Bumping, Assembly, and Reliability of Fine-Pitch Lead-Free Micro Solder Joints for 3-D IC Integration

In this investigation, Cu-Sn lead-free solder microbumps on 10-μm pads with a 20-μm pitch are designed and fabricated. The chip size is 5 × 5 mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but to still achieve good plating uniformity. With the current process, the undercut is less than 1 μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder microbumped chip is bonded on an Si wafer using chip-to-wafer bonding technique. Furthermore, the microgap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips without the underfill is measured and it exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, scanning acoustic tomography analysis, and cross-section with scanning electron microscopy analysis. The stacked ICs are evaluated by reliability (thermal cycling) test (-55 to 125°C). Finally, ultrafine-pitch (5-μm pads on a 10-μm pitch) lead-free solder microbumping is explored.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Advanced Substrate Applied Fluxing Underfill for Bonding of Fine Pitch Solder Capped Cu Pillars to Oxidized Cu Substrates

Underfill solutions for fine pitch flip chip assemblies is an active area of development. Non-conductive films (NCF) and pastes (NCP) have shown great potential in bridging the gap between no-flow and capillary underfills for improving the reliability of fine pitched devices. But NCFs and NCPs require costly passivated pad finishes (e.g. Au, Sn, Ni, OSP) or careful substrate handling for proper solder joint formation. In this paper, we will describe a new class of underfill material that benefits from the growing trend of using thermal compression bonding as a cost effective alternative to mass reflow based underfilling processes (e.g. capillary and no-flow). This material is a fluxing NCP that is useful for a wide variety of fine pitch substrates, including low cost Cu. The material we will demonstrate contains many advanced features: high filler loading, strong flux activity, long work life, off-tool pre-dispense, low stress, high Tg, high modulus and rapid cure. The all-in-one underfill demonstrated in this paper is applied by using a screen printing process, where the material is applied to all of the chip sites in one step achieving excellent application efficiency and wetting/conformity to the substrate. The substrate is glass, containing a 4x4 array of die sites. Each of the die sites are 5x5mm in size with a full area array of 2501 Cu pads (50um pads on 100um pitch) that are pre-oxidized for 1h at 175C in air prior to printing (to simulate a dehydration bake). This transparent substrate was chosen to show the robust nature of the underfill for fluxing, stability and void-free placement/cure. Images of the substrate, before and after chip bonding will be given, along with cross sections. Details of the material properties will also be discussed.

Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects

Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper. Chip stacking result of the Si interposer and the top Si die is also presented. TSVs with 25 μm in pitch and aspect ratio higher than 10 are etched with BOSCH process. To avoid difficulties in wetting the sidewall of the TSVs, bottom-up plating method is used to fill the TSVs with Cu. In order to fill the TSVs from bottom, the TSVs are first sealed from the bottom by plated Cu with plating current of 1 A. The plated Cu is used as a seed layer and bottom-up plating is then conducted with plating current of 0.1 A. Good filling without voids or with only tiny voids has been achieved. Electroless nickel/immersion gold is plated on top of the TSVs as under bump metallurgy pads. On the top Si die, Cu pillars/Sn caps with 16 μm in diameter and 25 μm in pitch are fabricated with electroplating method. After chip stacking, interconnections are formed between them through the solder microbumps and the TSVs.

Improving the fine-pitch stencil printing capability using the Taguchi method and Taguchi fuzzy-based model

This paper presents industrial applications for improving the capability of the fine-pitch stencil printing process (SPP) based on the DMAIC framework and using Taguchi-based methodologies. SPP is widely recognized as the main contributor of soldering defects in a surface mount assembly (SMA). An inadequate volume of solder paste deposition or poor printing quality can cause soldering defects and lead to significant reworking and repairing costs. In practice, both the desired amount of solder paste volume (quantitative index) and printing quality (qualitative index) are preferably used to monitor the SPP for the reduction of soldering defects during the statistical control process (SPC), particularly for a fine-pitch solder paste printing operation. To continuously improve SPP capability, the DMAIC framework is followed and Taguchi-based methodologies are proposed under the considerations of single characteristic performance index (SCPI) and multiple characteristic performance indices (MCPI). The SCPI is optimized using the conventional Taguchi method. Then, a Taguchi fuzzy-based model is developed to optimize the SPP with the MCPI property. Optimizing a multi-response problem by the Taguchi method involves the engineer's judgment which tends to increase the degree of uncertainty. The performance of these two approaches is compared through the process capability metric, and the material and factors significantly affecting the fine-pitch SPP performance are reported.

Quality and Reliability of 3D TSV Interposer and Fine Pitch Solder Micro-bumps for 28nm Technology

Silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. Furthermore, providing high wiring density interconnections and improved electrical performance are the reasons TSV interposer has emerged as a good solution and getting significant industry attention. High density three dimensional (3D) interconnects formed by high aspect ratio through silicon via (TSV) and fine pitch solder micro bumps are presented in this paper. Different design/material related factors are evaluated during this study in order to yield high aspect ratio void-free TSV copper via and reliable micro-bumps. Quality and reliability of copper TSV and micro-bumps are monitored in-situ during the process. This paper presents some of the quality and reliability results as well as micro-bump and TSV resistance data. Furthermore, bake and thermal-cycling measurements are presented to insure reliability of the design and the material selected for the 28nm technology TSV interposer FPGA.

Wafer Bumping and Characterizations of Fine-Pitch Lead-Free Solder Microbumps on 12” (300mm) wafer for 3D IC Integration

In this study, the wafer bumping and characterization of fine-pitch lead-free solder microbumps on 300mm wafer for 3D IC integration are investigated. Emphasis is placed on the Cu-plating solutions (conformal and bottom-up). Also, the amount of Cu and solder (Sn) volumes is examined. Furthermore, characterizations such as shearing test and aging of the microbumps are provided and cross sections/SEM images of the microbumps before and after test are discussed. Finally, the process windows of applying the conventional electroplating wafer bumping method of the ordinary solder bumps to the microbumps are also presented.

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

Electromigration and Thermomigration in Pb-Free Flip-Chip Solder Joints

Pb-free solders have replaced Pb-containing SnPb solders in the electronic packaging industry due to environmental concerns. Both electromigration (EM) and thermomigration (TM) have serious reliability issues for fine-pitch Pb-free solder bumps in the flip-chip technology used in consumer electronic products. We review the unique features of EM and TM in flip-chip solder bumps, emphasizing the effects of current crowding and Joule heating. In addition, the challenges to a better understanding of EM and TM in Pb-free solders are discussed. For example, the anisotropic nature of Sn microstructure in Pb-free solders can enhance the dissolution rates of Ni and Cu in solders driven by EM and TM.

Interfacial reaction and joint reliability of fine-pitch flip-chip solder bump using stencil printing method

This study was focused on the formation and reliability evaluation of solder joints with different diameters and pitches for flip chip applications. We investigated the interfacial reaction and shear strength between two different solders (Sn–37Pb and Sn–3.0Ag–0.5Cu, in wt.%) and ENIG (Electroless Nickel Immersion Gold) UBM (Under Bump Metallurgy) during multiple reflow. Firstly, we formed the flip chip solder bumps on the Ti/Cu/ENIG metallized Si wafer using a stencil printing method. After reflow, the average solder bump diameters were about 130, 160 and 190 μm, respectively. After multiple reflows, Ni 3Sn 4 intermetallic compound (IMC) layer formed at the Sn–37Pb solder/ENIG UBM interface. On the other hand, in the case of Sn–3.0Ag–0.5Cu solder, (Cu,Ni) 6Sn 5 and (Ni,Cu) 3Sn 4 IMCs were formed at the interface. The shear force of the Pb-free Sn–3.0Ag–0.5Cu flip chip solder bump was higher than that of the conventional Sn–37Pb flip chip solder bump.