Fine-grained Reconfigurable Architecture Research Articles

A framework for high-level simulation and optimization of fine-grained reconfigurable architectures

Field Programmable Gate Arrays (FPGAs), due to their programmability, have become a popular design choice for control and processing blocks of modern-day digital design. However, this flexibility makes them larger, slower, and less power-efficient when compared to Application Specific Integrated Circuits (ASICs). On the other hand, ASICs have their own drawbacks, such as lack of programmability and inflexibility. One potential solution is specialized fine-grained reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designing a fine-grained reconfigurable architecture is a daunting task in itself due to lack of high-level design-flow support. This article proposes an automated design-flow for the system-level simulation, optimization, and resource estimation of generic as well as custom fine-grained reconfigurable architectures. The proposed framework is generic in nature as it can be used for both control-oriented and compute-intensive applications and then generates a homogeneous or heterogeneous reconfigurable architecture for them. Four sets of homogeneous and heterogeneous benchmarks are used in this work to show the efficacy of our proposed design-flow, and simulation results reveal that our framework can generate both generic and custom fine-grained reconfigurable architectures. Moreover, the area and power estimations show that auto-generated domain-specific reconfigurable architectures are 76% and 73% more area and power-efficient, respectively, than generic FPGA-based implementations. These results are consistent with the savings reported for manual designs in the literature.

Support of Superchannel Formats in Optical Networks With Legacy Services and Traffic Churn [Invited

The improved agility introduced at the electrical domain, via fast digital signal processing, and at the optical domain, enabled by coherent reception and fine-grained reconfigurable add-drop architectures, empowers optical communication systems with strong arguments to satisfy ever-growing bandwidth requirements. Superchannels are one of these arguments, but the exact network conditions in which this technology is going to be deployed are still a matter of discussion. Hence, this paper proposes to evaluate, from a networking perspective, how different factors can influence service satisfaction. The set of accounted factors includes different frequency grids, multiple client types, existence of legacy services, introduction of traffic churn, and others. The planning is done on a multiperiod basis with three reference topologies. The results obtained underline the importance of combining transmission formats with antagonistic properties (longer reach or higher spectral efficiency) to maximize the service adoption. When compared with purely incremental scenarios, traffic churn has a negative impact due to the associated spectrum fragmentation (which is further potentiated with fixed frequency grids). The presence of legacy services also leads to early capacity exhaustion. In addition, algorithmic options during the planning process, such as the spectrum assignment for legacy services and the demand ordering policy, are also shown to impair the network performance.

A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors

A fine-grained reconfigurable architecture based on double gate technology is proposed and analyzed. The logic function operating on the first gate of a double-gate (DG) transistor is reconfigured by altering the charge on its second gate. Each cell in the array can act as logic or interconnect, or both, contrasting with current field-programmable gate array structures in which logic and interconnect are built and configured separately. Simulation results are presented for a fully depleted SOI DG-MOSFET implementation and contrasted with two other proposals from the literature based on directed self-assembly.

System-level power-performance tradeoffs for reconfigurable computing

In this paper, we propose a configuration-aware data-partitioning approach for reconfigurable computing. We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-level power-performance tradeoffs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. For a certain group of streaming applications, we show that an efficient hardware/software partitioning algorithm is required when targeting low power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. We propose a design methodology that adapts the architecture and algorithms to the application requirements. The methodology has been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones