Fin Field Effect Transistor Technology Research Articles

Advantages, manufacturing processes and challenges of FinFET technology

Abstract As an emerging cutting-edge integrated circuit technology, Fin Field Effect Transistor (FinFET) has not only successfully broken through the limitations of the 22nm node since its development in 1998, but it still maintains considerable vitality and is developing into smaller sizes. As an improvement over traditional MOSFET technology, FinFET offers many technical advantages, which practically solve the challenges encountered by traditional MOSFET. The FinFET process technology is incompatible with planar MOSFET process technology. Moreover, since the development of Finfet technology, there have been many technical challenges. The first half of this article mainly introduces the differences and advantages between FinFET and traditional Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), and briefly outlines its manufacturing process. The second half explains the challenges and hopes on the development path of FinFET technology. I believe this article can provide a reference for integrated circuit designers when understanding FinFET technology, and provide guidance and reference for beginners.

Ultra-Efficient Low-Power Retinal Nano Electronic Circuit for Edge Enhancement and Detection Using 7 nm FinFET Technology

Ultra-Efficient Low-Power Retinal Nano Electronic Circuit for Edge Enhancement and Detection Using 7 nm FinFET Technology

Advancements And Applications of Finfet Technology in Modern Semiconductor Engineering

This comprehensive study presents an in-depth analysis of Fin Field-Effect Transistor (FinFET) technology, a significant innovation in semiconductor technology, focusing on its structural attributes, applications, and future prospects. FinFETs, characterized by their distinctive fin-like channels, are pivotal in overcoming the limitations of traditional MOSFETs, particularly in the context of device miniaturization. The paper begins by exploring the basic theory and structural characteristics of FinFETs, emphasizing their enhanced control over short channel effects and reduced leakage currents in scaled-down devices. Attention is then directed towards the integration of FinFET technology in Static Random-Access Memory (SRAM), detailing how FinFETs contribute to improved stability and efficiency in memory storage. Another crucial application discussed is in the biomedical field, where FinFETs have facilitated the development of advanced instrumentation amplifiers and sensitive sensors, marking a leap in medical electronics. The paper concludes by addressing the challenges encountered by FinFETs as fabrication approaches the 5-7nm scale, including their physical and structural limitations. It also highlights ongoing research in structural modifications and material innovations like Gate-All-Around FETs and alternative materials, underscoring the continued evolution and relevance of FinFET technology in the ever-advancing semiconductor industry.

A 0.75V 10nm FinField-Effect Transistor Based Hybrid Self Controlled PreCharge Free Content Addressable Memory for Low Standby Power Applications

ABSTRACT The switching speed and driving capability have been enhanced by scaling the transistor size to nanoscale. The limitations in using MOSFET are that the short channel effects such as leakage current, subthreshold voltage, etc. thereby the Complementary Metal Oxide Semiconductor (CMOS) scaling is challenging now.This leads to the emergence of multi-gate devices, such as Fin Field Effect Transistor (FinFET) and Double Gate FinFET (DG-FinFET), which reduces the short channel effect. Now, a days memory plays a vital role in Integrated Circuits (IC), so the size of it must be scaled down to reduce the overall leakage andinstead of CMOS an advanced MOSFET such as FinFET can be used to avoid SCE. The area of the memory Static Random Access Memory (SRAM) is reduced by eliminating the two-load transistor. The novel 4T SRAM is designed at 10 nm 0.75 v FinFET Technology and compared with 14 nm Technology that is inbuilt into content addressable memory (CAM) to reduce the power consumption of CAM. The results show that the proposed design improves on a voltage basis and the complexity of the circuit is reduced by about 23% in terms of transistor count compared with the other conventional techniques. The 10 nm FinFET Hybrid Self Controlled - PreCharge Free (HSCPF) CAM design is best-suitable for low-power applications.

Design and Performance Analysis of Logic Circuits using FinFET Technology

As the dimensions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) decreases, the short channel effect (SCE) becomes a dominating concern in VLSI. The Short channel effect causes an exponential increase in the leakage current. To reduce the SCE and hence leakage current, a new technology has been developed in recent years. In this recent technology a 3D multiple gate MOSFETs like FinFET (Fin Field Effect Transistor) has been developed which possess numerous advantages over conventional MOSFETs and has attracted many engineers and designers. FinFET is the new growing technology that works in the nm range to minimize short channel effects. Many companies (like Intel) have started using FinFET technology. This document is a review paper of current research on FinFET technology and discusses how it can be used in future to design new logic devices (like Adder, Comparator, MUX and De-MUX etc.) and memory devices. Various parameters of FinFET like reduced short channel effects, less leakage current, low power consumption, less propagation delay and less time delay are discussed. Various mathematical models and software (HSpice) were used to simulate power, delay, power delay product, average power dissipation and energy delay product. Thus, FinFET technology was designed to eliminate the problem of SCE by permitting transistors to be scaled down into sub 20nm range.

Improved Stability for Robust and Low-Power SRAM Cell Using FinFET Technology

In the current nanoscale regime, fin field effect transistor (FinFET) technology overcomes the limitations of metal oxide semiconductor field effect transistor (MOSFET) technology. Robust and low-power static random access memory (SRAM) design is a demanding task for memory designers, especially in the nanoscale regime. Therefore, this paper proposes a 10 transistor (10T)-based SRAM cell design using low-power FinFET technology. The proposed approach not only reduces the leakage current, but also improves cell stability in different states. The proposed SRAM cell is simulated and analyzed at a 10[Formula: see text]nm technology node using a multi-gate predictive technology model (PTM) for the transistors with a power supply of 0.7[Formula: see text]V. The comparison analysis is also presented with the existing designs. The read and write static noise margins, and SRAM electrical quantity matrix (SEQM) of the proposed SRAM cell are improved by 3.54×, 1.71× and 26.41×, respectively, compared with the conventional 6T (C6T) design. The reliability investigations and comparison of the proposed SRAM cell have been carried out using Monte Carlo simulations with [Formula: see text]% deviations in the process parameters. The reliability analysis shows that the proposed SRAM cell is less sensitive to process variations.

Design and analysis of Voltage Difference Transconductance Amplifier (VDTA) at FINFET CMOS technology

This paper proposes a FINFET (Fin Field Effect Transistor)-based Voltage Difference Transconductance Amplifier (VDTA). This paper aims to provide an amplifier that will enable VDTA to achieve its desired characteristics. The circuit proposed for FINFET-based VDTA operates with a bias current order of 150μA and a source voltage of 0.9V. The active element makes the amplitude electronically tuneable with bias current. The designed circuit was implemented in both GPDK 180nm technology and FINFET technology using the Cadence Virtuoso tool. Various factors, including technology node components and the operating voltage provided by FINFET VDTA structures, are compared. A Monte Carlo simulation is conducted for the suggested circuit, which dissipates 187.53μW of power. In comparison to the standard VDTA, it exhibits notably low power dissipation.

Mitigation of Critical Delay in the Carry Skip Adders Using FinFET 18nm Technology

In this paper optimization of full adder in 3-dimensional (3-D) using Fin Field Effect Transistor (FinFET) with Gate Diffusion Input (GDI) is proposed to optimize critical delay, power. FinFET technology is more suitable for below 10nm technology process. The major aim of this work is to indemnify significant factor in adder structure i.e. critical delay. Pipelining architecture is enforced to accomplish the objective with the aid of FinFET 18nm technology. The structure is optimized to get the minimum delay confinement. Suggested design needs less logic resources. The outcomes are validated using FPGA synthesis methods. By applying the FinFET technique, we developed adder topology yielding up to 90% performance improvement with respect to delay, power and area compared to the conventional adders. The simulation was carried out with low power cds ff mpt PDK. The study also includes a carry skip adder design for FPGA implementation.

Effect of temperature on heavy ion-induced single event transient on 16-nm FinFET inverter chains

The variations of single event transient (SET) pulse width of high-LET heavy ion irradiation in 16-nm-thick bulk silicon fin field-effect transistor (FinFET) inverter chains with different driven strengths are measured at different temperatures. Three-dimensional (3D) technology computer-aided design simulations are carried out to study the SET pulse width and saturation current varying with temperature. Experimental and simulation results indicate that the increase in temperature will enhance the parasitic bipolar effect of bulk FinFET technology, resulting in the increase of SET pulse width. On the other hand, the increase of inverter driven strength will change the layout topology, which has a complex influence on the SET temperature effects of FinFET inverter chains. The experimental and simulation results show that the device with the strongest driven strength has the least dependence on temperature.

A 16 nm FinFET circuit with triple function as digital multiplexer, active-high and active-low output decoder for high-performance SRAM architecture

This paper presents a fin field-effect transistor (FinFET)-based single circuit (FSC) used to realize an active-high output decoder (AHD), active-low output decoder (ALD) and digital multiplexer. Traversal of the input signal through a single transmission gate irrespective of the size of the FSC is unique to this proposed multiplexer. This new FSC architecture uses an equal number of n-FinFET and p-FinFET devices, requiring few transistors compared with complementary metal oxide semiconductor designs. Three novel circuits are created using various logic styles following the same architecture. This FSC is compared with these similar circuits and, on average, the results for power dissipation and delay in the worst case show that this FSC is better by 14% and 18%, respectively. A FSC is created and extensively simulated with 16 nm FinFET technology using Eldo software. All the circuits are designed for 0.75 V, 1 V and 1.25 V and are stimulated with multiple input frequencies. The proposed circuit is most suitable for row address decoders and column multiplexers of static random access memories.

Characterization of charge sharing induced by high LET heavy ions using inverter chains in a commercial bulk FinFET process

The inverter is one of the most important cell types in any standard cell library at each technology node, and it is also very important for single-event research. The distributions and cross-sections of single-event transients (SETs) and single-event multiple transients (SEMTs) were characterized using 14/16 nm bulk fin field-effect transistor (FinFET) inverters under heavy ion radiation. An inverter with double driving strength (INVX2) was used as an instantiate object to observe the SET and SEMT response. 181Ta with energies of 1891 GeV and 2000.5 MeV were used respectively in the experiments, of which the linear energy transfer (LET) values were 87.4 MeV cm2 mg−1 and 75.4 MeV cm2 mg−1. The test results indicated that: (a) the mean pulse widths of the SET and SEMT were less than 100 ps, and decreased with LET decreasing; (b) there was charge sharing between abutted INVX2 inverters placed horizontally, and the generation probability of SEMT induced by charge sharing was less than 1% even if the LET of heavy ion reached 87.4 MeV cm2 mg−1. The results were beneficial for a better understanding of SET and SEMT tolerance for inverters in FinFET technology.

Operational transconductance amplifier-based comparator for high frequency applications using 22 nm FinFET technology

<p><span>Fin field-effect transistor (FinFET) based analog circuits are gaining importance over metal oxide semiconductor field effect transistor (MOSFET) based circuits with stability and high frequency operations. Comparator that forms the sub block of most of the analog circuits is designed using operational transconductance amplifier (OTA). The OTA is designed using new design procedures and the comparator circuit is designed integrating the sub circuits with OTA. The building blocks of the comparator design such as input level shifter, differential pair with cascode stage and class AB amplifier for output swing are designed and integrated. Folded cascode circuit is used in the feedback path to maintain the common mode input value to a constant, so that the differential pair amplifies the differential signal. The gain of the comparator is achieved to be greater than 100 dB, with phase margin of 65°, common mode rejection ratio (CMRR) of above 70 dB and output swing from rail to rail. The circuit provides unity gain bandwidth of 5 GHz and is suitable for high sampling rate data converter circuits.</span></p>

Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology

Given their non-invasiveness and demonstrated effectiveness, power analysis attacks (PAAs) are concerning and to be accounted for in modern circuit design. That is especially relevant for technology-dependent verification of PAA countermeasure implementations. Prior art proposed various countermeasures against PAAs, including masking and hiding, voltage switching, noise injection, etc. Aside from the proven working principles of such countermeasures, it is important to understand that their effectiveness is primarily technology- and implementation-dependent. Hence, before deployment, especially for integrated circuits, such countermeasures require accurate circuit-level studies.This work investigates an industrial-grade 14 nm fin field-effect transistor (FinFET) technology at design-time in the context of PAAs. We leverage device-level measurement data from Intel high-volume manufacturing processes, build up accordingly well-characterized standard-cell libraries, and utilize a commercial-grade computer-aided design (CAD) flow for PAA evaluation at design-time. Our study is focused on (1) the effectiveness of voltage switching as a countermeasure, (2) the advanced encryption standard (AES) cipher as a representative circuit, and (3) the correlation power analysis (CPA) as an attack framework. We show that, to improve the resilience against the CPA attack in particular and to lower information leakage in general, specific voltage configurations are more promising than others for the 14 nm FinFET technology.

重离子在14-nm FinFET SRAM器件引起的单粒子翻转

The characteristic of single-event upset(SEU) in a 14-nm bulk fin field-effect transistor (FinFET) static random access memory(SRAM) is investigated by heavy-ion experiments. The linear energy transfer(LET) threshold 0.1 MeV/(mg/cm2) is obtained by fitting the SEU cross-section using the Weibull function. The contribution of multiple-bit upset(MBU) is investigated. The results show that when the LET is equal to 40.3 MeV/(mg/cm2), greater than 95% of SEU comes from the MBU. Additionally, the SEU cross-section of the FinFET SRAM presents anisotropies for incident angles associated with the fin direction. This research has a certain kind of guiding role in designing of radiation-hardened complementary metal-oxide semiconductor(CMOS) integrated circuits(ICs) based on FinFET technology.

Design optimization of nanoscale electrothermal transport in 10 nm SOI FinFET technology node

A flexible framework is obtained for enhancing both the thermal and electrical performance of fin field-effect transistor (FinFET) technology. Investigation of the nanoscale heat conduction within a short-channel field-effect transistor can be regarded as an emerging challenge related to future-generation transistors. In this work, we report the electrothermal transport in a 10 nm silicon-on-insulator (SOI) FinFET based on the dual-phase-lag model and modified drift-diffusion motions. We found that electron mobility decreases along the channel due to carrier confinement under higher electric field. In addition, the surface detection temperature indicates that the self-heating process is localized between the source and drain region. As promising results, high-κ metal-oxide and lower thermal boundary resistance can optimize the nanoscale heat transport in the SOI FinFET device.

A 4:1 multiplexer using low-power high-speed domino technique for large fan-in gates using FinFET

PurposeThis paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis.Design/methodology/approachIn the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE.FindingsThe proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques.Originality/valueThe research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

Three-dimensional imaging of integrated circuits with macro- to nanoscale zoom

The imaging of integrated circuits across different length scales is required for failure analysis, design validation and quality control. At present, such inspection is accomplished using a hierarchy of different probes, from optical microscopy on the millimetre length scale to electron microscopy on the nanometre scale. Here we show that ptychographic X-ray laminography can provide non-destructive, three-dimensional views of integrated circuits, yielding both images of an entire chip volume and high-resolution images of arbitrarily chosen subregions. We demonstrate the approach using chips produced with 16 nm fin field-effect transistor technology, achieving a reconstruction resolution of 18.9 nm, and compare our results with photolithographic mask layout files and more conventional imaging approaches such as scanning electron microscopy. The technique should also be applicable to other branches of science and engineering where three-dimensional X-ray images of planar samples are required. A technique that combines X-ray ptychography with laminography can provide three-dimensional views of integrated circuits, yielding both images of entire chip volumes and high-resolution images of arbitrarily chosen subregions, and is applicable to any imaging problem where the samples are planar.

3D Investigation of 8-nm Tapered n-FinFET Model

The miniaturization has become a key word for advanced integrated circuits over the last few years. It is within this context that the fin field effect transistor (FinFET) has appeared as a suitable technology to enable in every single chip to contain more million transistors. This paper proposes a numerical investigation of the influence of the gate length, drain/source doping concentrations, and gate work function on the output properties of 3D tapered FinFET technology by using Silvaco TCAD tools. The simulation results show that decreasing the gate length from 14 nm to 6 nm, the leakage current enhances dramatically and increasing the metal gate work function from 5.33 eV to 5.70 eV has affected transistor response time and the on-current, but in parallel, the leakage current increase affecting the transistor efficiency. The subthreshold slope (SS) and transconductance (gm) are quite constant for all work function levels. This variation leads to determine the optimal metal gate work function of about 4.50 eV. The paper reports recent findings and some guidelines to achieve the following results: a threshold voltage (Vth) of 0.216 V, a subthreshold slope of 68.54 mV/dec, a transconductance of 315.7 μA/V, an on-current (Ion) of 103.75 μA, and an off-current (Ioff) of 2.51 nA with a fixed gate length (Lg) of 8 nm, a top fin-width (FWT) of 3 nm, a bottom fin-width (FWB) of 6 nm, and a fin-height (FH) of 50 nm, which are close to those reported in other research studies.

A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology

In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9[Formula: see text]V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–[Formula: see text] higher compared to different existing techniques in FinFET SG mode and is 1.42–[Formula: see text] higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to [Formula: see text] higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.

Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology.

In this work, we present a novel pH sensor using efficient laterally coupled structure enabled by Complementary Metal-Oxide Semiconductor (CMOS) Fin Field-Effect Transistor (FinFET) processes. This new sensor features adjustable sensitivity, wide sensing range, multi-pad sensing capability and compatibility to advanced CMOS technologies. With a self-balanced readout scheme and proposed corresponding circuit, the proposed sensor is found to be easily embedded into integrated circuits (ICs) and expanded into sensors array. To ensure the robustness of this new device, the transient response and noise analysis are performed. In addition, an embedded calibration operation scheme is implemented to prevent the proposed sensing device from the background offset from process variation, providing reliable and stable sensing results.