A method for constructing a fixed coefficient FIR filter with only adders without multipliers is proposed in this paper. Using past techniques, FIR filters can be constructed with only adders and adders used can be reduced by shared operations. However, since registers of an order greater than the order of the transfer function are needed if shared operations are performed without imposing certain limitations, the number of gates cannot be reduced in a configuration using many registers with a reduced number of adders. Thus, in this paper, a method for designing FIR filters constructable with a minimal number of registers without requiring new registers, using only adders and not using multipliers, is investigated. In addition, a method for improving the operational speed considering the order of addition is studied. In addition, a design algorithm for FIR filters which can be used to restrict the maximum delay time and the maximum number of adder level is proposed. © 2000 Scripta Technica, Electron Comm Jpn Pt 3, 83(5): 23–31, 2000