This work presents an optimized Field-Programmable Gate Array (FPGA) implementation of an Echo State Network (ESN), a type of Recurrent Neural Network (RNN), to predict the chaotic signal of the Lorenz system. The focus is on executing AI models efficiently on resource-limited devices like those in the Internet of Things (IoT). In contrast to previous state-of-the-art works that used the tanh activation function (which required complex hardware approximations), this proposal employs the simpler ReLU function. This choice eliminates the need for approximations and, when combined with an optimized network architecture, enables a drastic reduction in resource usage. Specifically, the optimization achieved three key reductions: a) The reservoir size, decreased from 50 to 3; b) The connectivity matrix, transitioned from a dense matrix of 2500 values to a diagonal matrix with only 3 non-zero values; and c) Precision, reducing the operational bit-width from 32 to 23 bits. As a result, the optimized ESN is significantly more efficient on FPGA hardware, successfully reducing utilized resources while simultaneously achieving improved performance compared to prior state-of-the-art implementations. • We apply a Network Search Architecture with Echo State Networks (ESN) to predict the chaotic signal of Lorenz system. • A very small network with a size of 3 neurons in the reservoir is ob- tained. • An implementation of the obtained ESN in FPGA is presented.

Sleep stage classification is critical for diagnosing and managing disorders like sleep apnea and insomnia. However, conventional methods like polysomnography are costly and impractical for long-term, home-based monitoring. This study presents an energy-efficient approach for detecting four sleep stages (wake, rapid eye movement (REM), light sleep, deep sleep) using a single-lead electrocardiogram (ECG) signal. We evaluate various machine learning and deep learning models, introducing two windowing strategies: (1) a 5-minute window with 30-second steps for machine learning and (2) a 30-second window with 10-second steps for deep learning, enabling 10-second temporal resolution for real-time predictions. While deep learning models like MobileNet-v1 achieve high accuracy (92%) and F1-score (91%), their energy demands make them unsuitable for wearables. To address this, we design SleepLiteCNN, optimized for ECG-based sleep staging, achieving 89% accuracy and 89% F1-score while minimizing energy use. Applying 8-bit quantization further reduces energy consumption to 5.48 μJ per inference, with 90% accuracy and F1-score. Additionally, field-programmable gate array (FPGA) deployment shows significant reductions in resource usage. This approach provides a practical, energy-efficient solution for continuous ECG-based sleep monitoring in resource-constrained wearable devices.

The development and implementation of scalable and efficient security solutions have become a critical area of focus in cybersecurity research and practice. This trend is receiving more attention lately due to the increasing frequency and sophistication of cyber threats to Internet of Things (IoT) networks. This paper proposes a novel cryptographic co-processor architecture based on RISC-V, designed to offer both high efficiency and flexibility for IoT applications. The design introduces a generic interface for cipher blocks, supports parallel execution of cipher operations, and avoids custom modifications to the RISC-V instruction set architecture. The proposed design extends the RISC-V architecture without new instruction sets to support AES-128 and SHA-256 operations, demonstrating its capabilities through these ciphering blocks. The new processor architecture ensures efficient data transfers between memory and cipher units, without delaying the processor pipeline, by utilizing Memory-Mapped I/O (MMIO) and Direct Memory Access (DMA) modules to optimize data handling. The proposed design is implemented and verified on the Xilinx ZCU-102 FPGA board using the Vivado 2022.2 tool. The proposed design achieves throughput rates of 8.2 Gbps for the AES-128 cipher block and 482 Mbps for the SHA-256 cipher block, operating at a relatively low system clock frequency of 64 MHz. The throughput is calculated based on the core cycle count of each algorithm, as this metric is commonly adopted in the literature. Nevertheless, the total end-to-end cycles of the proposed design equal the core cycles plus the serializer and deserializer cycles. The cycle count of the serializer/deserializer depends only on the processor's data bus width. Also, the total power consumption of the proposed design is 1.575 watts. Achieving such high throughput at this reduced frequency is significant as it helps designers better minimize the power consumption, thereby enhancing the overall energy efficiency and performance of the system.

To develop an integrated system for tendon injury repair that combines electrical stimulation, drug iontophoresis, and electromyography (EMG) monitoring, and validate it in a rat Achilles tendon injury model. A flexible 16-channel acquisition and stimulation system was constructed based on field programmable gate array. The system had a sampling rate ranging from 250 SPS to 16 kSPS with a resolution of 5 μV, and the stimulation current was 2.55 mA with a resolution of 10 nA, enabling synchronous and stable stimulation and signal monitoring. Fifteen Sprague-Dawley rats with induced Achilles tendon injuries were randomly allocated to three groups ( n=5): blank control, electrical stimulation, and drug iontophoresis groups. The Achilles tendon injury model was established by injecting typeⅠcollagenase solution into the Achilles tendon of right hind limb. At 3 days after modeling, the electrical stimulation group and drug iontophoresis group received corresponding interventions with the self-developed system for 2 consecutive weeks, and aspirin was delivered via iontophoresis in the latter group. No treatment was performed in the blank control group. The survival status and limb motor function of rats were observed, and EMG signals were recorded throughout the intervention. Gross observation and histological examination (HE staining and Sirius red staining) of Achilles tendons were performed at 2 and 4 weeks since the initiation of intervention to evaluate the repair effect. All rats survived until the scheduled experimental time point. All animals presented postoperative limping, which recovered spontaneously within 2 weeks without obvious intergroup difference. EMG results demonstrated that all groups underwent a consistent three-stage recovery process, namely compensatory activation, collagen remodeling, and functional recovery. The electrical stimulation group exhibited the mildest EMG fluctuations, whereas the drug iontophoresis group showed the most significant early muscular compensatory activation. Obvious differences in EMG characteristics between the injured and contralateral healthy sides were observed in the early stage, which gradually diminished and finally achieved synchronization with the progression of tendon repair. The support vector machine (SVM) achieved a classification accuracy of 85.8% for recovery stage identification. Gross observation and histological examination revealed that both intervention groups displayed milder peritendinous adhesion and better tendon luster compared with the blank control group, and achieved superior tendon repair outcomes. The integrated system proves to be effective for both the assessment and intervention of tendon injury repair. EMG signals can reliably distinguish between different stages of Achilles tendon recovery. Furthermore, both electrical stimulation and iontophoretic drug delivery promote repair by effectively regulating collagen remodeling and modulating compensatory muscle activation patterns.

Autonomous driving offers a promising way to tackle the rising number of fatalities from traffic accidents. An autonomous vehicle includes many features, but the ability to detect pedestrians is crucial, challenging, and relevant to various real-time situations like surveillance, tracking people, and monitoring. Accurately identifying pedestrians is difficult because they can appear in different shapes, positions, and postures. They can wear various types of clothing and sometimes be partially hidden or blend in with nearby objects. This paper focuses on the real-time detection of pedestrians for self-driving cars using a popular hardware platform: The field programmable gate array (FPGA), Ultra 96 v2. The study implements a method for pedestrian detection based on a histogram of oriented gradients (HOG) combined with a support vector machine (SVM) classifier to recognize individuals on the FPGA board, leveraging high-level synthesis (HLS) tools. The effectiveness of the system has been tested on both still images and live video. The results show that advanced FPGA boards like the Ultra 96 v2 significantly improve performance metrics. The system operates at a clock frequency of 150 MHz while using less than half of the available resources and consuming around 2.5 W of power. Also, the system reports the pedestrian detection accuracy close to 95% and other efficient metrics for detection evaluation, like precision (78.6%), recall (88.3%), and F1 Score (83.1%). In summary, the developed system can detect pedestrians in real-time and has the potential to significantly improve the development of a smart and safe transportation environment.

This paper presents a methodology for the remaining useful life (RUL) prediction in power electronic converters based on the health monitoring of semiconductor devices and DC capacitor(s). The primary components considered are Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) and aluminum electrolytic capacitors (AECs). The proposed methodology leverages long-term component characterization under accelerated aging testing in a laboratory setup. A statistical approach based on uniform probability density functions (PDFs) is utilized to estimate the system-level probability of survival under the desired operating conditions. Given that the PDFs and system-level probability calculations involve taking integrals and other complex operations, a machine learning (ML)-assisted model is utilized to reduce the computational burden on the controller units in power electronics converters. A neural network (NN) is used to process the experimentally derived degradation data and the extracted PDFs for arriving at a simple model presented by a few matrices that can even be deployed on modern microcontrollers or field-programmable gate arrays (FPGAs) for in-situ implementation. Experimental results obtained using a laboratory-scale prototype show that the proposed data-driven approach can achieve accuracy levels higher than 99% in predicting the time evolution between degradation checkpoints under accelerated thermal cycling conditions. This validation confirms the model's consistency with established statistical approaches across the full reliability range (T99-T01). Hence, this approach can identify aged or potentially failing converters in-situ and avoid early decommissioning, thereby extending the operational life.

Approximate computing has emerged as an effective approach for reducing power consumption in error-tolerant applications, particularly in resource-constrained Internet of Things (IoT) edge systems. However, most existing approximate multipliers employ static approximation levels, limiting their ability to adapt to dynamically varying energy conditions at runtime. This paper proposes a Dynamic Energy-Aware Linear Mapping Multiplier (DEA-LMM) that integrates runtime energy monitoring with adaptive approximation control. By incorporating energy-aware normalization, leading zero detection, and configurable multi-level compensation mechanisms, the proposed architecture enables dynamic adjustment of the accuracy-energy trade-off according to the available energy budget. To further improve energy efficiency, an enhanced architecture, referred to as Dynamic Energy-Aware Linear Improved Mapping Multiplier (DEA-ILMM), is introduced by extending the baseline design with energy-aware dynamic truncation. This mechanism adaptively configures operand precision at runtime, reducing power and area overhead while maintaining bounded approximation error. Both designs preserve compatibility with fixed-point linear mapping formulations and avoid modifications to the core multiplier structure. Comprehensive experimental evaluations on Field-Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) platforms, including realistic solar-energy-harvesting traces, demonstrate that the proposed DEA-LMM and DEA-ILMM achieve up to 70% power savings in aggressive modes and an additional 15-25% energy reduction through runtime dynamic adaptation compared with state-of-the-art static approximate multipliers, while preserving acceptable accuracy across dynamically varying energy budgets. Real-world validation on an ESP32-C3-based solar-powered sensor node further confirms 47% energy reduction with negligible accuracy loss in practical environmental monitoring tasks. These results indicate that the proposed designs provide a flexible and effective solution for energy-adaptive computation in modern edge systems.

The dawn of Reconfigurable Intelligent Surfaces (RIS) promises to revolutionize wireless communication by enabling dynamic control of the propagation of electromagnetic waves. However, the practical implementation of RIS demands sophisticated configuration strategies to unlock their full potential. This paper presents a hardware implementation of a Deep Learning (DL) approach to the configuration of RIS, addressing both the complexity and efficiency of the configuration process. A deep learning-based algorithm, designed to optimize the phase shifts of RIS elements and shown to enhance signal quality and system performance, is implemented on two dedicated hardware platforms based on Field-Programmable Gate Arrays (FPGA), which leads to real-time processing and adaptability. This approach leverages the inherent parallelism of FPGAs to accelerate the computationally intensive tasks associated with deep learning inference. As a matter of fact, it is possible to achieve more than 18.000 configurations per second, thus ensuring rapid and efficient RIS configuration with a novel approach within this field. • FPGA implementation of hardware accelerators of CNNs for RIS configuration on the edge. • CNN tailored for FPGA-based acceleration. • Resource and performance analysis of several architectures on Altera® and AMD FPGA devices. • Novel approach to computation of RIS configurations.

Image and signal processing workloads are widely deployed on Graphics Processing Units (GPUs) for high throughput and on Field-Programmable Gate Arrays (FPGAs) for hardware specialization and energy efficiency. Soft GPU overlays on FPGAs aim to combine these advantages, yet existing solutions often depend on fixed hard processors or impose platform constraints that limit portability. This work extends a popular open-source soft GPGPU overlay to integrate a soft RISC-V control plane and enable compatibility with High-Bandwidth Memory (HBM2). The resulting system can be instantiated on FPGA boards without a hard ARM processor, improving portability, simplifying system integration, and broadening deployability. Across representative image and signal processing kernels, the soft GPGPU achieves geometric-mean speedups of 114.60 × over a scalar soft RISC-V core and 19.72 × over a hard ARM core, demonstrating substantial performance benefits while retaining FPGA reconfigurability. HBM2 integration further benefits bandwidth-sensitive workloads by increasing sustained throughput and reducing the performance bottlenecks associated with off-chip memory access. Collectively, these results indicate that GPU-like programmability and performance can be delivered on reconfigurable platforms without reliance on hard CPU subsystems, providing a portable and scalable foundation for embedded vision and DSP acceleration.

Neutron-gamma discrimination based on STFT-DFF model and FPGA implementation.

The next-generation of cryogenic neutrinoless double-beta decay experiments require increasingly fast readout in order to improve background discrimination. These experiments, operated as cryogenic calorimeters at ∼ 10 mK, are usually read out by high-impedance neutron transmutation doped (NTD) thermistors, which provide good energy resolution, but are limited by ∼ 1 ms response times. Superconducting detectors, such as transition-edge sensors (TESs) with a time resolution of ∼ 100 μs, offer superior timing performance over NTD semiconductor bolometers. To make this technology viable for an application to a thousand or more channels, multiplexed readout is necessary in order to minimize the thermal load and radioactive contamination induced by the readout. Frequency-domain multiplexing readout (fMUX) for TESs, previously developed at Berkeley Lab and McGill University, is currently in use for mm-wave telescopes with detector sampling rates in the order of 100 Hz. We demonstrate a new readout system, based on the McGill/Berkeley digital fMux readout, to satisfy the higher bandwidth and noise requirements of the next generation of TES-instrumented cryogenic calorimeters. Each multiplexing readout module comprises 10 superconducting resonators in the 1–5 MHz range and a DC superconducting quantum interference device (DC-SQUID), interfaced to high-speed field programmable gate array (FPGA)-based electronics for digital signal processing and low-latency SQUID feedback. The new readout samples detectors at 156 kHz, three orders of magnitude faster than its cosmology-oriented predecessor, and demonstrates a stable feedback bandwidth of 3 kHz in a real TES-based system.

Abstract Deep learning (DL) models require significant computational resources, making their deployment on edge devices with limited power and hardware capabilities challenging. Field-programmable gate arrays (FPGAs) provide an effective platform for accelerating such workloads because of their inherent parallelism and energy efficiency. This study investigates the impact of layer-wise parallelization levels, represented by folding coefficients, on the resource utilization and performance of FPGA-based DL accelerators, with a specific focus on convolutional (CONV) and fully connected (FC) layers. A LeNet-based accelerator model was implemented using the Xilinx FINN framework with W1A2 quantization (1-bit weights and 2-bit activations). Three folding coefficients, namely low (L), medium (M), and high (H), were defined for both the CONV and FC layers, yielding nine unique parallelization configurations. These accelerators were deployed on the PYNQ-Z1 platform and evaluated using the Fashion-MNIST dataset. A comprehensive evaluation quantifies key metrics, such as throughput (frames per second, FPS), resource utilization (look-up tables (LUTs), flip-flops (FFs), and block RAMs (BRAMs)), and power consumption. The results show that lower folding levels, corresponding to higher parallelism, significantly enhance the throughput, reaching up to 6809 FPS in the L-M and L-L configurations. This represents a 13-fold improvement over the baseline H-H configuration (C1) at the cost of increased resource usage. This study extends prior research on quantized neural networks (QNNs) by analyzing layer-specific parallelization strategies through adjustable folding factors and their effects on performance and resource trade-offs, offering valuable insights for optimizing FPGA-based deep learning (DL) inference in resource-constrained environments.

A vehicle-mounted radar system for quick tunnel inspection

We present a real-time anomaly detection framework for liquid argon time projection chambers (LArTPCs), targeting applications in particle physics experiments such as the Short Baseline Near Detector or the future Deep Underground Neutrino Experiment. These experiments employ detectors that generate and stream high-resolution but sparse images of neutrino and other particle interactions. Our approach utilizes anomaly detection with autoencoders, compressed through knowledge distillation, to enable the detection of anomalous signals in the data through efficient inference on resource-constrained hardware. The framework is targeted for deployment on computing platforms equipped with field-programmable gate arrays, GPUs, or CPUs, allowing low-latency selection of relevant activity directly from the raw detector data stream. We demonstrate that our approach is suitable for the detection and localization of anomalously “high-multiplicity” activity, and outline promising applications for LArTPC online data filtering and triggering.

Computationally expensive, high-accuracy detector simulations are a major bottleneck for many particle physics experiments such as those at the Large Hadron Collider (LHC) as well as those planned for future colliders. This challenge has motivated the development of fast generative machine learning based surrogates. We present a hardware-aware variational autoencoder model for fast calorimeter simulation that is designed specifically for field programmable gate array (FPGA) deployment, offering faster and lower power inference capability. Quantization aware training and other compression techniques are applied to respect the resource constraints of a single FPGA. The synthesized implementation of the VAE decoder achieves sub-millisecond latency, resulting in a substantial speed up compared to a traditional GPU implementation with only a small performance drop. This feasibility study demonstrates the potential of utilizing existing FPGA architecture at the LHC and other facilities for efficient offline computing using online resources.

Talkative Power Conversion (TPC), also known as switching-ripple communication (SRC), provides cost-effective data transmission for smart grids, DC microgrids, and automotive power systems, but it remains vulnerable to unauthorized access and data interception. This paper proposes an integrated TPC system embedding Advanced Encryption Standard 128 (AES-128) encryption directly into a binary frequency shift keying (FSK)-modulated DC-DC buck converter, eliminating external modems and security hardware. The key novelty is a converter-centric physical-layer co-design that seals plaintext within the converter controller and transmits only ciphertext ripple on the shared DC bus without external modem/security interfaces. Utilizing the converter's intrinsic switching ripple for data transmission, the buck converter transmits encrypted data using 61 kHz and 73 kHz switching frequencies, with a 24 kHz synchronization tone. Real-time encryption, modulation, demodulation, and decryption are implemented on a PYNQ-Z2 FPGA board. Experimental validation demonstrates secure, error-free data transmission with desired power quality, confirming the proposed method's practicality. The integrated FPGA-based solution significantly reduces system complexity and cost, ensuring robust protection against cyber threats in DC power distribution systems.

Advanced nanoscale devices are core components in modern aerospace systems. The on-orbit reliability of the devices faces challenges from Single Event Effects (SEEs) induced by high-energy particles in space. The ground-based irradiation testing is a critical method for predicting on-orbit performance. However, the ground test is an accelerated testing method. The influence of ion strike time intervals (i.e. ion flux) on the SEE sensitivity of advanced nanoscale devices is not yet fully understood. This problem can lead to inaccurate reliability assessment. In this work, the impact of ion strike time intervals on the Single Event Upset (SEU) has been investigated systematically in a 28 nm Static Random Access Memory based (SRAM-based) Field Programmable Gate Array (FPGA). The ground-based irradiation experiments were conducted using various heavy ions under well controlled ion flux levels. The experimental results definitively demonstrate that the device's SEU cross section increases significantly as the ion strike time interval decreases. It shows when the flux exceeds 1000 ions/(cm2·s), the cross section exhibits changes, while it remains unchanged at the flux below 1000 ions/(cm2·s). Moreover, the flux of 1000 ions/(cm2·s) is significantly lower than the typical flux used in SEE testing. This phenomenon was more pronounced at lower core voltages and higher Linear Energy Transfer (LET) values. The analysis reveals that the voltage drop induced by transient pulses from heavy ions is the primary physical mechanism that is responsible for the flux dependence. Furthermore, the physical mechanism of the experimental phenomena has been elucidated through Technology Computer-Aided Design (TCAD) and circuit-level simulations. Moreover, the mechanism is equally applicable to other advanced nanoscale devices. This finding provides an essential reference for accurate prediction of on-orbit failure rates of the advanced nanoscale devices.

Image-activated cell sorting (IACS) enables high-throughput cell classification by linking cellular morphology to physiology. While integrating advanced artificial intelligence (AI) can enhance the capture of subtle morphological heterogeneity, AI models inevitably introduce greater computational complexity when addressing complex problems, leading to increased analysis latency and latency instability. High latency implies longer chip lengths, while latency instability leads to incorrect sorting timing. To address this challenge, IACS can utilize field-programmable gate array (FPGA) as a stable, low-latency image analysis tool. Here, we developed a two-stage FPGA processing system for cellular data acquisition and real-time AI inference, utilizing the high-level synthesis (HLS) framework. By deploying a customized U-Net model on the AMD-Xilinx accelerator card and integrating hardware acceleration modules including activation function approximation and pixel-level convolution acceleration, we achieved a stable segmentation latency of 3.06 milliseconds (ms) at a 272 MHz clock frequency and delivered a processing throughput of up to 16,601 frames per second (fps). Using the morphological parameters obtained after segmentation, we successfully separated deformed HeLa cells from normal cells and distinguished colorectal cells, red blood cells, HeLa cells, and microspheres. This work provides IACS with a stable and low-latency image processing solution.

Autonomous driving perception demands low latency, high temporal resolution, and stringent hardware efficiency. While event-based spiking neural networks (SNNs) offer bio-inspired sparse computation, their deployment on edge field-programmable gate arrays (FPGAs) is obstructed by irregular execution patterns and temporal state storage overhead. To address this, we propose HAPQ, a unified hardware-aware pruning and quantization pipeline for compact event-based object detection. Starting from an end-to-end adaptive sampling SNN detector (EAS-SNN), HAPQ conducts hardware-aware configuration search within discrete digital signal processor (DSP) and block RAM (BRAM) budgets, applies single-instruction-multiple-data (SIMD)-aligned structured pruning for computational regularity, and jointly quantizes synaptic weights and membrane potentials via a shift-friendly fixed-point recurrence. Evaluation on the Prophesee Gen1 dataset and an FPGA accelerator shows that HAPQ improves detection accuracy from 0.284 to 0.425 in mean average precision () and achieves 0.722 . Hardware implementation reveals a reduction in lookup table (LUT) usage to 1680, complete DSP elimination, and a maximum operating frequency of 920.81 MHz at 0.630 W. These results confirm that effective temporal SNN deployment requires joint optimization of model architecture, state precision, and hardware-aligned workload organization.

Abstract Secure data obfuscation requires balancing perceptual transparency, computational efficiency, and architectural deployability. Conventional spatial-domain steganography achieves high capacity but lacks structural abstraction and hardware-oriented design. We introduce SteganoSNN, a neuromorphic steganographic framework that integrates spike-based temporal encoding with field programmable gate array (FPGA)-accelerated embedding for secure and energy-aware multimedia data hiding. Audio samples are transformed into spike-count regimes using a Leaky Integrate-and-Fire (LIF) spiking neuron model, followed by modulo-based symbol transformation and deterministic spike-index mapping. The spike-to-Spike Index (SI) abstraction decouples source symbols from embedded bit patterns, introducing a temporal encoding layer prior to least significant bit (LSB) embedding in red, green, blue, alpha (RGBA) images. The proposed system is implemented in Python using NEST and realised on a PYNQ-Z2 FPGA through a hybrid processing-system/programming-logic co-design. Post-implementation analysis reports total on-chip power consumption of approximately 1.41 W, with programmable logic contributing only a small fraction of overall energy usage. The proposed framework supports an embedding capacity of 8 bits per pixel (bpp) while maintaining high perceptual fidelity on the DIV2K 2017 dataset, achieving peak signal-to-noise ratio (PSNR) values between 40.4 dB and 41.35 dB and structural similarity index (SSIM) above 0.97. Real-time feasibility is demonstrated through detailed latency and throughput evaluation on full-High Definition (HD) images. Unlike purely LSB-based approaches, SteganoSNN introduces a neuromorphic temporal representation layer that enables hardware-efficient symbol abstraction without increasing embedding depth. The results establish spike-based encoding as a viable architectural paradigm for secure and resource-aware steganography in edge-Artificial Intelligence (AI) and embedded systems.