Field Programmable Gate Array Prototype Research Articles

Do Not Trust, Verify: A Verifiable Hardware Accelerator for Matrix Multiplication

In this letter, we propose VeritAcc, a novel application that enables secure integration of an untrusted third-party matrix multiplication (MM) hardware accelerator in a system-on-chip containing a trusted general purpose processor. Our solution builds upon the theory of interactive proof (IP) protocols to enable run time verification of each computation executed on the untrusted accelerator and formally guarantees that any incorrect results are detected with high probability. Our novel optimizations in hardware implementation reduces area and performance overhead of VeritAcc. We show that an field programmable gate array (FPGA) prototype of VeritAcc introduces less than 6.25% digital signal processing (DSP) area overhead compared to a baseline untrusted MM accelerator while enabling $11\times -69\times $ speed-ups compared with software execution.

Relaxation digital‐to‐analogue converter

The novel relaxation digital-to-analogue conversion technique, which takes advantage of the exponential impulse response of a first-order RC network to generate binary-weighted voltages, is proposed to design standard-cell based, mismatch-insensitive, ultra-low power, tiny digital-to-analogue converters targeting the requirements of Internet of Things applications. The effectiveness of the approach is validated by simulations and measurements performed on a proof-of-concept 10 bit, 300 S/s field programmable gate array prototype.

Architecture and FPGA prototype of cycle stealing DMA array signal processor for ultrasound sector imaging systems

Array Signal Processor (ASP) is widely used in antenna-array beamforming applications, such as RADAR, SONAR, Medical Ultrasound, Multiple-Input-Multiple-Output (MIMO) etc. In this paper, architecture and Field Programmable Gate Array (FPGA) Prototype of a Cycle Steeling Direct Memory Access (DMA) Digital Beamformer (DBF) for Ultrasound Sector Imaging Systems is proposed. The architecture is based on delay and sum and it requires Fine Delay (FD) and Coarse Delay (CD) values to steer and dynamically focus the array, and apodization weights to improve the directivity. To improve the Fine delay accuracy Minimum Mean Square Error (MMSE) interpolation filter is proposed and implemented. To support wide Field of View (FOV) steering, immense delay values are required and real-time computations are hard for high sampling rate systems. Also, the precomputed delay values require huge memory, which causes a significant increase in the ASP area. To solve this problem, a cycle stealing DMA controller based on Quad Serial Peripheral (QSPI) interface to load delay values from external flash without disturbing ASP processing has been proposed and realized. Moreover, for debuggability,the architecture supports custom JTAG debug interface logic and lock-up latch based Design for Testability (DFT) Scan chain for multiple clock domains. The paper also presents the design and implementation of an Ultrasound Sector Imaging System Prototype setup to emulate the ASP. Most of the existing research work in this area supports ultrasound echo acquisition to PC and processing. However, the designed prototype helps researchers to validate computationally complex Ultrasound signal processing algorithms like ASP on FPGA and further processing on PC.

Coverage Driven Functional Testing Architecture for Prototyping System Using Synthesizable Active Agent

Time and efforts for functional testing of digital logic is big chunk of overall project cycle in VLSI industry. Progress of functional testing is measured by functional coverage where test-plan defines what needs to be covered, and test-results indicates quality of stimulus. Claiming closer of functional testing requires that functional coverage hits 100% of original test-plan. Depending on the complexity of the design, availability of resources and budget, various methods are used for functional testing. Software simulations using various logic simulators, available from Electronic Design Automation (EDA) companies, is primary method for functional testing. The next level in functional testing is pre-silicon verification using Field Programmable Gate Array (FPGA) prototype and/or emulation platforms for stress testing the Design Under Test (DUT). With all the efforts, the purpose is to gain confidence on maturity of DUT to ensures first time silicon success that meets time to market needs of the industry. For any test-environment the bottleneck, in achieving verification closer, is controllability and observability that is quality of stimulus to unearth issues at early stage and coverage calculation. Software simulation, FPGA prototype, or emulation, each method has its own limitations, be it test-time, ease of use, or cost of software, tools and hardware-platform. Compared to software simulation, FPGA prototyping and emulation methods pose greater challenges in quality stimulus generation and coverage calculation. Many researchers have identified the problems of bug-detection/localization, but very few have touched the concept of quality stimulus generation that leads to better functional coverage and thereby uncover hidden bugs in FPGA prototype verification setup. This paper presents a novel approach to address above-mentioned issues by embedding synthesizable active-agent and coverage collector into FPGA prototype. The proposed architecture has been experimented for functional and stress testing of Universal Serial Bus (USB) Link Training and Status State Machine (LTSSM) logic module as DUT in FPGA prototype. The proposed solution is fully synthesizable and hence can be used in both software simulation as well as in prototype system. The biggest advantage is plug and play nature of this active-agent component, that allows its reusability in any USB3.0 LTSSM digital core.al Coverage, Synthesizable Active Agent, Universal Serial Bus (USB), Link Training and Status State Machine (LTSSM).

FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip

The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.

Secure and Lightweight Compressive Sensing Using Stream Cipher

We are proposing a lightweight and secure compressive sensing (CS) method for compression of data generated by image sensors. This method simultaneously compresses and encrypts image and video files, thereby reducing communication cost, storage space, runtime, and power/energy overhead. Our proposed method combines the CS technique with stream cipher to implement the secure CS. Furthermore, the usage of stream cipher to generate the measurement matrix results in minimal overhead to achieve the security objective. Our experimental studies using the field-programmable gate array prototype show that the security enhancements to the circuit comes, with no timing overhead, reduces 41%–84% of memory requirements and there is only a 8%–33% increase in the LUTs depending on the compression ratio.

COVERAGE DRIVEN FUNCTIONAL TESTING ARCHITECTURE FOR PROTOTYPING SYSTEM USING SYNTHESIZABLE ACTIVE AGENT

Time and efforts for functional testing of digital logic is big chunk of overall project cycle in VLSI industry. Progress of functional testing is measured by functional coverage where test-plan defines what needs to be covered, and test-results indicates quality of stimulus. Claiming closer of functional testing requires that functional coverage hits 100% of original test-plan. Depending on the complexity of the design, availability of resources and budget, various methods are used for functional testing. Software simulations using various logic simulators, available from Electronic Design Automation (EDA) companies, is primary method for functional testing. The next level in functional testing is pre-silicon verification using Field Programmable Gate Array (FPGA) prototype and/or emulation platforms for stress testing the Design Under Test (DUT). With all the efforts, the purpose is to gain confidence on maturity of DUT to ensures first time silicon success that meets time to market needs of the industry. For any test-environment the bottleneck, in achieving verification closer, is controllability and observability that is quality of stimulus to unearth issues at early stage and coverage calculation. Software simulation, FPGA prototype, or emulation, each method has its own limitations, be it test-time, ease of use, or cost of software, tools and hardware-platform. Compared to software simulation, FPGA prototyping and emulation methods pose greater challenges in quality stimulus generation and coverage calculation. Many researchers have identified the problems of bug-detection/localization, but very few have touched the concept of quality stimulus generation that leads to better functional coverage and thereby uncover hidden bugs in FPGA prototype verification setup. This paper presents a novel approach to address above-mentioned issues by embedding synthesizable active-agent and coverage collector into FPGA prototype. The proposed architecture has been experimented for functional and stress testing of Universal Serial Bus (USB) Link Training and Status State Machine (LTSSM) logic module as DUT in FPGA prototype. The proposed solution is fully synthesizable and hence can be used in both software simulation as well as in prototype system. The biggest advantage is plug and play nature of this active-agent component, that allows its reusability in any USB3.0 LTSSM digital core.al Coverage, Synthesizable Active Agent, Universal Serial Bus (USB), Link Training and Status State Machine (LTSSM).

Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems

Abstract This paper presents a reconfigurable Fast Fourier Transform (FFT) hardware architecture for 3GPP LTE systems. In the main FFT computing process, a novel processing kernel engine is proposed to support four configuration types of changeable hybrid-radix FFT operations. Also, in the data storage manipulation, a smart 2D-FIFO structure is used to flexibly handle efficient reading/writing data access for 36 different FFT sizes. In addition to a field-programmable gate array prototyping design approach, we provide application-specific integrated circuit implementation via TSMC 90-nm CMOS technology. The developed FFT chip only occupies a core area of 1 . 416 mm 2 , consumes 24.2 mW of power, and reaches maximum speed of 111.11 MHz.

FPGA Logic Circuit Implementation and Synthesis with VHDL Programming: A Learning Approach

There are significant numbers of relevant research works available that concerns VHDL programming and Field Programmable Gate Array (FPGA) based hardware design, simulation and implementation. This is because; both the FPGA design and VHDL programming realization are quiet new and useful to accomplish various tasks in the field of research for digital system designed and development of miniaturized embedded system. It is found difficult to understand and put into practice by the learners in the tertiary institution, which still requires rapid training and development. In this paper, we design and demonstrate an FPGAlogic circuit using 4-bit BCD adders and parallel 4-bit comparator with a stepwise development of the vital soft logic design flow, simulation and timing analysis. It also presents an educational concept designed for complementing courses offered like FPGA prototype and ASIC design. This perception of FPGA-based design flow will facilitate learner’s understanding, skills and it will provide detailed insights into various aspects of microelectronics, digital logic systems design and VHDL programming. Keywords: Behavioral synthesis, BCD Adder, Four-bit comparator, FPGA prototype, Hardware design, Microelectronic, VHDL programming.

Low-Complexity Methodology for Complex Square-Root Computation

In this brief, we propose a low-complexity methodology to compute a complex square root using only a circular coordinate rotation digital computer (CORDIC) as opposed to the state-of-the-art techniques that need both circular as well as hyperbolic CORDICs. Subsequently, an architecture has been designed based on the proposed methodology and implemented on the ASIC platform using the UMC 180-nm Technology node with 1.0 V at 5 MHz. Field programmable gate array (FPGA) prototyping using Xilinx’ Virtex-6 (XC6v1x240t) has also been carried out. After thorough theoretical analysis and experimental validations, it can be inferred that the proposed methodology reduces 21.15% slice look up tables (on FPGA platform) and saves 20.25% silicon area overhead and decreases 19% power consumption (on ASIC platform) when compared with the state-of-the-art method without compromising the computational speed, throughput, and accuracy.

ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform

Network-on-chip (NoC) is an emerging interconnect infrastructure to address the scalability limitation of conventional shared bus architecture for many-core system-on-chip (MCSoC). Current field-programmable gate arrays (FPGAs) have over million lookup tables, making it possible to prototype a complete NoC-based MCSoC on a single FPGA device. FPGA prototyping allows rapid system verification and optimum design parameters estimation. However, existing NoC-based MCSoC prototypes are usually adopting simple NoC architectural functionality. These NoC prototypes cannot represent a realistic projection of the state-of-the-art application-specific integrated circuit (ASIC) NoCs as these prototypes have limited overall system performance. This paper presents ProNoC, an integrated tool for rapid prototyping and validation of NoC-based MCSoC projects targeting FPGA devices. ProNoC adopts most advanced NoC features such as the support of virtual channel (VC), virtual network, low latency routing and different routing algorithms. Results show that NoC interconnect in ProNoC outperforms CONNECT, the most recent VC based prototype NoC with lower logic cell utilization, higher maximum operating frequency, higher average saturation throughput, and lower average communication latency. Moreover, ProNoC is equipped with graphical user interface to facilitate the development of MCSoC prototypes on FPGA platforms.

Fast FPGA prototyping for real-time image processing with very high-level synthesis

Programming in high abstraction level can facilitate the development of digital signal processing systems. In the recent 20 years, high-level synthesis (HLS) has made significantly progress. This technique greatly benefits the R&D productivity of the Field Programmable Gate Array (FPGA) developments and helps for adding to the maintainability of the products by automating the C-to-RTL (register transfer language) conversion. However, due to the high complexity and computational intensity, image processing algorithms usually necessitate a higher abstraction environment than C-synthesis, and the current HLS tools do not have the ability of this kind. This paper presents a conception of very high-level synthesis method which allows fast prototyping and verifying the FPGA-based image processing designs in the MATLAB environment. We build a heterogeneous development flow by using currently available tool kits for verifying the proposed approach and evaluated it within two real-life applications. Experiment results demonstrate that it can effectively reduce the complexity of the development by automatically synthesizing the algorithm behavior from the user level into the low register transfer level and give play to the advantages of FPGA related to the other devices.

An Intelligent Vehicular Traffic Signal Control System with State Flow Chart Design and FPGA Prototyping

The problem of vehicular traffic congestion is a persistent constraint in the socio-economic development of Pakistan. This paper presents design and implementation of an intelligent traffic controller based on FPGA (Field Programmable Gate Array) to provide an efficient traffic management by optimizing functioning of traffic lights which will result in minimizing traffic congestion at intersections. The existent Traffic Signal system in Pakistan is fixed-time based and offers only Open Loop method for Traffic Control. The Intelligent Traffic Controller presented here uses feedback sensors to read the Traffic density present at a four way intersection to provide an efficient alternative for better supervisory Control of Traffic flow. The traffic density based control logic has been developed in a State Flow Chart for improved visualization of State Machine based operation, and implemented as a Subsystem in Simulink and transferred into VHDL (Hardware Description Language) code using HDL Coder for reducing development time and time to market, which are essential to capitalize Embedded Systems Market. The VHDL code is synthesized with Altera QUARTUS, simulated timing waveform is obtained to verify correctness of the algorithm for different Traffic Scenarios. For implementation purpose estimations were obtained for Cyclone-III and Stratix-III.

An efficient and cost effective FPGA based implementation of the Viola-Jones face detection algorithm

Abstract We present an field programmable gate arrays (FPGA) based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and that it will encourage and facilitate further research and educational ideas in the areas of image processing, computer vision, and advanced digital design and FPGA prototyping.

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC

Chip communication architectures become an important element that is critical to control when designing a complex MultiProcessor System-on-Chip (MPSoC). This led to the emergence of new interconnection architectures, like Network-on-Chip (NoC). NoCs have been proven to be a promising solution to the concerns of MPSoCs in terms of data parallelism. Field-Programmable Gate Arrays (FPGA) has some perceived challenges. Overcoming those challenges with the right prototyping solutions is easy and cost-effective leading to much faster time-to-market. In this paper, we present an FPGA based on rapid prototyping in hardware/software co-design and design evaluation of a mixed HW/SW MPSoC using a NoC. A case study of two-dimensional mesh NoC-based MPSoC architecture is presented with a validation environment. The synthesis and implementation results of the NoC-based MPSoC on a Virtex 5 ML 507 enable a reasonable frequency (151.5 MHz) and a resource usage rate equals to 58% (6,586 out of 11,200 slices used).

Configurable Controller for High-Resolution LED Display Systems

Light-emitting diode (LED) display systems are implemented in various resolutions and aspect ratios to satisfy various display requirements. The requisite resolution and aspect ratio can be obtained by combining the appropriate LED panels. However, using different types of LED panels require using different types of LED controllers to drive them, which constitutes a rather burdensome design constraint. In addition, a driving circuit inside an LED panel may be modified to improve the display quality by adopting a new driving scheme or new LED elements. Furthermore, it may sometimes be necessary to create a completely new LED panel. All of these situations require the design of new LED controllers. In this paper, we, therefore, propose a configurable LED controller that can be used with various types of LED panels without requiring hardware modification or redesign. The proposed LED controller consists of an application-specific instruction-set processor (ASIP) and custom hardware. The ASIP is software programmable, and the custom hardware is employed to obtain a high operating speed. Moreover, the function of the custom hardware can be configured through the ASIP software program for generating the necessary address sequence to read the image bit plane memory and, consequently, to accommodate the target LED panel. Therefore, the proposed LED controller provides the advantages of flexibility and high-speed operation. The proposed LED controller was implemented using Xilinx Virtex-5, and it successfully drove LED panels having 64 × 96, 96 × 80, and 128 × 64 pixels at refresh rates of 3125, 2232, and 1736 Hz, respectively. An analysis of the operational capability indicates that, at the same refresh rate, the field-programmable gate array prototype of the proposed controller drives 1.44 times more pixels per unit time than a state-of-the-art commercial controller.

Fast Protection-Domain Crossing in the CHERI Capability-System Architecture

Capability Hardware Enhanced RISC Instructions (CHERI) supplement the conventional memory management unit (MMU) with instruction-set architecture (ISA) extensions that implement a capability system model in the address space. CHERI can also underpin a hardware-software object-capability model for scalable application compartmentalization that can mitigate broader classes of attack. This article describes ISA additions to CHERI that support fast protection-domain switching, not only in terms of low cycle count, but also efficient memory sharing with mutual distrust. The authors propose ISA support for sealed capabilities, hardware-assisted checking during protection-domain switching, a lightweight capability flow-control model, and fast register clearing, while retaining the flexibility of a software-defined protection-domain transition model. They validate this approach through a full-system experimental design, including ISA extensions, a field-programmable gate array prototype (implemented in Bluespec SystemVerilog), and a software stack including an OS (based on FreeBSD), compiler (based on LLVM), software compartmentalization model, and open-source applications.

The Design and Implementation of Embedded Security CPU Based on Multi‐strategy

Control flow monitoring, information flow tracking and memory monitoring are the three main solutions to enhance the security of embedded system at the hardware architecture level. However, most of the current studies about the security of embedded system consider the above solutions in separate dimensions rather than a combined effort. We start from the operation model at the instruction level, and propose a security multi-strategy which combines information flow tracking and memory monitoring by studying the security operating mechanism of embedded system. As a hardware approach this strategy extends the embedded processor architecture with additional security defense control. The experimental results show this multi-strategy is more effective and can detect more malicious attacks than a single solution. The effectiveness of our proposed security multi-strategy has been verified in a Field programmable gate array (FPGA) prototype platform based on a customized Leon3 microprocessor.

Efficient and high‐performance pedestrian detector implementation for intelligent vehicles

Human detection is exploited as a key operation in many applications such as automotive safety, intelligent vehicles, assisted living, and video surveillance. Consequently, there is a significant advancement in this area of research in the past years and a vast literature. In this study, the authors propose a pedestrian detection system which relies on sliding covariance matrix feature descriptor combined with a support vector machine classifier. The proposed framework is implemented onto field programmable gate array prototyping boards. Experimental results using the standard Institut National de Recherche en Informatique et en Automatique (INRIA) pedestrian benchmark dataset show that the proposed architecture achieved outstanding processing performances with high detection accuracy when compared with state-of-the-art methods.

Low latency pipelined CORDIC-like rotator architecture

ABSTRACTThis work presents a Field Programmable Gate Array (FPGA) prototyping of a new low latency pipelined COordinate Rotation DIgital Computer (CORDIC)-like rotator. The proposed rotator predicts the directions for all rotations in parallel and determines the final coordinates using the architecture with logarithmic relation between the number stages and precision of the target angle. The functionality of the pipelined CORDIC-like rotator is verified by implementing on the Xilinx Virtex-4 pro device (XC4vlx40, 90 nm technology). Based on detailed comparisons with the available pipelined rotators for the resolution of 8–12 bits, it is observed that the proposed rotator requires less hardware and improves latency by 45–85%.