Field Programmable Gate Array Resources Research Articles

Optimizing Security and Cost Efficiency in N-Level Cascaded Chaotic-Based Secure Communication System

In recent years, chaos-based secure communication systems have garnered significant attention for their unique attributes, including sensitivity to initial conditions and periodic orbit density. However, existing systems face challenges in balancing encryption strength with practical implementation, especially for multiple levels. This paper addresses this gap by introducing a novel N-level cascaded chaotic-based secure communication system for voice encryption, leveraging the four-dimensional unified hyperchaotic system. Performance evaluation is conducted using various security metrics, including Signal-to-Noise Ratio (SNR), Peak Signal-to-Noise Ratio (PSNR), Percent Residual Deviation (PRD), and correlation coefficient, as well as Field-Programmable Gate Array (FPGA) resource metrics. A new Value-Based Performance Metrics (VBPM) framework is also introduced, focusing on both security and efficiency. Simulation results reveal that the system achieves optimal performance at N = 4 levels, demonstrating significant improvements in both security and FPGA resource utilization compared to existing approaches. This research offers a scalable and cost-efficient solution for secure communication systems, with broader implications for real-time encryption in practical applications.

Prototype development of a three-stage, high-precision, low-jitter, wide-range digital delay generator fully utilizing on-chip resources.

This paper introduces the design and implementation of a prototype Digital Delay Generator (DDG) characterized by high precision, low jitter, and a wide delay range, fully realized within a Field Programmable Gate Array (FPGA). The DDG's architecture is based on an innovative combination of an embedded time-to-digital converter (TDC) and Multi-stage Time Interpolation (MTI) delay logic. The paper explores the factors influencing delay jitter during external trigger mode and carefully selects the optimal design approach for each element. The embedded TDC, which undergoes automatic calibration, accurately measures the time difference between the arrival of an external trigger and the FPGA's internal clock signal. When paired with the MTI delay logic, this allows for highly precise control over delay durations. A key aspect of this design is its sole dependence on the FPGA's built-in resources, ensuring simplicity in implementation and adaptability to various applications. Evaluation of the prototype has shown promising results, demonstrating a delay resolution as fine as 20ps and maintaining a low jitter of 105ps peak-to-peak (20ps rms) when operated in the externally triggered mode.

Arterial Distension Monitoring Scheme Using FPGA-Based Inference Machine in Ultrasound Scanner Circuit System.

This paper presents an arterial distension monitoring scheme using a field-programmable gate array (FPGA)-based inference machine in an ultrasound scanner circuit system. An arterial distension monitoring requires a precise positioning of an ultrasound probe on an artery as a prerequisite. The proposed arterial distension monitoring scheme is based on a finite state machine that incorporates sequential support vector machines (SVMs) to assist in both coarse and fine adjustments of probe position. The SVMs sequentially perform recognitions of ultrasonic A-mode echo pattern for a human carotid artery. By employing sequential SVMs in combination with convolution and average pooling, the number of features for the inference machine is significantly reduced, resulting in less utilization of hardware resources in FPGA. The proposed arterial distension monitoring scheme was implemented in an FPGA (Artix7) with a resource utilization percentage less than 9.3%. To demonstrate the proposed scheme, we implemented a customized ultrasound scanner consisting of a single-element transducer, an FPGA, and analog interface circuits with discrete chips. In measurements, we set virtual coordinates on a human neck for 9 human subjects. The achieved accuracy of probe positioning inference is 88%, and the Pearson coefficient (r) of arterial distension estimation is 0.838.

"Enhanced DA Algorithm for FIR Filter Design and FPGA Implementation"

Abstract: This study looks into the difficulties of using the Distributed Arithmetic (DA) method for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). It focuses on how coefficients are represented, balancing precision using fixed-point arithmetic and quantization. The research explores ways to optimize memory use, aiming to store data more efficiently within FPGA resources and reduce memory needs. To speed up computations, it examines how to make accessing lookup tables faster and suggests improvements in design. The study also considers how to manage FPGA resources effectively, balancing latency, throughput, and resource use. It looks at specific improvements to the DA method for FIR filters to make better use of resources and enhance performance. Overall, this work provides insights and solutions for algorithm design, memory use, lookup table speed, and FPGA architecture to make DA-based FIR filter implementations on FPGAs more efficient.

Area–time–energy efficient architecture of CBNS‐based fast Fourier transform

AbstractA new approach for implementing the fast Fourier transform (FFT) using complex binary number system (CBNS) is presented in this paper. The advantage of using CBNS is that instead of processing the real and imaginary parts of a complex number separately, we can process both as a single entity. A total of four FFT architectures have been developed, which are 16‐, 64‐, 256‐, and 1024‐point FFT architectures. The proposed FFT is designed using Verilog‐HDL and implemented using a Virtex‐7 field‐programmable gate array (FPGA). The maximum clock rate achieved by the proposed FPGA‐based design is 376.1 MHz. The FPGA resource utilization of the FFT is less than the state‐of‐the‐art FFT designs. An application‐specific integrated circuit (ASIC) for the FFT is also designed. The normalized energy per FFT of the proposed ASIC is 0.14 nJ, and the normalized area per FFT of the ASIC is 1.08 mm2 which is less than other existing designs.

High frequency attitude determination of micro satellites based on FPGA

The accuracy and speed of satellite attitude calculation algorithms are one of the key factors affecting the performance of satellite attitude control. This article proposes a high-performance attitude calculation algorithm for micro satellites based on Field Programmable Gate Array (FPGA). This algorithm is designed and simplified based on the parallel characteristics and abundant computing resources of FPGA. The algorithm fully utilizes the parallel computing power of FPGA and designs a multi-stage pipeline for complex matrix operations in Kalman filtering. It can simultaneously complete data collection and final attitude determination result output, greatly improving the output frequency of attitude information and reducing output delay. The experimental results show that compared to traditional embedded processors, FPGA based attitude calculation has significant advantages in terms of speed.

FPGA implementation of joint synchronization algorithm based on short training sequence

Synchronization processing is a vital component of the Orthogonal Frequency Division Multiplexing (OFDM) receiver, playing a decisive role in determining the performance of the OFDM receiver. Based on the repetitive structure of the Short Training Sequence (STS) in the IEEE 802.11 physical layer protocol data unit, this paper proposes and implements a joint synchronization algorithm to address issues related to data packet detection and coarse frequency offset correction during the synchronization process. Through software simulation and Field-Programmable Gate Array (FPGA) board-level validation, it is concluded that the algorithm ensures performance while, to some extent, conserving FPGA resources.

Flare: An FPGA-Based Full Precision Low Power CNN Accelerator with Reconfigurable Structure.

Convolutional neural networks (CNNs) have significantly advanced various fields; however, their computational demands and power consumption have escalated, posing challenges for deployment in low-power scenarios. To address this issue and facilitate the application of CNNs in power constrained environments, the development of dedicated CNN accelerators is crucial. Prior research has predominantly concentrated on developing low precision CNN accelerators using code generated from high-level synthesis (HLS) tools. Unfortunately, these approaches often fail to efficiently utilize the computational resources of field-programmable gate arrays (FPGAs) and do not extend well to full precision scenarios. To overcome these limitations, we integrate vector dot products to unify the convolution and fully connected layers. By treating the row vector of input feature maps as the fundamental processing unit, we balance processing latency and resource consumption while eliminating data rearrangement time. Furthermore, an accurate design space exploration (DSE) model is established to identify the optimal design points for each CNN layer, and dynamic partial reconfiguration is employed to maximize each layer's access to computational resources. Our approach is validated through the implementation of AlexNet and VGG16 on 7A100T and ZU15EG platforms, respectively. We achieve an average convolutional layer throughput of 28.985 GOP/s and 246.711 GOP/s for full precision. Notably, the proposed accelerator demonstrates remarkable power efficiency, with a maximum improvement of 23.989 and 15.376 times compared to current state-of-the-art FPGA implementations.

The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW

The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW

Asynchronous co-simulation of photovoltaic power generation system based on FPGA-CPU

In order to realize the real-time electromagnetic transient simulation of grid-connected photovoltaic power generation system with small time step, a heterogeneous multiplexed parallel real-time simulation method based on field programmable gate array (FPGA) and central processor is studied. According to the simulation accuracy requirements of the high and low frequency decoupling module, a differentiated simulation step size is used to solve the problem, and a 1us/50us FPGA-CPU multi-rate real-time simulation platform is constructed, in which the FPGA simulation part meets the real-time requirements of small-step transient simulation through the optimization of the response matching method and the EMTP algorithm, the offline simulation results are compared with Simulink, and the model before and after optimization is analyzed, the real-time electromagnetic transient simulation results are compared with Simulink, and the model before and after optimization is analyzed. By comparing the offline simulation results with Simulink and analyzing the FPGA resource consumption before and after model optimization, the accuracy and real-time performance of the co-simulation method for real-time simulation of grid-connected photovoltaic systems are verified.

Hardware Sequence Combinators

Recent advances in formal methods for constructing parsers have employed the notion of combinators: primitive elemental parsers with well-defined methods for combining them in sequences or through choice. This paper explores the subtleties associated with leveraging sequence combinators to produce compact, custom hardware traffic validators. This involves a fully automated process that takes as input a formal grammar specifying message formats and produces a parsing circuit capable of validating traffic headers and payload content. The resulting circuit is deployed through network guard appliances that employ Field Programmable Gate Array (FPGA) devices, or alternatively, within the on-chip FPGA associated with System-on-Chip (SoC) devices, such as the Xilinx UltraScale MPSoC. Each guard appliance acts as a hidden “bump-in-the-wire” that either forwards or drops individual packets based on the message parsing outcome, thereby hardening network segments against zero-day attacks and persistent implants. Guards may operate on a wide variety traffic protocols and formats including TCP/IP, CAN/J1939, or MIL-STD-1553. The central step in parser construction is to build a collection of standard shift/reduce parsing tables that can be employed by a push-down automata to check each byte in a message. Typically, these tables are sparse, resulting in excessive use of FPGA circuit resources to represent them. By leveraging sequence combinators, along with other optimizations, we have been able to produce highly compact representations that can reduce table size by up to 95% for non-trivial grammars. Depending on the grammar, this translates directly into FPGA resource reductions. The reductions now make it viable to implement complex parsers on small, inexpensive FPGA’s, or alternatively combine parsers with encryption and encapsulation to enhance guard capabilities.

Enhancing FPGA Testing Efficiency: A PRBS-Based Approach for DSP Slices and Multipliers

The multiplication operations are pivotal in (Application-Specific Integrated Circuits) ASICs and Digital Signal Processors (DSPs). The integration of Field-Programmable Gate Arrays (FPGAs) into modern embedded systems, efficient Built-in Self-Tests (BISTs), particularly for complex components like DSP slices, is essential. This paper evaluates Pseudo Random Binary Sequence (PRBS) generators and checkers as BIST tools for high-speed data transfers in FPGAs. The design achieves minimal errors and remarkable efficiency with less than 4% logic utilization within available Look-Up Tables (LUTs). The testing of embedded multipliers in modern FPGAs is analyzed, shedding light on their performance. The analysis includes Built-in Self-Test (BIST), PRBS generator, PRBS checker, and Bit Error Rate (BER), providing insights into FPGA-based testing. This analysis assesses PRBS tools for high-speed FPGA data transfers. A hybrid multiplier design, featuring BIST and PRBS capabilities, notably reduces DSP slice utilization from 16% to 5%. This liberated FPGA resource enhances operational capabilities. The runtime PRBS data control at the block level design exemplifies adaptability in FPGA testing. The findings underscore PRBS-based BIST potential in FPGA testing. The hybrid multiplier not only optimizes FPGA resources but also aligns with dynamic digital system requirements. This research aids FPGA designers and engineers in advanced testing strategies for evolving embedded systems.

Developing a Portable Fluorescence Imaging Device for Fish Freshness Detection.

Rapid detection of fish freshness is of vital importance to ensuring the safety of aquatic product consumption. Currently, the widely used optical detecting methods of fish freshness are faced with multiple challenges, including low detecting efficiency, high cost, large size and low integration of detecting equipment. This research aims to address these issues by developing a low-cost portable fluorescence imaging device for rapid fish freshness detection. The developed device employs ultraviolet-light-emitting diode (UV-LED) lamp beads (365 nm, 10 W) as excitation light sources, and a low-cost field programmable gate array (FPGA) board (model: ZYNQ XC7Z020) as the master control unit. The fluorescence images captured by a complementary metal oxide semiconductor (CMOS) camera are processed by the YOLOv4-Tiny model embedded in FPGA to obtain the ultimate results of fish freshness. The circuit for the YOLOv4-Tiny model is optimized to make full use of FPGA resources and to increase computing efficiency. The performance of the device is evaluated by using grass carp fillets as the research object. The average accuracy of freshness detection reaches up to 97.10%. Moreover, the detection time of below 1 s per sample and the overall power consumption of 47.1 W (including 42.4 W light source power consumption) indicate that the device has good real-time performance and low power consumption. The research provides a potential tool for fish freshness evaluation in a low-cost and rapid manner.

ChamelIoT: a tightly- and loosely-coupled hardware-assisted OS framework for low-end IoT devices

The evergrowing Internet of Things (IoT) ecosystem continues to impose new requirements and constraints on every device. At the edge, low-end devices are getting pressured by increasing workloads and stricter timing deadlines while simultaneously are desired to minimize their power consumption, form factor, and memory footprint. Field-Programmable Gate Arrays (FPGAs) emerge as a possible solution for the increasing demands of the IoT. Reconfigurable IoT platforms enable the offloading of software tasks to hardware, enhancing their performance and determinism. This paper presents ChamelIoT, an agnostic hardware operating systems (OSes) framework for reconfigurable IoT devices. The framework provides hardware acceleration for kernel services of different IoT OSes by leveraging the RISC-V open-source instruction set architecture (ISA). The ChamelIoT hardware accelerator can be deployed in a tightly- or loosely-coupled approach and implements the following kernel services: thread management, scheduling, synchronization mechanisms, and inter-process communication (IPC). ChamelIoT allows developers to run unmodified applications of three well-established OSes, RIOT, Zephyr, and FreeRTOS. The experiments conducted on both coupling approaches consisted of microbenchmarks to measure the API latency, the Thread Metric benchmark suite to evaluated the system performance, and tests to the FPGA resource consumption. The results show that the latency can be reduced up to 92.65% and 89.14% for the tightly- and loosely-coupled approaches, respectively, the jitter removed, and the execution performance increased by 199.49% and 184.85% for both approaches.

Place-and-Route Analysis of FPGA Implementation of Nested Hardware Self-Organizing Map Architecture

Self-organizing map (SOM) is a type of artificial neural network that provides a nonlinear mapping from a given high-dimensional input space to a low-dimensional map of neurons for clustering. The clustering of high-dimensional vectors is too slow for SOM when implemented in software. In such cases, an application-specific hardware SOM accelerator is highly desirable. Field-programmable gate array (FPGA) implementation is a popular platform to implement hardware SOM. In our previous work, a nested hardware SOM architecture, which has a homogeneous modular structure to enhance expandability, was proposed. This paper investigates the impact of the nested hardware SOM on FPGA implementation tools that perform logic synthesis, place, and route (PAR). Experiments revealed that the nested architecture provided better results in resource usage and performance. FPGA resource usage of the nested architecture was 97.2% of that of the flat design on average. Importantly, the nested architecture operated at 10% higher clock frequencies compared to flat SOM designs. In addition, the pipeline computation was improved by increasing the pipeline stages so that it operates with a higher clock frequency. The operable clock frequency was 81 MHz, which was 21 MHz higher than its predecessor.

FPGA implementation of carrier-based PWM techniques for single-phase matrix converters

Field programmable gate arrays (FPGAs) stand out as a highly efficient and reliable digital solution to control power electronics converters. Direct single-to-single-phase matrix converters (SSMCs) are widely used in industrial and power system-related applications and are usually controlled using carrier-based PWM techniques. Existing literature studies on FPGA implementation of carrier-based PWM techniques for SSMC lack providing architectural design details and programming algorithms. Further, resource utilization/power consumption optimizations and analyses are not performed. To fill these research gaps, we propose a new FPGA-based design that is capable of employing the desired carrier-based PWM technique and synthesizing any output frequency. It also optimizes the FPGA resource utilization and power consumption and utilizes a novel approach to synchronize the generated triggering pulses with the source. A laboratory setup is built to experimentally test the proposed FPGA-based design, where results demonstrate the efficiency and reliability of the design.

Hardware implementation of deep neural network for seizure prediction

Epilepsy is a neurological disorder characterized by seizures, which are caused by a sudden, uncontrollable electrical disturbance in the brain. Recently, machine learning and deep learning techniques have been used in seizure prediction algorithms, which greatly aids epilepsy patients. Moreover, the usage of hardware that is available for both medical practitioners and epilepsy patients would help enhance the quality of life for epilepsy patients. For this purpose, a Field-programmable Gate Array (FPGA) is used in this work to implement a hardware model of a neural network that is able to predict seizures. In this research, the main aim is to implement an FPGA-based general and patient-specific seizure prediction algorithm that detects seizures for epilepsy patients using Multilayer Perceptron (MLP) neural network models. Moreover, the work will also tackle ways to optimize the FPGA resources and the computational time of the seizure prediction models. The data available for training and testing are raw electroencephalogram (EEG) signal samples provided by the Melbourne-NeuroVista seizure trial and the Melbourne-University AES-MathWorks-NIH Seizure Prediction Challenge. The results show that the general model had an Area under curve (AUC) score of 0.72 while the patient-specific model had an average AUC score of 0.8.

Peak Cancellation Method With IIR Filters and Its FPGA Implementation

To improve the efficiency of power amplifiers (PA) in communication transmitters, peak cancellation (PC) in the time domain is often implemented on a Field-programmable gate array (FPGA) to reduce the peak-to-average power ratio (PAPR) of the baseband signals. However, to reduce the out-of-band radiation, the existing techniques tend to use high-order finite impulse response (FIR) filters, which increases the input-to-output delay and resource consumption of FPGA. To address this issue, a PC method with the infinite impulse response (IIR) filter is proposed in this brief. The design criteria of the IIR filter for PC is given. The FPGA implementation scheme and resource optimization are discussed. To verify the performance of the proposed method, MATLAB simulation and FPGA implementation are made with a 5G NR signal. The comparison with the state-of-the-art PC methods shows that the proposed technique can reduce the total time delay greatly, with good PC performance and low resource consumption.

A many-channel FPGA control system.

We describe a many-channel experiment control system based on a field-programmable gate array (FPGA). The system has 16 bit resolution on 10 analog 100 megasamples-per-second (MS/s) input channels, 14 analog 100 MS/s output channels, 16 slow analog input and output channels, dozens of digital inputs and outputs, and a touchscreen display for experiment control and monitoring. The system can support ten servo loops with 155ns latency and MHz bandwidths, in addition to as many as 30 lower bandwidth servos. We demonstrate infinite-impulse-response (IIR) proportional-integral-differential filters with 30ns latency by using only bit-shifts and additions. These IIR filters allow timing margin at 100 MS/s and use fewer FPGA resources than straightforward multiplier-based filters, facilitating many servos on a single FPGA. We present several specific applications: Hänsch-Couillaud laser locks with automatic lock acquisition and a slow dither correction of lock offsets, variable duty cycle temperature servos, and the generation of multiple synchronized arbitrary waveforms.

Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs

Domain-specific accelerators for signal processing, image processing, and machine learning are increasingly being implemented on SRAM-based field-programmable gate arrays (FPGAs). Owing to the inherent error tolerance of such applications, approximate arithmetic operations, in particular, the design of approximate multipliers, have become an important research problem. Truncation of lower bits is a widely used approximation approach; however, analyzing and limiting the effects of carry-propagation due to this approximation has not been explored in detail yet. In this article, an optimized carry-aware approximate radix-4 Booth multiplier design is presented that leverages the built-in slice look-up tables (LUTs) and carry-chain resources in a novel configuration. The proposed multiplier simplifies the computation of the upper and lower bits and provides significant benefits in terms of FPGA resource usage (LUTs saving 38.5%–42.9%), Power Delay Product (PDP saving 49.4%–53%), performance metric (LUTs × critical path delay (CPD) × PDP saving 68.9%–73.1%) and errors (70% improvement in mean relative error distance) compared to the latest state-of-the-art designs. Therefore, the proposed designs are an attractive choice to implement multiplication on FPGA-based accelerators.