Feedback Field-effect Transistor Research Articles

Design and performance analysis of tri-layered strained Si/Si1–x Ge x /Si heterostructure DG feedback FET

This work presents the design and performance analysis of a tri-layered strained Si/Si1−x Ge x /Si heterostructure double gate feedback field-effect transistor (DG FBFET). The proposed DG FBFET is designed by introducing biaxial strain in the device by sandwiching a Si1−x Ge x layer between two thin Si layers to provide high ON current as well as ultra-steep switching characteristics. The device offers a significantly high ON current (3.4 x 10−3 A/μm), high I ON /I OFF ratio (∼1010), a large memory window of 1.06 V, and an extremely low subthreshold swing (∼0.3 μ V/decade), which can be very useful for memory and neuromorphic applications. Furthermore, the ON/OFF switching of the device has been accomplished at a lower threshold voltage (0.287 V), allowing it to be utilized in low-power electronics. Synopsys TCAD tool has been used to create the device structure and analyze the electrical performances of the device.

Doping-Less Feedback Field-Effect Transistors.

In this study, we propose doping-less feedback field-effect transistors (DLFBFETs). Our DLFBFETs are 5 nm thick intrinsic semiconductor bodies with dual gates. Usually, DLFBFETs are virtually doped through charge plasma phenomena caused by the source, the drain, and the dual-gate electrodes as well as the gate biases. Our DLFBFETs can be fabricated through a simple process of creating contact between a metal and a silicon body without any doping processes. The voltages applied to both gates determine whether the DLFBFETs operate in diode or feedback field-effect transistor (FBFET) modes. In the FBFET mode, our DLFBFETs show good characteristics such as an on/off current ratio of ~104 and steep switching characteristics (~1 mV/decade of current) that result from positive feedback phenomena without dopants.

Logic-in-memory application of silicon nanotube-based FBFET with core-source architecture

The performance of a silicon nanotube-based feedback field-effect transistor (SiNT FBFET) with a core-source architecture has been explored in this work for the use in logic-in-memory (LIM) applications. Both n-channel and p-channel FETs with extremely symmetric transfer characteristics and a high ON/OFF current ratio of 109 are implemented in a single structure using the core and outer gates. SiNT FBFET exhibits significant data retention attributes during memory operations for up to 103 s. The SiNT FBFET-based inverter circuit retains output logic states of “1” and “0” for 1.705 s and 1.948 s, respectively, at megahertz operating frequency without standby power consumption. Additionally, SiNT FBFET has also been used to build ternary NAND/NOR logic gates with memory functionality. Numerical mixed-mode simulations of the circuits have been carried out using the commercially available Synopsys “Sentaurus” TCAD tool for examining the performance and memory characteristics of SiNT FBFETs. This study demonstrates the possible use of SiNT FBFET in multivalued logic systems and the development of next-generation memory devices.

Positive feedback field effect transistor based on vertical NAND flash structure for in-memory computing

The distance between memory and central processing unit has led to a memory wall. To solve it, an in-memory technology that performs both memory and computation has been studied. To realize an ideal in-memory computing, we propose a positive feedback FET based on vertical NAND flash structure that can act as a memory and perform computation. The device can reconfigure the processing operations into AND or OR operations depending on the control gate bias. It performs memory by accumulating charge in the body, and logic operations can be performed by reading data stored in the charge trap layer. After this, it can also perform a writing operation. This component enables memory and read-compute-write operations, making it capable of implementing intrinsic in-memory computing. As a result, in this study, we designed and verified a structure that implements the core principles of in-memory computing.

Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET

The design and performance analysis of a Si-SiGe heterostructure-based double gate feedback field-effect transistor (HDG FBFET) are presented in this paper. The proposed HDG FBFET is capable of providing high on current (3 × 10−4 A/μm) with a large I ON /I OFF ratio (3 × 1011) and is scalable up to 20 nm channel length. Its exceptionally steep switching characteristics (SS < 1 mV/decade) and ability to switch ON/OFF at lower gate voltage due to the use of smaller band-gap material (Si1−x Ge x ) in channel-2 and drain regions make it suitable for use in low power applications. A significant hysteresis window of 4.99 V is also achieved by the device, which can be extremely helpful for memory applications. Moreover, a comprehensive investigation of the nature of hysteresis in relation to the different device parameters has also been carried out. The designing of the device structure and all of the electrical performance characterization have been done using the Sentaurus TCAD tool.

Reconfigurable Feedback Field-Effect Transistors with a Single Gate.

In this study, we present a reconfigurable feedback field-effect transistor (FET) that can operate in both p- and n-type configurations using a feedback mechanism. In contrast to previously reported reconfigurable FETs, our device utilizes a single gate to trigger a feedback mechanism at the center, resulting in steep switching characteristics. The device exhibited high symmetry of transfer characteristics, an on/off current ratio of approximately 1010, extremely low subthreshold swings, and a high on-current of approximately 1.5 mA at low gate voltages in both configurations. In addition, because of their hysteresis and bistable characteristics, they can be applied to various electronic devices. These characteristics were analyzed using a commercial device simulator.

Design of Binary and Ternary Logic Inverters Based on Silicon Feedback FETs Using TCAD Simulator

A feedback field effect transistor (FBFET) with p-n-p-n structure benefits from a positive feedback mechanism. In this structure, the accumulated charges in its potential well and limitation of carrier flow by its internal potential barrier lead to superior electrical properties such as lower subthreshold swing (SS) and higher I ON / I OFF ratio in comparison with FinFET. Thus, FBFET is a promising alternative for digital applications such as logic inverters. In this paper, binary and ternary logic inverters are designed by using FBFETs with 40 nm channel length. The doping profile in the device plays an essential role and specifies the binary or ternary operation of the inverter. The inverter is analyzed by using a TCAD mixed-mode simulator. The results indicate the high value of 1010 for I ON / I OFF ratio with an extremely low SS (1 mV/decade). The voltage transfer characteristics of the inverter and its dependence on doping levels have been investigated. Also, the electrical properties of this inverter are compared with previous inverter counterparts.

Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD.

In this study, the electrical characteristics and electrical coupling effect for monolithic 3-dimensional nonvolatile memory consisting of a feedback field-effect transistor (M3D-NVM-FBFET) were investigated using technology computer-aided design. The M3D-NVM-FBFET consists of an N-type FBFET with an oxide-nitride-oxide layer and a metal-oxide-semiconductor FET (MOSFET) in the top and bottom tiers, respectively. For the memory simulation, the programming and erasing voltages were applied at 18 and -18 V for 1 μs, respectively. The memory window of the M3D-NVM-FBFET was 1.98 V. As the retention simulation was conducted for 10 years, the memory window decreased from 1.98 to 0.83 V. For the M3D-NVM-FBFET, the electrical coupling that occurs through an electrical signal in the bottom-tier transistor was investigated. As the thickness of the interlayer dielectric (TILD) decreases from 100 to 10 nm, the change in the VTH increases from 0.16 to 0.87 V and from 0.15 to 0.84 V after the programming and erasing operations, respectively. M3D-NVM-FBFET circuits with a thin TILD of 50 nm or less need to be designed considering electrical coupling.

Investigation of switching and inverter characteristics of Recessed-Source/Drain (Re–S/D) Silicon-on-Insulator (SOI) Feedback Field Effect Transistor (FBFET)

In this paper, the switching and inverter characteristics of Recessed-Source/Drain (Re–S/D) Silicon-on-Insulator (SOI) Feedback Field Effect Transistor (FBFET) are presented using a TCAD mixed-mode simulator. FBFETs have recently acquired popularity as alternative steep-switching devices. It has a very steep subthreshold slope (SS) and high ON current (ION). The current in the device is caused by the movement of electrons and holes which creates positive feedback. To improve the device characteristics in SOI FBFET, a Re–S/D technique is incorporated by extending the source and drain regions into the buried oxide (BOX). An improvement in the IONis observed with reduced hysteresis (memory window) in a Re–S/D SOI FBFET compared to conventional SOI FBFETs which is very useful in logic applications. A complementary inverter implemented using n-type and p-type Re–S/D SOI FBFETs is found to have improved voltage transfer characteristics (VTC) and transient response levels than those of SOI FBFET-based inverters. The high logic level is improved to 0.882V from 0.85V and the low logic level is improved to 0.1V from 0.15V in both VTC and transient response of SOI FBFET inverter at a Re–S/D thickness of 50 nm. Hence, a Re–S/D technique is very useful for both improvements in ION and tackling the problem of clear ON/OFF states in FBFET devices. Further, the three-stage Re–S/D SOI FBFET inverter-based ring-oscillator is implemented, and found that the frequency (fo) and propagation delay (tp) are improved with increased Re–S/D thickness.

Design and performance assessment of a vertical feedback FET

This paper proposes the structure of a vertical PNPN single gated feedback field-effect transistor (vertical FBFET) and investigates its performance using a TCAD simulator. The performance of the device is investigated against variations in a few geometrical and process parameters. The device exhibits an ultra-steep switching characteristic with a minimum subthreshold swing of 0.03 mV/dec and a high ON/OFF current ratio of ∼1011. Subsequently, the hysteresis characteristic of the vertical FBFET is analyzed against variation in interface trap charges at Si and Al2O3 interfaces. Due to the presence of negative/positive interface trap charges at silicon and Al2O3 interface, the memory window is enlarged/reduced from 1.1 V to 1.21 V/0.96 V respectively. The vertical FBFET also shows a wide variation in the memory window for channel length and temperature variations.

Capacitor-Less Low-Power Neuron Circuit with Multi-Gate Feedback Field Effect Transistor

Recently, research on artificial neuron circuits imitating biological systems has been actively studied. The neuron circuit can implement an artificial neural network (ANN) capable of low-power parallel processing by configuring a biological neural network system in hardware. Conventional CMOS analog neuron circuits require many MOSFETs and membrane capacitors. Additionally, it has low energy efficiency in the first inverter stage connected to the capacitor. In this paper, we propose a low-power neuron circuit with a multi-gate feedback field effect transistor (FBFET) that can perform integration without a capacitor to solve the problem of an analog neuron circuit. The multi-gate FBFET has a low off-current due to its low operating voltage and excellent sub-threshold characteristics. We replace the n-channel MOSFET of the inverter with FBFET to suppress leakage current. FBFET devices and neuron circuits were analyzed using TACD and SPICE mixed-mode simulation. As a result, we found that the neuron circuit with multi-gate FBFET has a low subthreshold slope and can completely suppress energy consumption. We also verified the temporal and spatial integration of neuron circuits.

A Monolithic 3-Dimensional Static Random Access Memory Containing a Feedback Field Effect Transistor.

A monolithic three-dimensional integrated static random access memory containing a feedback field effect transistor (M3D-FBFET-SRAM) was proposed. The M3D-FBFET-SRAM cell consists of one metal oxide semiconductor field effect transistor (MOSFET) and one FBFET, and each transistor is located on the top tier and one on the bottom tier in a monolithic 3D integration, respectively. The electrical characteristics and operation of the NFBFET in the M3D-FBFET-SRAM cell were investigated using a TCAD simulator. For SRAM operation, the optimum doping profile of the NFBFET was used for non-turn-off characteristics. For the M3D-FBFET-SRAM cell, the operation of the SRAM and electrical coupling occurring between the top and bottom tier transistor were investigated. As the thickness of interlayer dielectric decreases, the reading ‘ON’ current decreases. To prevent performance degradation, two ways to compensate for current level were suggested.

Understanding of carriers’ kinetic energy in steep-slope P+N+P+N+ feedback field effect transistor

A feedback field-effect transistor takes advantage of the charges accumulated in its potential well and the restriction of carrier flow by its internal potential barrier to achieve superior electrical properties such as a subthreshold swing, threshold voltage, transconductance, and on/off current ratio. However, the device must deal with the modulation of non-uniformity under forward/reverse bias and with completely losing carrier flow control during reverse bias below a certain channel length. In this work, we address these significant issues by focusing on the width of the source/drain and demonstrate the operation of positive feedback in n-type metal oxide semiconductor field-effect transistor (nMOSFET) using only one additional step, resulting in a superior subthreshold swing (∼3 mV/decade at 300 K), a low threshold voltage (∼0.26 V), hysteresis window (0.018 V), and clear saturation region.

Investigation of Tunneling Effect for a N-Type Feedback Field-Effect Transistor.

In this paper, the tunneling effect for a N-type feedback field-effect transistor (NFBFET) was investigated. The NFBFET has highly doped N-P junction in the channel region. When drain-source voltage is applied at the NFBFET, the aligning between conduction band of N-region and valence band of P-region occur, and band-to-band tunneling (BTBT) current can be formed on surface region of N-P junction in the channel of the NFBFET. When the doping concentration of gated-channel region (Ngc) is 4 × 1018 cm−3, the tunneling current makes off-currents increase approximately 104 times. As gate-source voltage is applied to NFBFET, the tunneling rate decreases owing to reducing of aligned region between bands by stronger gate-field. Eventually, the tunneling currents are vanished at the BTBT vanishing point before threshold voltage. When Ngc increase from 4 × 1018 to 6 × 1018, the tunneling current is generated not only at the surface region but also at the bulk region. Moreover, the tunneling length is shorter at the surface and bulk regions, and hence the leakage currents more increase. The BTBT vanishing point also increases due to increase of tunneling rates at surface and bulk region as Ngc increases.

Dependence of latch-up and threshold voltages on channel length in single-gated feedback field-effect transistor

This study demonstrates an optimal design method for the channel length in a p +–i–p–n + structure of feedback field-effect transistors (FBFETs) for next-generation memory devices. We demonstrate the dependence of latch-up and threshold voltages on the channel length in single-gated FBFETs with silicon channels consisting of gated and non-gated regions. The operation principle of the latch-up phenomena related to the channel length using an equivalent circuit in an FBFET has been described. The abrupt increase in the drain current of the single-gated FBFETs at the latch-up (threshold) voltage in the sweep of the drain (gate) voltage was analyzed with current gains in an equivalent circuit. The current gain depends on the gated and non-gated channel lengths; thereby, the latch-up and threshold voltages too depend on the gated and non-gated channel lengths. The dependences of the latch-up and threshold voltages on the non-gated channel length were found to be 3.62 times and 1.68 times higher than that on the gated channel length, respectively.

Logic and memory characteristics of an inverter comprising a feedback FET and a MOSFET

In this study, we design an inverter comprising a p-channel feedback field-effect transistor (p-FBFET) and an n-channel metal-oxide-semiconductor field-effect transistor and examine its logic and memory characteristics. For the transition of inverter from the logic ‘0’ (‘1’) state to ‘1’ (‘0’) state, the gain is 2001.6 V/V (1992.4 V/V). The steep switching characteristics and high on/off current ratio of the p-FBFET contribute to the high inverter gains. For an inverter with zero static power consumption, the logic states remain for more than 500 s. The long retention time allows the inverter proposed in this study to be applicable to logic-in-memory.

Study on memory characteristics of fin-shaped feedback field effect transistor

The nonvolatile and volatile memory characteristics of feedback field-effect transistors (FBFETs) with nitride charge storage layers were theoretically studied. Because of the electrons and holes stored in the nitride layer, the threshold voltage (V TH) window of 0.6 V was opened/observed. And, with the help of the formation of a positive feedback loop in the p+–n+–p–n+ doped silicon region in FBFET, it turned out that the read delay time of the FBFET for nonvolatile memory applications can be shorter than 1 ns. On the other hand, for the volatile memory applications, the FBFET can implement (a) non-destructive read operations owing to the self-sustaining feedback loop characteristic, and (b) a significantly long retention time which can suppress the power dissipation in refresh. Furthermore, the operation scheme of volatile memory mode can be simplified by setting gate voltage conditions for the hold and read operations to be identical to each other. The FBFET showed its on-state drive current of 6 × 10−5 A μm−1 and the on-/off-current ratio of 109. The potential of merging nonvolatile and volatile memory devices in a single cell is discussed and demonstrated in this work.

Design and Simulation of Logic-In-Memory Inverter Based on a Silicon Nanowire Feedback Field-Effect Transistor.

In this paper, we propose a logic-in-memory (LIM) inverter comprising a silicon nanowire (SiNW) n-channel feedback field-effect transistor (n-FBFET) and a SiNW p-channel metal oxide semiconductor field-effect transistor (p-MOSFET). The hybrid logic and memory operations of the LIM inverter were investigated by mixed-mode technology computer-aided design simulations. Our LIM inverter exhibited a high voltage gain of 296.8 (V/V) when transitioning from logic ‘1’ to ‘0’ and 7.9 (V/V) when transitioning from logic ‘0’ to ‘1’, while holding calculated logic at zero input voltage. The energy band diagrams of the n-FBFET structure demonstrated that the holding operation of the inverter was implemented by controlling the positive feedback loop. Moreover, the output logic can remain constant without any supply voltage, resulting in zero static power consumption.

Optimization of Feedback FET with Asymmetric Source Drain Doping Profile.

A feedback field-effect transistor (FBFET) is a novel device that uses a positive feedback mechanism. FBFET has a high on-/off ratio and is expected to realize ideal switching characteristics through steep changes from off-state to on-state. In this paper, we propose and optimize FBFET devices with asymmetric source/drain doping concentrations. Additionally, we discuss the changes in electrical characteristics across various channel length and channel thickness conditions and compare them with those of FBFET with a symmetric source/drain. This shows that FBFET with an asymmetric source/drain has a higher on-/off ratio than FBFET with a symmetric source/drain.

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation.

In this study, we propose an improved macro-model of an N-type feedback field-effect transistor (NFBFET) and compare it with a previous macro-model for circuit simulation. The macro-model of the NFBFET is configured into two parts. One is a charge integrator circuit and the other is a current generator circuit. The charge integrator circuit consisted of one N-type metal-oxide-semiconductor field-effect transistor (NMOSFET), one capacitor, and one resistor. This circuit implements the charging characteristics of NFBFET, which occur in the channel region. For the previous model, the current generator circuit consisted of one ideal switch and one resistor. The previous current generator circuit could implement IDS-VGS characteristics but could not accurately implement IDS-VDS characteristics. To solve this problem, we connected a physics-based diode model with an ideal switch in series to the current generator circuit. The parameters of the NMOSFET and diode used in this proposed model were fitted from TCAD data of the NFBFET, divided into two parts. The proposed model implements not only the IDS-VGS characteristics but also the IDS-VDS characteristics. A hybrid inverter and an integrate and fire (I&F) circuit for a spiking neural network, which consisted of NMOSFETs and an NFBFET, were simulated using the circuit simulator to verify a validation of the proposed NFBFET macro-model.