Feedback Bridging Research Articles

A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits

A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits

Application-Dependent Testing of FPGA Interconnect Network

The extensive application of field-programmable gate array (FPGA) devices in industrial environments makes FPGA testing a significant area of exploration. The application-dependent testing approach ensures better manufacturing yield compared to the manufacturing testing process since it can bypass the faulty parts without disturbing a given user-defined design. The interconnection resources occupy a large area in the FPGA die, and it is highly error-prone due to the presence of a huge number of transistors. Interconnection resources testing play a major role in the reconfigurable hardware testing area. This paper presents an application-dependent testing technique to generate test configurations for interconnects in static RAM (SRAM)-based FPGAs. To generate a test pattern for interconnects, logic block configurations have been modified. This paper addresses stuck-at faults, different types of dominant bridging faults, and feedback bridging faults. Appropriate constraints have been designed using Boolean satisfiability to test the above faults in the interconnects. Simulations performed on ISCAS’89, MCNC, and ITC’99 benchmark circuits mapped on different FPGA architectures show that the proposed approach can obtain a minimum number of test configurations with 100% fault coverage for the above-mentioned faults and is technology independent which enables it to address new emerging architectures in FPGAs.

Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults

Feedback bridging faults may give rise to oscillations within integrated circuits. This work mainly investigates the propagation of oscillations, a behavior that may have a relevant impact on the fault detection. We propose both a logic-level model of the faulty circuit and two techniques aiming to the generation of high-quality test sequences.

A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults

Classical manufacturing test verifies that a circuit is fault free during fabrication, however, cannot detect any fault that occurs after deployment or during operation. As complexity of integration rises, frequency of such failures is increasing for which on-line testing (OLT) is becoming an essential part in design for testability. In majority of the works on OLT, single stuck at fault model is considered. However in modern integration technology, single stuck at fault model can capture only a small fraction of real defects and as a remedy, advanced fault models such as bridging faults, transition faults, delay faults, etc. are now being considered. In this paper we concentrate on bridging faults for OLT. The reported works on OLT using bridging fault model have considered non-feedback faults only. The basic idea is, as feedback bridging faults may cause oscillations, detecting them on-line using logic testing is difficult. However, not all feedback bridging faults create oscillations and even if some does, there are test patterns for which the fault effect is manifested logically. In this paper it is shown that the number of such cases is not insignificant and discarding them impacts OLT in terms of fault coverage and detection latency. The present work aims at developing an OLT scheme for bridging faults including the feedback bridging faults also, that can be detected using logic test patterns. The proposed scheme is based on Binary Decision Diagrams, which enables it to handle fairly large circuits. Results on ISCAS 89 benchmarks illustrate that consideration of feedback bridging faults along with non-feedback ones improves fault coverage, however, increase in area overhead is marginal, compared to schemes only involving non-feedback faults.

New Techniques and Tools for Application-Dependent Testing of FPGA-Based Components

Field programmable gate array (FPGA) devices are increasingly being deployed in industrial environments, making reconfigurable hardware testing and reliability an active area of investigation. While FPGA devices can be tested exhaustively, the so-called application-dependent test (ADT) has emerged as an effective approach ensuring reduced testing efforts and improving the manufacturing yield since it can selectively exclude a subset of faults not affecting a given design. In addition to manufacturing, ADT can be used online, providing a solution for fast runtime fault detection and diagnostics. This paper identifies a number of issues in existing ADT techniques which limit their applicability and proposes new approaches improving the range of covered faults, with special emphasis on feedback bridging faults, as well as new algorithms for generating ADT test configurations. Furthermore, the work introduces a software environment addressing the current lack of tools, either academic or commercial, supporting ADT techniques. The architecture of the environment is highly modular and extensively based on a plug-in approach. To demonstrate the potential of the toolset, we developed a complete suite of plug-ins, based on both state-of-the-art ADT techniques and the novel approaches introduced here. The experimental results presented at the end of the paper confirm the impact of the proposed techniques.

A Quasi-Vehicle/Bridge Interaction Model for High Speed Railways

ABSTRACTVehicle response is served as a reference to evaluate riding comfort of passengers and running safety of moving carriages for high speed trains. In analyzing the vehicle-bridge interaction (VBI) problems, two sets of coupled equations of motion for running vehicles and bridge need to be solved and the VBI system matrices must be updated and factorized at each time step in a time-history analysis. This paper proposed a quasi-VBI model to abridge the complicated computational process, in which the bridge is subjected to only moving static forces of the train loadings, and the moving vehicle over it is excited by the corresponding feedback bridge response. To examine the interacting degree of the vehicle with the bridge, a coupling evaluation index (CEI) is defined as a quantitative assessment of the VBI system. The numerical parametric studies reveal that (1) the mass ratio of vehicle to bridge is the most sensitive parameter affecting the bridge response; (2) increasing bridge damping can reduce the coupling degree of the VBI system at high speeds; (3) the present quasi-VBI model is an efficient and simple tool to predict the vehicle's response with enough accuracy based on engineering approximation.

Bridging fault detection in cluster based FPGA by using Muller C element

In this work, we propose a testing technique for detecting single stuck-at and bridging faults in the interconnects of the cluster based FPGA. The presence of the feedback-bridging fault, race and glitch poses major challenges to the detection of the fault. The feedback bridging fault has a high ingredient of delay dependent properties due to the variation of the feedback path delay. So we have exploited the concept of asynchronous logic in order to detect the fault. We configure the block under test (BUT) with a pseudo delay independent asynchronous element known as Muller C element. The novelty of this scheme lies in the fact that, it can detect the stuck-at and bridging fault including the feedback bridging fault by a single test configuration. The Xilinx Jbits 3.0 API (Application Program Interface) is used to implement the BISTER (Built-in-self-tester) structure in the FPGA. In comparison to the traditional FPGA development tool (ISE), ‘Jbits’ gives more controllability for which the partial run time reconfiguration of the FPGA is easily achieved.

Wall shear stress hot film sensor for use in gases

The purpose of this work is to present the construction and characterization of a wall shear stress hot film sensor for use in gases made with MEMS technology. For this purpose, several associated devices were used, including a constant temperature feedback bridge and a shear stress calibration device that allows the sensor performance evaluation. The sensor design adopted here is simple, economical and is manufactured on a flexible substrate allowing its application to curved surfaces. Stationary and transient wall shear stress tests were carried on by means of the calibration device, determining its performance for different conditions.

Modeling Feedback Bridging Faults with Non-Zero Resistance

We study the behavior of feedback bridging faults with non-zero bridge resistance in both combinational and sequential circuits. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance. Moreover, the resistance intervals in which a particular behavior is observed are not necessarily contiguous. We demonstrate non-trivial behavior for situations in which a detection seems impossible, namely disabled loops going through a gate with controlling values on its side inputs. We outline the multiple strengths problem which arises due to the fact that a critical bridge resistance depends on the strengths of the signals driving the bridge, which in turn are functions of the number of the on-transistors, these again depending on the bridge resistance, making such a fault very hard to resolve. For sequential circuits, we describe additional difficulties caused by the need to account for implications on bridge behavior, which have originated in the previous time frames. We conclude that the complexity of resistive feedback bridging fault simulation accurate enough to resolve such situations will probably be prohibitively high and propose possible simplifying assumptions. We present simulation results for ISCAS benchmarks using these assumptions with and without taking oscillation into account.

Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits

In this paper we analyze fault behaviors of internal feedback bridging faults. To investigate their behaviors, we use a simple circuit model consisting of 2-input NAND gate and NOT gate. From analysis results, we find that behaviors of internal feedback bridging faults are more complex than those of external feedback bridging faults. We expose that they cause IDDQ-only failure, internal latch and internal oscillation as well as latch and oscillation behavior. These phenomena are caused by the following facts: formation of an electrically conducting feedback loop and connection of the feedback loop with the circuit output depend on input values of the circuit, and the feedback loop is often alive only within the circuit. We also discuss methods for detecting this kind of fault.

Bridge fault diagnosis using stuck-at fault simulation

A new diagnostic fault simulator is described that diagnoses both feedback and nonfeedback bridge faults in combinational circuits while using information from fault simulation of single stuck-at faults. A realistic fault model is used which considers the existence of the Byzantine Generals problem. Sets representing nodes possibly involved in a defect are partitioned based on logic and fault simulation of failing vectors. The approach has been demonstrated for two-line bridge faults on several large combinational benchmark circuits containing Boolean primitives and has achieved over 98% accuracy for nonfeedback bridge faults and over 85% accuracy for feedback bridge faults with good diagnostic resolution.

Logic testing of bridging faults in CMOS integrated circuits

We describe a system for simulating and generating accurate tests for bridging faults in CMOS ICs. After introducing the Primitive Bridge Function, a characteristic function describing the behavior of a bridging fault, we present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridging faults via topological analysis of the feedback-influenced region of the faulty circuit. We present a bridging fault simulation strategy superior to previously published strategies, describe the new test pattern generation system in detail, and report on the system's performance, which is comparable to that of a single stuck-at ATPG system. The paper reports fault coverage as well as defect coverage for the MCNC layouts of the ISCBS-85 benchmark circuits.

Detection of multiple faults using SSFTS in CMOS logic circuits

With the increasing density of CMOS VLSI circuits, it is necessary to test for the combinations of different multiple faults. This paper studies the possibility of using single stuck-at fault test set (SSFTS) to detect multiple faults and their combinations. The paper shows that a single stuck-at-fault test set can detect single and multiple self-feedback bridging faults, combinations of feedback bridging, input bridging and stuck-on faults when current monitoring is done. We also prove that a single stuck-at fault test set can detect the combination of single stuck-open fault and some other faults like bridging and stuck-on faults when both logic and current monitoring are done.

Current testability analysis of feedback bridging faults in CMOS circuits

An exhaustive classification of bridging faults between pairs of logic level circuit nodes and an I/sub DDQ/ testability analysis scheme for these faults are presented in this paper. The case of feedback bridging faults producing oscillations is considered in detail. The testability of such faults is verified through a set of experiments with specially implemented ASIC's.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A katharometer bridge circuit with linearising feedback

A katharometer for determining the concentration of helium in air in the range 0-100% was coupled to an electronic feedback bridge supply circuit. It was found that an optimal feedback gain exists for which the measurement non-linearity reaches a minimum value of 1%, which is 15 times better than with the conventional constant voltage bridge supply.

Detecting I/O and Internal Feedback Bridging Faults

The testing of bridging faults (short circuits) has become increasingly important with the increasing density in VLSI (very large scale integration) chips. Yet very little work has been done in this area. In this correspondence, based on a two-state sequential machine model, we present the conditions for a circuit with feedback bridgings to oscillate and to exhibit stable sequential behavior. It is shown that only two test patterns are sufficient to detect feedback bridging faults between input and output lines of a general combinational network. We derive a simple equation to generate test patterns for detecting feedback bridging faults among internal lines of a general combinational network.

Comments on "Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines"

Theorem 2ii), Theorem 7, and Corollary 5ii) with respect to detection and location of feedback bridging faults in the above paper1 are shown to be incorrect by counterexamples. In addition, some misunderstandings about asynchronous behavior of a faulty network with a feedback bridging are pointed out.

Correction to “detection and location of input and feedback bridging faults among input and output lines”

The following errors should be noted in the above correspondence.

Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines

The study of short circuits between conducting paths (bridging faults) has become increasingly important. Yet very little work has been done in this area. In this paper, conditions for feedback bridging (short circuit) faults to generate oscillation and asynchronous behavior are given for short circuits among input lines and the primary output. The lower and upper bounds on the number of tests for detecting all feedback bridging faults are given. Necessary and sufficient conditions for the undetectability of input bridgings are presented. It is found that any test detecting single bridging fault e will also detect all multiple bridgings containing e. Complete test sets for locating either all input or all feedback bridgings of any multiplicities for networks implementing several classes of functions are given.