With the background of general integrated circuit (IC) feature size shrinking designers to get high performance transistors, Self-Alignment-Double-Patterning (SADP) FinFETetch was widely used in 14/16 nm technologies node and beyond. Rigorous process loading control (CD, profile, depth) in reactive ion etch (RIE) becomes more critical and challenging to ensure precise patterning and to avoid performance degradation among different features.[1]However, it’s quite hard to tackle such notorious loading for its inherent high Te induced ionization in traditional continuous wave (CW) plasmas.Thus, significant improvements in controlling plasma properties in a dry etching reactor are essential to satisfy such stringent requirement. Pulsed plasmas have demonstrated several advantages compared to CW plasmas. By varying the pulse frequency and the duty cycle, pulsed plasma provide additional “control knobs” in controlling critical plasma parameters, such as ion and electron densities, electron temperature, flux and energy of the ions and radicals incident on surface. These critical factors affecting overall on-wafer performance during plasma etching processes at both within wafer and within die levels, etching and deposition, vertical and lateral etch rate, profile control, feature sidewall passivation and plasma damage.[2]In view of characters of pulsed plasma noted above, it appears to be a promising approach to improve RIE-lag loading in SADP fin etch. In this paper, we systematically investigated the influence of both bias pulsed plasma and synchronous pulsed plasma to fin CD, profile (sidewall angle) and depth loading performance among dense and semi-isolated lines. It was found that proper duty cycle and frequency of pulsed power could drastically impact the loading performance. Based on the above learning, we finally delivered the overall solution by introducing synchronous pulsed plasma etch in mandrel and shallow trench isolation (STI) to address the rigorous loading control between dense and isolated patterns. [1] Y. Wang, et al, CSTIC, “Process Loading Reduction on SADP FinFET Etch”, 2015 [2] S. Banna, et al, JVST A, “Pulsed High-density Plasmas for Advanced Dry Etching Process”, 2012
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