Fault-tolerant Processor Arrays Research Articles

Parallel processing for block ciphers on a fault tolerant networked processor array

The computational performance of network-on-chip (NoC) and multi-processor system-on-chip (MPSoC) for implementing cryptographic block ciphers can be improved by exploiting parallel and pipelined execution. In this paper, we present a parallel and pipeline processing method for block cipher algorithms using purely software implementation on an NoC. Algorithms are decomposed into task loops, functions and data flow for parallel and pipeline execution. Tasks are allocated by the proposed mapping strategy to each processing element (PE). In order to provide fault tolerance on nanoscale NoC circuits, we add Hamming error correction code (ECC) encoder and decoder at the network interface. The proposed parallel block cipher algorithm implementation on the fault tolerant NoC is simulated by using networked processor array (NePA), the cycle-accurate SystemC and hardware description language (HDL) model platform. Our parallel software implementation method on a multicore NoC architecture has the advantage of flexibility compared with traditional ASIC solutions. In addition, the simulation result presents that the parallel and pipeline processing approach for software block ciphers can be implemented on various NoC platforms which have different complexities and constraints.

On the pagenumber of trivalent Cayley graphs

Book embedding of graphs is one of the graph layout problem. It is useful for the multiprocessor network layout or the fault-tolerant processor arrays. We show that the trivalent Cayley graphs proposed by Vadapalli and Srimani can be embedded in five pages, and show some additional results on cube-connected cycles.

Fault-tolerant processor arrays based on the 1 1/2 -track switches with flexible spare distributions

A mesh-connected processor array consists of many similar processing elements (PEs) which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, some fault-tolerant issues are necessary to enhance the (fabrication-time) yield and the (run-time) reliability. In this paper, we propose a fault-tolerant reconfigurable processor array using single-track switches like Kung et al.'s model. The reconfiguration process in our model is executed based on the concept of the "compensation path" like Kung et al.'s method, too. In our model, spare PEs are not necessarily put around the array, but are more flexibly put in the array by changing connections between spare PEs and nonspare PEs while retaining the connections among nonspare PEs in the same manner in Kung et al.'s model. The proposed model has such a desirable property that physical distances between logically adjacent PEs in the reconfigured array are within a constant, that is, independent of sizes of arrays. We show that the hardware overhead of the proposed model is a little greater than that of Kung et al.'s model, while the yield of the proposed model is much better than that of Kung et al.'s model.

Fault-tolerant processor arrays using additional bypass linking allocated by Graph-Node coloring

An advanced spare-connection scheme for k-out-of-n redundancy called generalized additional bypass linking is proposed for constructing fault-tolerant massively parallel computers with series-connected, mesh-connected, or tree-connected processing element (PE) arrays. This scheme uses bypass links with wired OR connections to selectively connect the primary PEs to a spare PE in parallel. These bypass links are allocated to the primary PEs by node-coloring of a graph with a minimum inter-node distance of three in order to minimize the number of bypass links (i.e., the chromatic number). The main advantage of this scheme is that it can be used for constructing various k-out-of-n configurations capable of enhanced PE-to-PE communication and broadcast while still achieving strong fault tolerance for these PEs and links. In particular, it enables the construction of optimal r-strongly-fault-tolerant configurations capable of direct k-out-of-n selections by providing r spare PEs and r extra connections per PE for any kind of array when node-coloring with a distance of three is used. This simple spare-circuit structure enhances fault tolerance more than conventional schemes do. The node-coloring patterns were constructed using new node-coloring algorithms and the chromatic numbers were evaluated theoretically. Enhanced PE-to-PE communication and broadcast were achieved by using new fault-tolerant routing algorithms based on the properties of the node-coloring patterns with four or five message transmission steps being optimal configurations with any size array.

Design methodology for systematic derivation of fault-tolerant processor array architectures

A systematic approach for mapping of iterative algorithms into fault-tolerant processor arrays is presented. The initial description of the algorithms is assumed to be Fortran-like nested loops, and it is not required to transform them into any intermediate form, such as UREs. The principles of Lamport's Coordinate Method are employed and regular or piecewise, regular arrays (RA or PRA) can be derived. Moreover, the allocation and the scheduling of the computations are specified by suitable interpretation of the functional behaviour of each loop index. Also, this paper proposes new approaches facilitating fault/defect-tolerant array processor design during the mapping process. An especially suited methodology is fault tolerance via idle PEs.

RECONFIGURATION IN FAULT-TOLERANT 3D MESHES

The [Formula: see text] track model for fault tolerant 2D processor arrays is extended to 3D mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are considered. It is shown that when six directions in the 3D mesh are allowed for compensation paths, then switches with 13 states are needed to preserve the 3D mesh topology after faults. The number of switch states reduces to 7 if only 3 directions are allowed for compensation paths. It is also shown that switch reconfiguration after faults is local in the sense that the state of each switch is uniquely determined by the states of the 2 processors connected to it.

Laying Out Graphs Using Queues

The problem of laying out the edges of a graph using queues is studied. In a k-queue layout, vertices of the graph are placed in some linear order and each edge is assigned to exactly one of the k queues so that the edges assigned to each queue obey a first-in/first-out discipline. This layout problem abstracts a design problem of fault-tolerant processor arrays, a problem of sorting with parallel queues, and a problem of scheduling parallel processors. A number of basic results about queue layouts of graphs are established, and these results are contrasted with their analogues for stack layouts of graphs (the book-embedding problem). The 1-queue graphs (they are almost leveled-planar graphs) are characterized. It is proved that the problem of recognizing 1-queue graphs is NP-complete. Queue layouts for some specific classes of graphs are given. Relationships between the queuenumber of a graph and its bandwidth and separator size are presented. An apparent tradeoff between the queuewidth and the number of queues allowed in layouts of complete binary trees is indicated.

Embedding graphs in books: a survey

Embedding a graph in a book is an arrangement of vertices in a line along the spine of the book and edges on the pages in such a way that edges residing on the same page do not cross. Each graph has many different embeddings in books. The embedding with the minimum number of pages is optimum. This paper is a survey of problems dealing with embedding graphs in books. The computational complexity of the problems is mentioned. Some examples of optimum graph embeddings in books are presented. The problem of embedding a graph in a book is very important from the technical point of view. Optimisation of graph embeddings may be important in several technical applications, e.g. sorting with parallel stacks, fault-tolerant processor arrays design, and layout problems with application to very large scale integration (VLSI).

Detailed modeling and reliability analysis of fault-tolerant processor arrays

A method for the generation of detailed models of fault-tolerant processor arrays, based on stochastic Petri nets (SPNs), is presented. A compact SPN model of the array associates with each transition a set of attributes that includes a discrete probability distribution. Depending on the type of component and the reconfiguration scheme, these probabilities are determined using simulation or closed-form expressions and correspond to the survival of the array given that a number of components required by the reconfiguration process are faulty.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The full-use-of-suitable-spares (FUSS) approach to hardware reconfiguration for fault-tolerant processor arrays

A general approach to hardware recognition is proposed for VLSI/WSI fault-tolerant processor arrays. The technique, called full use of suitable spares (FUSS), uses an indicator vector, the surplus vector, to guide the replacement of faulty processors within an array. Analytical study of the general FUSS algorithm shows that there is a linear relationship between the array size and the area of interconnect required for reconfiguration to be 100% successful. In an instance of FUSS, called simple FUSS, reconfiguration is done by shifting up to or down the surplus vector's entries. The surplus vector is progressively updated after each column is reconfigured. The reconfiguration is successful when the surplus vector becomes null. Simple FUSS is discussed in detail and evaluated. Simulations show that when the number of faulty processors is equal to that of space processors, simple FUSS can achieve a probability of survival as high as 99%. >

A taxonomy of reconfiguration techniques for fault-tolerant processor arrays

Focuses on the characterization and classification of reconfiguration techniques. The techniques are differentiated according to the type of redundancy (time or hardware), allocation of redundancy (local or global), replacement unit, (processor or a set of processors), switching domain (global or local), and switching implementation (switching element, bus, or network). Typical techniques from four major classes-set switching, processor switching, local redundancy, and time redundancy-are reviewed. The proposed taxonomy can be used as a guide for future research in design and analysis of reconfiguration schemes. >

Comment on "Nonplanar VLSI arrays with high fault-tolerance capabilities

In the above-named work (see ibid., vol.38, p.51-7, April 1989), S. Lafiti and A. El-Amawy apply, in a straightforward manner, the method developed by A.D. Singh (1985) to calculate lower bounds for the yield of nonplanar interstitial redundancy topologies of processor arrays with spare processors. In their introduction, they claim that the models suggested by I. Koren and D.K. Pradhan (1987) are highly theoretical since the number of states in the Markov model might be very large and the determination of the transition rates might be intractable. They add that applying some empirical rules, as suggested by Koren and Pradhan (1987), can lead to unrealistic results and may require a large number of computations. They also claim that the model of Koren and Pradhan does not suggest an algorithm to replace faulty elements. They conclude that a simpler model, like the one proposed by Singh, is needed for calculating the yield of fault-tolerant processor arrays. In the present comment, Koren and Pradhan respond to the above comments and attempt to clarify the differences between their yield analysis and that of Singh. >

Design of a self-reconfiguring interconnection network for fault-tolerant VLSI processor arrays

An interconnection network capable of spontaneously reconfiguring a VLSI processor array on detection of faulty processors is presented. Although the reconfiguration process is global, the network control circuitry is localized around each processor and is therefore completely modular. The structure of the control circuitry is fixed and thus independent of the array size or the number of spare processors. The network performance in yield enhancement is analyzed through Monte Carlo simulation. The network effectiveness in using surviving processors is close to that of an ideal network (one capable of tolerating as many faulty processors per row as there are spare processors per row). Strategies involved in testing the fault-tolerant array are also presented. Test circuitry is placed around each of the processors to enable testing of all the processors in parallel. The same circuitry is used to test the interconnection network efficiently. The additional silicon area requirements due to the network and the test circuitries are examined through the design of a prototype fault-tolerant array.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Embedding Graphs in Books: A Layout Problem with Applications to VLSI Design

We study the graph-theoretic problem of embedding a graph in a book with its vertices in a line along the spine of the book and its edges on the pages in such a way that edges residing on the same page do not cross. This problem abstracts layout problems arising in the routing of multilayer printed circuit boards and in the design of fault-tolerant processor arrays. In devising an embedding, one strives to minimize both the number of pages used and the “cutwidth” of the edges on each page. Our main results (1) present optimal embeddings of a variety of families of graphs; (2) exhibit situations where one can achieve small pagenumber only at the expense of large cutwidth; and (3) establish bounds on the minimum pagenumber of a graph based on various structural properties of the graph. Notable in the last category are proofs that (a) every n-vertex d-valent graph can be embedded using $O( dn^{1/ 2} )$ pages, and (b) for every $d > 2$ and all large n, there are n-vertex d-valent graphs whose pagenumber is at least \[ \Omega \left( \frac{n^{1/ 2 - 1/d}}{\log^2 n} \right). \]

Minced trees, with applications to fault-tolerant VLSI processor arrays

We derive here a lower bound on the number of edgesf(c, d) that one must remove from a depth-d complete binary tree in order to partition the tree intoc equal size pieces (to within rounding). We show that for the sequence of integersc l = def 3× 2 l $$f\left( {c_l ,d} \right) \geqslant \frac{{c_l }}{{16}}\left( {d - 2l - {{19} \mathord{\left/ {\vphantom {{19} 6}} \right. \kern-\nulldelimiterspace} 6}} \right)$$ . We then apply this bound to a graph-embedding problem related to the design of fault-tolerant VLSI processor arrays. An earlier study has exhibited a fault-tolerant implementation of arbitrary binary trees, using a particular design strategy. We show here that that implementation is optimal in area consumption (to within constant factors) among designs using that strategy, even when the array to be simulated must have the structure of acomplete binary tree.

A Hypergraph Model for Fault-Tolerant VLSI Processor Arrays

We study here a formal version of a strategy for constructing fault-tolerant VLSI processor arrays in an environment of wafer-scale integration. The strategy achieves tolerance to faults by running buses past the implemented PE's and interconnecting the fault-free ones into an array of the desired structure by having PE's tap into the bank of buses. Earlier studies [12] have shown this strategy to be competitive with more familiar strategies, particularly given the availability of laser-welding technology. We study here fault-tolerant implementation of linear arrays and tree-structured arrays, deriving both upper and lower bounds on the area required to lay out the fault-tolerant arrays. We also consider briefly the issue of wire lengths.

On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays

Fault-tolerance is undoubtedly a desirable property of any processor array. However, increased design and implementation costs should be expected when fault-tolerance is being introduced into the architecture of a processor array. When the processor array is implemented within a single VLSI chip, these cost increases are directly related to the chip silicon area. Thus, the increase in area should be weighed against the improved performance of the gracefully degrading fault-tolerant processor array. In addition, a larger chip area might reduce the wafer yield to an unaceptable level making the use of fault-tolerant VLSI processor arrays impractical. The objective of this paper is to devise performance measures for the evaluation of the effectiveness and area utilization of various fault-tolerant techniques. Another goal is to analyze the reduction in wafer yield and investigate the possibility of yield enhancement through redundancy.