Fat-tree Network Research Articles

A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip

Network-on-Chip (NoC) interconnect fabrics are categorized according to trade-offs among latency, throughput, speed, and silicon area, and the correctness and performance of these fabrics in Field-Programmable Gate Array (FPGA) applications are assessed through experimentation and simulation. In this paper, we propose a consistent parametric method for evaluating the FPGA performance of three common on-chip interconnect architectures namely, the Mesh, Torus and Fat-tree architectures. We also investigate how NoC architectures are affected by interconnect and routing parameters, and demonstrate their flexibility and performance through FPGA synthesis and testing of 392 different NoC configurations. In this process, we found that the Flit Data Width (FDW) and Flit Buffer Depth (FBD) parameters have the heaviest impact on FPGA resources, and that these parameters, along with the number of Virtual Channels (VCs), significantly affect reassembly buffering and routing and logic requirements at NoC endpoints. Applying our evaluation technique to a detailed and flexible cycle accurate simulation, we drive the three NoC architectures using benign (Nearest Neighbor and Uniform) and adversarial (Tornado and Random Permutation) traffic patterns with different numbers of VCs, producing a set of load–delay curves. The results show that by strategically tuning the router and interconnect parameters, the Fat-tree network produces the best utilization of FPGA resources in terms of silicon area, clock frequency, critical path delays, network cost, saturation throughput, and latency, whereas the Mesh and Torus networks showed comparatively high resource costs and poor performance under adversarial traffic patterns. From our findings it is clear that the Fat-tree network proved to be more efficient in terms of FPGA resource utilization and is compliant with the current Xilinx FPGA devices. This approach will assist engineers and architects in establishing an early decision in the choice of right interconnects and router parameters for large and complex NoCs. We demonstrate that our approach substantially improves performance under a large variety of experimentation and simulation which confirm its suitability for real systems.

Mixed-grained CMOS field programmable analog array for smart sensory applications

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays (FPAAs), which are the analogue counterparts of Field Programmable Gate Arrays (FPGAs). In this paper, we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem. The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks (CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers (CCAs). The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors. To reduce the nonideal parasitic effects and save area, the fat-tree interconnection network is adopted in this FPAA. The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter. The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth. The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency. And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

The importance of switch dimension for energy-efficient datacenter design

Saving power in datacenter networks has become a pressing issue as the networks tend to consume steady power even when many servers may be idle during periods of low activity. While in operation, ElasticTree and CARPO can save power consumed by a fat-tree network by using sleep mode, where some components such as ports and switches are turned off when traffic demand in the network is relatively moderate. In this paper, we propose a new approach by exploring the design stage of a datacenter network, and focus on how to choose the right switch size that can potentially save the most power during the expected operation of the network. We also consider speed scaling where the power of a switch can be varied by adjusting its processing rate according to its traffic demand. We first perform analysis and simulation to investigate the power-saving performance of different switch sizes, power-saving modes and traffic demand patterns. Based on fat-tree networks with sleep mode and supporting a fixed number of servers, our findings reveal that deploying a large number of small switches is more power-efficient than a small number of large switches when the traffic demand is relatively moderate or when servers exchanging traffic are in close proximity. With speed scaling, the reverse is generally true. We confirm our findings using traffic traces from a production datacenter. Our approach for studying the fat-tree topology design is also extendible to other types of datacenter network topologies.

Switch sizing for energy-efficient datacenter networks

Saving power in datacenter networks has become a pressing issue. ElasticTree and CARPO fat-tree networks have recently been proposed to reduce power consumption by using sleep mode during the operation stage of the network. In this paper, we address the design stage where the right switch size is evaluated to maximize power saving during the expected operation of the network. Our findings reveal that deploying a large number of small switches is more power-efficient than a small number of large switches when the traffic demand is relatively moderate or when servers exchanging traffic are in close proximity. We also discuss the impact of sleep mode on performance such as packet delay and loss.

Evaluating SDN based Rack-to-Rack Multi-path Switching for Data-center Networks

Software defined networking becomes more and more popular in the networking community, but is still missing its triumphal procession into existing networks. Especially data-centers could benefit from this evolutionary network paradigm and get rid of many legacy parts with are still blocking the evolution how their networks are working in general.In this paper we will present an approach, use-case and performance evaluation as well, for the integration of software defined networking applications in data-centers. This approach addresses a sub topic or more precisely a single software defined networking application for enhancing inter rack communication by involving the top-of-rack and aggregation switches in a common fat-tree network topology.The basic aim is to provide some sort of load distribution mechanism on the afore mentioned network layers by using a flow based load sharing procedure with layer two multi-path. The evaluation will show that this is increasing the throughput in a rack-to-rack data exchange scenario.

Fast pattern-specific routing for fat tree networks

In the context of eXtended Generalized Fat Tree (XGFT) topologies, widely used in HPC and datacenter network designs, we propose a generic method, based on Integer Linear Programming (ILP), to efficiently determine optimal routes for arbitrary workloads. We propose a novel approach that combines ILP with dynamic programming, effectively reducing the time to solution. Specifically, we divide the network into smaller subdomains optimized using a custom ILP formulation that ensures global optimality of local solutions. Local solutions are then combined into an optimal global solution using dynamic programming. Finally, we demonstrate through a series of extensive benchmarks that our approach scales in practice to networks interconnecting several thousands of nodes, using a single-threaded, freely available linear programming solver on commodity hardware, with the potential for higher scalability by means of commercial, parallel solvers.

Fast pattern-specific routing for fat tree networks

In the context of eXtended Generalized Fat Tree (XGFT) topologies, widely used in HPC and datacenter network designs, we propose a generic method, based on Integer Linear Programming (ILP), to efficiently determine optimal routes for arbitrary workloads. We propose a novel approach that combines ILP with dynamic programming, effectively reducing the time to solution. Specifically, we divide the network into smaller subdomains optimized using a custom ILP formulation that ensures global optimality of local solutions. Local solutions are then combined into an optimal global solution using dynamic programming. Finally, we demonstrate through a series of extensive benchmarks that our approach scales in practice to networks interconnecting several thousands of nodes, using a single-threaded, freely available linear programming solver on commodity hardware, with the potential for higher scalability by means of commercial, parallel solvers.

Guest Editors’ Introduction to Special Issue on Advances in DSP System Design

The constant advances in IC technologies have introduced new challenges for implementations and design methodologies; higher integration level allows more complex systems to be implemented but on the other hand implementations often have strict constraints on power consumption. These challenges are present in signal processing systems implying the need to improve design methods and find more efficient algorithm-architecture optimizations. This special issue contains a selection of recent papers on design and implementation of signal processing systems ranging from circuit level architectures to scheduling methods and from application-specific architectures to implementations on many-core systems. In Data Center Switch for Load Balanced Fat-Trees, Lai, and Chiu demonstrate a fault tolerant switch IC operating at the maximum rate of 5.8 Gbps per channel. This work employs a load-balanced fat-tree architecture that does not consume all of its bandwidth even under heavy traffic. When there are broken links or faulty switches in the network even in heavy traffic load situations, available bandwidth remains in every connection pattern and alternative paths are provided to re-route the traffic. Fault tolerance capability evaluations of link or switch faults in the fattree network are given to support the presented idea, and a 4×4 Banyan type switch IC is developed as the commodity switch for building the fault tolerant fat-tree data center networks. Lee and Sung propose a cell-to-cell interference (CCI) cancellation technique for multi-level NAND flash memory in their paper Least Squares Based Coupling Cancellation for MLC NAND Flash Memory with a Small Number of Voltage Sensing Operations. Their two-step algorithm consists of training and then interference removal performed during the page read operation. A least-squares adaptive CCI canceller is developed and optimal quantization schemes are studied. Experimental results show a significant BER improvement despite a low number of voltage sensing operations. In A Fast Recursive Algorithm and Architecture for Pruned Bit-Reversal Interleavers, Mansour describes an algorithm and architecture for implementing interleavers used in communications applications such as errorcorrecting codes (turbo codes) and bit-interleaved coded modulation. A mathematical formulation for developing flexible-length interleavers is developed along with a study of permutation statistics. Practical examples of implementations of parallel interleavers are provided. In Highly Parallelable Bidimensional Median Filter for Modern Parallel Programming Models, Sanchez and Rodriguez present efficient parallel implementation methods for median filtering. The authors implement their previous work on the parallel ccdf-based median filter (PCMF) on a GPU (Graphics Processing Unit), and show that the proposed median filtering algorithm is efficient and can outperform other generic median filters for the GPU. The proposed algorithm is implemented in three parallel programming models: SIMD Intel, multi-core Intel with SIMD, and SIMT (CUDA). Additionally they make use of the salt & pepper noise model to improve the image reconstruction quality with a small performance impact. J. Takala (*) Department of Pervasive Computing, Tampere University of Technology, Tampere, Finland e-mail: jarmo.takala@tut.fi

Data Center Switch for Load Balanced Fat-Trees

With the growing of cloud computing, the need of computing power no longer can be satisfied with a few powerful servers or small scale parallel computer systems. More and more servers are connected together as a data center network. Then, fault tolerance becomes an import issue when building a massive data center network. Currently, many researches focus on building fat-tree data center networks. In this paper, we propose a load balanced fat-tree architecture with uniform mapping connection patterns to provide higher fault tolerance capability for heavy traffic load networks. Two fault tolerated 4 ? 4 banyan type switch designs are introduced to improve the fault tolerance capability of fat-tree networks. Finally, fault tolerance capability evaluations of link or switch faults in fat-tree network are given to support our idea, and a 4 ? 4 banyan type switch IC is demonstrated as the commodity switch for building the fault tolerant fat-tree data center networks. The 4 ? 4 banyan type switch IC is fabricated in 90 nm CMOS technology, and the maximum operation rate of the IC is 5.8 Gbps per channel or 23.2 Gbps total data rate with only 23 ps peak-to-peak jitter.

MODELING THE PERFORMANCE OF DIRECT NUMERICAL SIMULATION ON PARALLEL SYSTEMS

Direct Numerical Simulation (DNS) is an important application area that is expected to use large fractions of future large-scale simulations. In this work we develop, validate and use a performance model of the combustion code, DNS3D, to explore achieved performance on current parallel systems. The performance model is developed from a thorough analysis of the application. Its key computation characteristics are coupled with the performance characteristics of the system using an parameterized analytical model. The model is validated on three parallel systems: a muti-core AMD Opteron based system with an Infiniband fat-tree network, an IBM Power5+ system with an HPS fat-tree network, and an IBM Power7 system with a direct connect network. The performance model is shown to achieve high prediction accuracy on all three systems. We illustrate how the model can be used to explore impact of changes in either the system or the application. It is used to both analyze the achieved performance on these systems as well as to explore the possible benefits of further optimizing DNS3D's main computational kernel of one-dimensional FFTs, or in possibly overlapping communication with computation.

Efficient and Scalable Hardware-Based Multicast in Fat-Tree Networks

This article presents an efficient and scalable mechanism to overcome the limitations of collective communication in switched interconnection networks in the presence of faults. Considering that current trends in supercomputing are moving toward massively parallel computers, with many thousands of components, reliability becomes a challenge. In such scenario, fat-tree networks that provide hardware support for collective communication suffer from serious performance degradation due to the presence of, even, a single faulty node. This paper describes a new mechanism to provide high-performance collective communication in such situations. The feasibility of the proposed technique is formally demonstrated. We present the design of a new hardware-based routing algorithm for multicast, that is at the base of our proposal. The proposed mechanism is implemented and experimentally evaluated. Our experimental results show that hardware-based multicast trees provide an efficient and scalable solution for collective communication in fat-tree networks, significantly outperforming traditional solutions.

A collision model for randomized routing in fat-tree networks

We present a proof that in a model of a fat-tree network with n processing nodes m ⩽ n messages with randomly chosen, distinct sources and independently and randomly chosen destinations are delivered within O ( lg m ) delivery rounds with high probability. More succinctly, we establish that m messages are delivered in O ( lg m + ln 1 / ε ) delivery rounds with probability 1 - ε for any small ε > 0 . Unlike previously applied proof methods, we use an approximating model for the collision behavior of the network amenable to concise yet simple theoretical analysis. We justify the accuracy of the approximation by means of behavioral simulations based on a gate-level implementation of a fat-tree network.

A Comparison of Asymptotically Scalable Superscalar Processors

The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path lengths of many components in existing implementations grow as Θ(n 2 ) where n is the fetch width, the issue width, or the window size. This paper describes two scalable processor architectures, Ultrascalar I and Ultrascalar II, and compares their VLSI complexities (gate delays, wire-length delays, and area.) Both processors are implemented by a large collection of ALUs with controllers (together called execution stations ) connected together by a network of parallel-prefix tree circuits. A fat-tree network connects an interleaved cache to the execution stations. These networks provide the full functionality of superscalar processors including renaming, out-of-order execution, and speculative execution. The difference between the processors is in the mechanism used to transmit register values from one execution station to another. Both architectures use a parallel-prefix tree to communicate the register values between the execution stations. Ultrascalar I transmits an entire copy of the register file to each station, and the station chooses which register values it needs based on the instruction. Ultrascalar I uses an H-tree layout. Ultrascalar II uses a mesh-of-trees and carefully sends only the register values that will actually be needed by each subtree to reduce the number of wires required on the chip. The complexity results are as follows: The complexity is described for a processor which has an instruction-set architecture containing L logical registers and can execute n instructions in parallel. The chip provides enough memory bandwidth to execute up to M(n) memory operations per cycle. (M is assumed to have a certain regularity property.) In all the processors, the VLSI area is the square of the wire delay. Ultrascalar I has gate delay O(log n) and wire delay \tauwires = \Theta(\sqrt{n}L) if $M(n)$ is $O(n^{1/2-\varepsilon})$, \tauwires = \Theta(\sqrt{n}(L+\log n)) if $M(n)$ is $\Theta(n^{1/2})$, \tauwires = \Theta(\sqrt{n}L+M(n)) if $M(n)$ is $\Omega(n^{1/2+\varepsilon})$ for ɛ>0 . Ultrascalar II has gate delay Θ(log L+log n) . The wire delay is Θ(n) , which is optimal for n=O(L) . Thus, Ultrascalar II dominates Ultrascalar I for n=O(L 2 ) , otherwise Ultrascalar I dominates Ultrascalar II. We introduce a hybrid ultrascalar that uses a two-level layout scheme: Clusters of execution stations are layed out using the Ultrascalar II mesh-of-trees layout, and then the clusters are connected together using the H-tree layout of Ultrascalar I. For the hybrid (in which n≥ L ), the wire delay is Θ(\sqrt nL+M(n)) , which is optimal. For n≥ L , the hybrid dominates both Ultrascalar I and Ultrascalar II. We also present an empirical comparison of Ultrascalar I and the hybrid, both layed out using the Magic VLSI editor. For a processor that has 32 32-bit registers and a simple integer ALU, the hybrid requires about 11 times less area.

Optimal High-Performance Parallel Text Retrieval via Fat-Trees

We present here a high-performance parallel free-text retrieval method for multiple text queries using the Vector Space Model. Our method employs the fat-tree area universal routing network for connecting the processors of a parallel machine, however (in its general form) it could also be efficiently applied over any other high-bandwidth network of processors or workstations. We provide a theoretical analysis of our technique which shows it is excessively efficient and clearly superior (concerning both the amortized processing times and the average waiting times per query) to parallel text retrieval methods for single queries (e.g., based on binary trees). Moreover, we prove our method to be optimal with respect to the execution of all the implied communication tasks on ideal fat-trees. We also experimentally demonstrate the high performance and superiority of our technique via suitable embeddings of ideal fat-trees on realistic two-dimensional mesh-oriented parallel machines (e.g., the GCel Parsytec machine) and via the use of the large-scale TREC document collections. Note that the fat-tree can simulate any other network of the same hardware with only a polylogarithmic loss of efficiency.

Design and performance analysis of the Practical Fat Tree Network using a butterfly network

The Practical Fat Tree Network (PFN) is proposed as an efficient interconnection structure for parallel processing computers using a butterfly network. It satisfies the concept of volume universality from Leiserson's theoretical fat tree network [1]. In the fat tree network, the locality of input traffic is a very important factor because it has significant effects on performance. The proposed performance model effectively highlights this locality factor. Performance is analyzed according to varing input traffic loads and buffer sizes. The accuracy of the model is confirmed by comparing its results with those from simulation. The proposed model is found to be very accurate. Although the PFN is a dynamic connection network, it shows low delay and high throughput for the applications that have locality.

Universal wormhole routing

We examine the wormhole routing problem in terms of the "congestion" c and "dilation" d for a set of packet paths. We show, with mild restrictions, that there is a simple randomized algorithm for routing any set of P packets in O(cd/spl eta/+d/spl eta/ log P) time with high probability, where L is the number of flits in a packet, and /spl eta/=min {d, L}; only a constant number of flits are stored in each queue at any time. Using this result, we show that a fat tree network of area /spl ominus/(A) can simulate wormhole routing on any network of comparable area with O(log/sup 3/ A) slowdown, when all worms have the same length. Variable length worms are also considered. We run some simulations on the fat tree which show that not only does wormhole routing tend to perform better than the more heavily studied store and forward routing in this context, but that performance superior to our provable bound is attainable in practice.