Fast Fourier Transform Length Research Articles

Simple and precise characterization of differential modal group delay arising in few-mode fiber.

In this Letter, we propose a simple and high-precision differential modal group delay (DMGD) characterization method for few-mode fibers (FMF) by using the frequency-modulated continuous wave. Since the detected signals are located at the low-frequency range, our DMGD characterization method waives the use of expensive equipment, such as vector network or optical spectrum analyzers. Due to the high linearity of the used Mach-Zehnder modulator, our DMGD measurement is free from the complex auxiliary interferometer, leading to an improvement of characterization precision. Meanwhile, we propose a novel spectrum recovery algorithm to overcome the shortcoming that the traditional fast Fourier transform (FFT) method is incapable to deal with spectrum features arising in a periodic signal. Therefore, the characterization precision is no longer limited by the FFT length. When a commercial 23299.8 m two-mode fiber is used in the experiment, the DMGD measurement of LP11 mode relative to LP01 mode has a high precision of ±0.007ps/m over the C-band. Our proposed method shows the potential for characterizing the wavelength-dependent DMGD of FMF with more than two LP modes.

Efficiency Near the Edge: Increasing the Energy Efficiency of FFTs on GPUs for Real-Time Edge Computing

The Square Kilometre Array (SKA) is an international initiative for developing the world's largest radio telescope with a total collecting area of over a million square meters. The scale of the operation, combined with the remote location of the telescope, requires the use of energy-efficient computational algorithms. This, along with the extreme data rates that will be produced by the SKA and the requirement for a real-time observing capability, necessitates in-situ data processing in an edge style computing solution. More generally, energy efficiency in the modern computing landscape is becoming of paramount concern. Whether it be the power budget that can limit some of the world's largest supercomputers, or the limited power available to the smallest Internet-of-Things devices. In this paper, we study the impact of hardware frequency scaling on the energy consumption and execution time of the Fast Fourier Transform (FFT) on NVIDIA GPUs using the cuFFT library. The FFT is used in many areas of science and it is one of the key algorithms used in radio astronomy data processing pipelines. Through the use of frequency scaling, we show that we can lower the power consumption of the NVIDIA V100 GPU when computing the FFT by up to 60% compared to the boost clock frequency, with less than a 10% increase in the execution time. Furthermore, using one common core clock frequency for all tested FFT lengths, we show on average a 50% reduction in power consumption compared to the boost core clock frequency with an increase in the execution time still below 10%. We demonstrate how these results can be used to lower the power consumption of existing data processing pipelines. These savings, when considered over years of operation, can yield significant financial savings, but can also lead to a significant reduction of greenhouse gas emissions.

Hardware chip performance analysis of different FFT architecture

ABSTRACT The Fast Fourier Transform (FFT) is one of the most important algorithm used in digital signal processing (DSP) and digital communication applications to compute fast operations. FFT and IFFT is widely used in modulation and demodulation schemes such as Orthogonal Frequency Division Multiplexing (OFDM), TV broadcasting (DVD), Digital radio broadcasting (DVB) etc. The different FFT processor architectures are used for several applications. The Xilinx ISE tool has FFT Core, which can be directly used for several applications. FFT support four types of architectures: Radix-2 lite burst I/O, Radix-2 burst I/O, Radix-4 burst I/O and Pipelined I/O. The research article focuses on the hardware chip performance analysis of the variable length FFT processor architectures on Field Programmable Gate Array (FPGA) platform using VHDL programming in which FFT length varies from 8 point to 65,536 point. The input data stream is considered of 8-bit, 16-bit and 32-bit. The estimated hardware chip performance parameters are DSP Slices and block RAM. The timing parameter are transform cycles and frequency. It is estimated that radix-2 lite burst I/O performs better in terms of hardware resource utilisation on FPGA and pipelined hardware architecture performs better in terms of transform cycles in comparison to other FFT architectures. The decoded 1024-point FFT signal is observed in Xilinx ISE software integrated Chipscope Pro-Analyzer. The analysis predicts about the best-suited FFT hardware architecture when the designer is going to design the hardware chip on FPGA platform for several applications.

Spectral Line Registration Backend Based on USRP X300 Software Defined Radio

This paper presents implementation of spectrometer based on off-the-shelf software defined radio (SDR) Ettus Research USRP X300 equipped with TwinRX daughterboard. Parallelized software, employing Fast Fourier Transform (FFT), is developed which allows two channel spectrum processing in real time with bandwidths up to 50[Formula: see text]MHz per channel, sample resolution of 14 bits and FFT lengths up to 32k points. Measured Allan stability time of the spectrometer is at least 750 sin laboratory environment. Software has network server-type interface that allows to conveniently integrate the spectrometer in radio telescope observation control and monitoring system with versatility of SDR allowing to implement various observation modes, for example, total power detection functionality with high frequency selectivity, which allows to carry continuum amplitude calibration in presence of near-by radio frequency interference. Presented spectrometer has been successfully integrated and used at RT-32 and RT-16 radio telescopes of Ventspils International Radio Astronomy Centre.

PARALLEL PIPELINED MULTI RADIX VARIABLE LENGTH FAST FOURIER TRANSFORM ARCHITECTURE

There is an enormous demand for high speed data communication or high speed internet using Long Term Evolution (LTE) or LTE-Advanced communication methods. To achieve the high speed data rate in the receiver side, it is necessary to achieve high throughput in the Fast Fourier transform (FFT) architecture. Hence there is demand to improve the throughput of the FFT architectures used for high speed data communication. The FFT architecture is designed and optimized for LTE-A applications. However, the high throughput has been achieved by sacrificing hardware resources of the Field Programmable Gate Array (FPGA). Many fixed and variable length FFT processors are proposed by the researchers with improved performance focusing either on algorithmic modifications, novel architectural optimizations or radix selection. Among these FFT processors, the goal and main objectives of this paper are: 1. To design and implement a pipelined FFT architecture to give high throughput for LTE-A MIMO applications 2. To develop an intellectual property (IP) core for FFT computation with variable FFT size 3. To propose a parallel implementation to increase the performance of LTE-A baseband processing system. In an Orthogonal Frequency Division Multiplexing (OFDM) baseband communication system, FFT operation is one of the highest computationally serious tasks which directly influence the communication system performance factor. The baseband hardware has to be capable as well as efficient enough to calculate FFT in specific timing restrictions. Thus, the parallel pipelined multi radix Variable Length FFT architectures for LTE-A Multiple-Input-Multiple-Output (MIMO) applications have been designed. The proposed FFT architecture delivers a throughput of 550 MSPS at the maximum clock rate of 550 MHz. The proposed FFT support the FFT length of 64, 128, 256, 512, 1024 and 2048 for LTE-Advanced MIMO standard. The proposed FFT architecture has been implemented in Xilinx Artix-7 FPGA device and the performance metrics have been analysed. Even though the proposed FFT architecture consumes additional Block-RAMs (BRAM) and quite an amount of Xilinx-Xtreme Digital Signal Processor (DSP)/ DSP48 resources, the Power Delay Product (PDP) of the proposed FFT is excellent compared to the existing FFT architectures. The proposed multi radix mixed 2/3/5 parallel pipelined 2048 point FFT architectures exhibits very less latency of 11.382 µs at 550 MHz clock frequency compared to the existing system with the latency of 56.88 µs at 200 MHz clock frequency. Moreover, the designed FFT architecture utilizes 96 Xilinx Xtreme DSP blocks 25040 clock cycles to complete the FFT operation with an excellent throughput of 2200 MSPS with FFT computation time of 45.528 µs at the clock frequency of 550 MHz for the 4x4 MIMO- OFDM architecture. Therefore, the designed FFT provides high throughput rate in order to meet the modern wireless standard specifications. The proposed FFT architecture outperforms well in terms high throughput, low latency and better PDP with extra hardware as trade-off for both for Single FFT and for MIMO technology.

Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data

Efficient computation of real-valued fast Fourier transform (RFFT) has received significant attention in recent years due to its several applications in conventional digital signal processing and other emerging areas. In-place RFFT architectures are gaining popularity due to their lower hardware complexity compared with pipeline architectures. But the scaling of in-place RFFT architecture for higher lengths and higher throughput is a challenging issue due to increasing memory access conflict and higher memory bandwidth requirement. In this paper, a design approach is presented to develop an area-delay and energy-efficient architecture for in-place RFFT. Generally, an in-place fast Fourier transform (FFT) structure consists of a butterfly block which performs a set of butterfly operations in every clock cycle. From complexity analysis we find that in-place FFT structures with larger butterfly blocks are more efficient in terms of area-time complexity and energy consumption. The resolution of memory access conflict is however more challenging for higher butterfly block sizes. Therefore, we have analyzed the data-flow and memory footprint of in-place RFFT architectures for different throughput requirements, and based on that, we have proposed here a strategy to partition the storage unit into several banks of smaller sizes (without increasing the overall memory size) to resolve the memory access conflicts by concurrent data-swapping between the banks. Synthesis result shows that the proposed structure with butterfly block of size 4 and 8 involves (~44% and ~57%) less area-delay product and (~54% and ~57%) less energy per sample than those of existing similar structure on average for different FFT lengths, respectively.

FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems

The transmission rate in current passive optical networks can be increased by employing Orthogonal Frequency Division Multiplexing (OFDM) modulation. The computational kernel of this modulation is the fast Fourier transform (FFT) operator, which has to achieve a very high throughput in order to be used in optical networks. This paper presents the implementation in an FPGA device of a variable-length FFT that can be configured in run-time to compute different FFT lengths between 16 and 1024 points. The FFT reaches a throughput of 10 GS/s in a Virtex-7 485T-3 FPGA device and was used to implement a 20 Gb/s optical OFDM receiver.

VLSI design of low‐cost and high‐precision fixed‐point reconfigurable FFT processors

Fast Fourier transform (FFT) plays an important role in digital signal processing systems. In this study, the authors explore the very large-scale integration (VLSI) design of high-precision fixed-point reconfigurable FFT processor. To achieve high accuracy under the limited wordlength, this study analyses the quantisation noise in FFT computation and proposes the mixed use of multiple scaling approaches to compensate the noise. In addition, a statistics-based optimisation scheme is proposed to configure the scaling operations of the cascaded arithmetic blocks at each stage for yielding the most optimised accuracy for a given FFT length. On the basis of this approach, they further present a VLSI implementation of area-efficient and high-precision FFT processor, which can perform power-of-two FFT from 32 to 8192 points. By using the SMIC 0.13 μ m process, the area of the proposed FFT processor is 27 m m 2 with a maximum operating frequency of 400 MHz. When the FFT processor is configured to perform 8192-point FFT at 40 MHz, the signal-to-quantisation-noise ratio is up to 53.28 dB and the power consumption measured by post-layout simulation is 35.7 mW.

A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes

This paper presents the design and implementation of memory-based fast Fourier transform (FFT) processors with generalized efficient, conflict-free address schemes. We unified the conflict-free address schemes of three different FFT lengths, including the single-power points, the common nonsingle-power points, and the nonsingle-power points applied with a prime factor algorithm. Though the three cases differ in terms of decomposition, they are all compatible with memory-based architecture by the way of the proposed address schemes. Moreover, the decomposition algorithm utilizes a method, named high-radix–small-butterfly (HRSB), to decrease the computation cycles and eliminate the complexity of the processing engine. In addition, an efficient index generator, a simplified multipath delay commutator engine, and a unified Winograd Fourier transform algorithm butterfly core were also designed. We designed two FFT examples in long-term evolution system to verify the availability of the address scheme, including a 2n (128–2048)-point FFT unit and a 35 different point (12–1296) DFT unit. Compared with previous works with similar address schemes, this paper supports more generalized lengths and achieves more flexible throughput.

Low‐cost memory data scheduling method for reconfigurable FFT bit‐reversal circuits

A low-cost memory data scheduling method based on two N/2-depth single-port memories is proposed for reconfigurable fast Fourier transform (FFT) bit-reversed data reordering tasks. To make single-port memories have the equivalent ability to read and write data simultaneously, two types of read and write address generation methods are proposed. Based on the proposed data scheduling method, the bit-reversal circuits are designed for continuous data reordering tasks. The proposed bit-reversal design is implemented for a maximum 8 k flexible length FFT processor. Compared with the other two conventional methods, the proposed bit-reversal method can reduce memory area cost by 53.8 and 46.1%, respectively.

CORDIC-based VLSI architecture for real time implementation of flat top window

Since decades, popular window techniques such as Hanning, Hamming, Blackman and Flat top window have been used to minimize unwanted effects like spectral leakage and scalloping losses due to direct truncation of signals before fast Fourier transform (FFT) processor. Conventionally, software and further ROM based implementation of aforesaid window functions have been adopted for real time applications where throughput in the case of software implementation and flexibility in the case of ROM based implementation are the main constraints. Recently, variable length FFT architectures to support wide range of applications in the domain of signal, image and communication system have been developed which demand variable length window architectures. To the knowledge of authors, window techniques such as Hanning, Hamming and Blackman are addressed for real time VLSI implementation; however one of the popular window technique, i.e. flat top window has not been addressed for efficient VLSI implementation. In this context, authors in this paper have proposed a novel, flexible and hardware efficient VLSI architecture for flat top window using CORDIC (Co-ordinate rotation digital computer) along with control units to ensure high throughput. This proposed VLSI architecture for implementing flat top window function is prototyped on commercially available FPGA (Field Programmable Gate Array) device, i.e. Spartan 3E XC3S500E. The first order analysis along with implementation results and error analysis of proposed architecture are highlighted.

Comparative Study of Influence of Noise on Power Frequency Estimation of Sine wave Using Interpolation FFT

This paper compares performances of frequency estimations provided by different interpolation fast Fourier transform (FFT) algorithms under white Gaussian noises. Firstly, accuracies of frequency estimation algorithms are evaluated by deriving analytical expressions of variances of frequency estimation. Then, theoretical results are validated by means of computer simulations. It is shown that the trade-off between biases and variances of frequency estimation is unavoidable. From both theoretical and simulation results, it can be concluded that variances of frequency estimation are proportional to the noise variance and inverse proportional to the length of FFT.

MPFFT: An Auto-Tuning FFT Library for OpenCL GPUs

Fourier methods have revolutionized many fields of science and engineering, such as astronomy, medical imaging, seismology and spectroscopy, and the fast Fourier transform (FFT) is a computationally efficient method of generating a Fourier transform. The emerging class of high performance computing architectures, such as GPU, seeks to achieve much higher performance and efficiency by exposing a hierarchy of distinct memories to software. However, the complexity of GPU programming poses a significant challenge to developers. In this paper, we propose an automatic performance tuning framework for FFT on various OpenCL GPUs, and implement a high performance library named MPFFT based on this framework. For power-of-two length FFTs, our library substantially outperforms the clAmdFft library on AMD GPUs and achieves comparable performance as the CUFFT library on NVIDIA GPUs. Furthermore, our library also supports non-power-of-two size. For 3D non-power-of-two FFTs, our library delivers 1.5x to 28x faster than FFTW with 4 threads and 20.01x average speedup over CUFFT 4.0 on Tesla C2050.

The sliced trispectrum fluctuation characteristics and flow pattern representation of the nitrogen-water two-phase flow of small channel

A new method of nonlinear analysis is proposed by combining the sliced trispectrum method with the fluctuation characteristics, and the influences of the length of the time sequence and fast Fourier transform (FFT) on the fluctuation characteristic value of sliced trispectrum are discussed. It is found that in the absence of noise, the length of sequence and FFT are proportional to the vector distance value; in the presence of noise, it is approximate inversely related. In order to test the anti-noise ability and characterize complexity ability of the fluctuation characteristics method, the proposed method is applied to fractal sequence (Brown), chaotic sequence (Lorenz) and periodic sequence (sine signal). The results show that compared with other power spectral method, the method of the fluctuation characteristics has good noise immunity of fractal sequence, and the anti-noise ability is relatively weak with periodic sequence; but the fluctuation characteristic theory of sequence internal complexity representation has a good effectiveness. On this basis, the differential pressure signals of nitrogen-water two-phase flow in small rectangular channel (w×h=2 mm×0.81 mm) are studied. By analyzing the differential pressure sliced trispectrum of flow patterns, the secondary coupling phenomenon of main oscillation mode of different flow patterns is established. The fluctuation characteristic values of the sliced trispectrum of different flow patterns are extracted to accurately identify the typical flow patterns of small channel nitrogen-water two-phase flow. At the same time, the fluctuation characteristic theory can be used to provide a useful exploration for the further investigation of flowing mechanism of multi-phase flows.

Generic Mixed-Radix FFT Pruning

Compared with traditional Fast Fourier Transform (FFT) algorithms, FFT pruning is more computationally efficient in those cases where some of the input values are zero and/or some of the output components are not needed. In this letter, a novel pruning scheme is developed for mixed-radix and high-radix FFT pruning. The proposed approach is applicable over a wide range of FFT lengths and input/output pruning patterns. In addition, it can effectively employ the benefits of high-radix FFT algorithms that have lower computational complexity.

Modal identification of Shanghai World Financial Center both from free and ambient vibration response

The Shanghai World Financial Center (SWFC), a currently built super high-rise building, is located in Lujiazui area. The height of this 101-storey building is 492m above ground. A set of dynamic field tests were conducted on the building from April to May 2008. To identify the dynamic properties of the building, three output-only modal identification techniques are applied to the ambient and forced vibration measurements. These methods consist of: the Peak-Picking method (PP) combined with the half-power bandwidth method, the Random Decrement based method (RDT) combined with curve-fitting method, and the Hilbert–Huang transform method (HHT). The fundamental frequencies and damping ratios in two translational directions are identified from the free decays of forced vibration tests. The estimated eleven modal frequencies and damping ratios under microtremors from the Peaking-Picking method and the Hilbert–Huang transform method are compared to each other with favorable correlation. The modal frequencies from the finite element analysis and the shaking table test are further studied with the results of field test. The effect of the installed Active Tuned Mass Damper (ATMD) on the damping characteristics of the building is presented. Based on the identified results, accuracy and efficiency of these methods are investigated with the length of Fast-Fourier Transform and the effect of RDT. The modal properties of the SWFC presented in this paper can be used as baseline in future health monitoring.

Using fuzzy logic controller with adaptive detection scheme for fast acquisition of satellite navigation signals

The paper presents a fuzzy logic controller (FLC) with adaptive threshold control scheme to regulate frequency search step size so as to enhance performance in global navigation satellite system (GNSS) signal acquisition. Conventional frequency search can be achieved utilizing step‐by‐step frequency bin search or through fast Fourier transform (FFT). Nevertheless, too large a frequency search step size and short length of FFT result in large loss of correlation, whereas too small frequency search step size and long length of FFT increase signal acquisition time. To shorten signal acquisition time without influencing the accuracy of signal parameters, the FLC is employed to regulate the frequency search step size in the frequency domain on the basis of an input variable: code correlation value and its rate of change. To enhance the robustness of signal acquisition performance, the signal detection threshold is adaptively adjusted and combined with FLC. Besides, the basis value of membership function in FLC is adjustable. Hence, the input and output parameters of membership functions (MFs) vary with the adjustment of the detection threshold. Simulations and experimental results demonstrate that the proposed method enhances acquisition performance with regards to execution time and precision of parameters in GNSS signals.

An Energy-Efficient Partial FFT Processor for the OFDMA Communication System

In the orthogonal frequency-division multiple-access (OFDMA) communication system, resource allocation plays an important role in improving the transmission performance. The maximum spectral efficiency can be achieved through channel quality measurement, resource allocation, adaptive modulation, and so on. In this brief, we design a partial cached fast Fourier transform (FFT) processor that accounts for the distribution of allocated resources to the users of the OFDMA system. We also design a constellation- and power-aware twiddle-factor multiplier for the variable FFT length and modulation order. We implement a 128- to 1024-point mixed pipelined/cached-FFT processor using a 0.18-?m 1P6M CMOS technology. The chip measurement results show that its energy dissipation ranges from 0.09 to 1.90 nJ per FFT point and scales to the allocated resources in the OFDMA system.

An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor

Fast Fourier transform (FFT) plays an important role in the orthogonal frequency division multiplexing (OFDM) communication systems. In this paper, we propose an area-efficient design of variable-length FFT processor which can perform various FFT lengths of 512/1,024/2,048/4,096/8,192 points used in OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). To reduce computational complexity and chip area, we develop a new variable-length FFT architecture by devising a mixed-radix algorithm that consist of radix-2, radix-22 and radix-2/4/8 algorithms and optimizing the realization by substructure sharing. Based on this architecture, an area-efficient design of variable-length FFT processor is presented. By synthesized using the UMC 0.18 μm process, the area of the processor is 2.9 mm2 and the 8,192-point FFT can be performed correctly up to 50 MHz with power consumption 823 mW under a 1.8 V supply voltage.

Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs

A scheme for reducing the hardware resources to implement on LUT-based FPGA devices the twiddle factors required in Fast Fourier Transform (FFT) processors is presented. The proposed scheme reduces the number of embedded block RAM for large FFTs and the number of slices for FFT lengths higher than 128 points. Results are given for Xilinx devices, but they can be generalized for other advanced LUT-based devices like ALTERA Stratix.