Fabrication Of TFTs Research Articles

Active-matrix micro-light-emitting diode displays driven by monolithically integrated dual-gate oxide thin-film transistors

We present the first monolithic fabrication of a-IGZO TFTs on a GaN-based micro-LED array at a low temperature to overcome the weak thermal endurance constraint of the organic planarization layer for high resolution and stable low-cost LED displays.

Effect of HfO2-Based Multi-Dielectrics on Electrical Properties of Amorphous In-Ga-Zn-O Thin Film Transistors

We report the fabrication of bottom gate a-IGZO TFTs based on HfO2 stacked dielectrics with decent electrical characteristics and bias stability. The microscopic, electrical, and optical properties of room temperature deposited a-IGZO film with varied oxygen content were explored. In order to suppress the bulk defects in the HfO2 thin film and hence maximize the quality, surface modification of the SiNx film was investigated so as to achieve a more uniform layer. The root mean square (RMS) roughness of SiNx/HfO2/SiNx (SHS) stacked dielectrics was only 0.66 nm, which was reduced by 35% compared with HfO2 single film (1.04 nm). The basic electrical characteristics of SHS-based a-IGZO TFT were as follows: Vth is 2.4 V, μsat is 21.1 cm2 V−1 s−1, Ion/Ioff of 3.3 × 107, Ioff is 10−11 A, and SS is 0.22 V/dec. Zr-doped HfO2 could form a more stable surface, which will decrease the bulk defect states so that the stability of device can be improved. It was found that the electrical characteristics were improved after Zr doping, with a Vth of 1.4 V, Ion/Ioff of 108, μsat of 19.5 cm2 V−1 s−1, Ioff of 10−12 A, SS of 0.18 V/dec. After positive gate bias stress of 104 s, the ΔVth was decreased from 0.43 V (without Zr doping) to 0.09 V (with Zr doping), the ΔSS was decreased from 0.19 V/dec to 0.057 V/dec, respectively, which shows a meaningful impact to realize the long-term working stability of TFT devices.

Layer Thickness Effect on Lifetime of Copper Oxide Passivated Plasma Etched Copper Line

Cu is a widely used interconnect material in high density ICs, large area TFT LCDs, etc. Due to the difficulty in etching the Cu thin film using the conventional plasma etching method [1], the CMP method was developed to achieve this goal [2]. Kuo’s group developed a plasma-based Cu etch process that had a high rate even at the room temperature. [3,4]. This process has been applied to the fabrication of BiCMOS chips and TFTs [5,6]. Recently, the authors reported that CuOx could be an effective passivation material for Cu [7]. In this study, the CuOx passivation layer thickness effect on the reliability of the Cu line is studied using the electromigration (EM) method [8,9].The TiW/Cu stack was sputter deposited on the DHF cleaned Corning 1737 glass and etched into a 4-point test pattern. The Cu layer was etched by a 2-step plasma-based process [3,4]. The first step was to convert the patterned Cu film into a CuClx layer using the CF4/HCl (5/20 sccm) plasma at 70 mTorr and 600W in a parallel-plate reactor (PlasmaTherm 700C) operated at the RIE mode. The second step was to dissolve the CuClx layer in a dilute HCl solution (HCl:H2O=1:8 v/v). the TiW barrier film was etched in the CF4 (20 sccm) plasma at 60 mTorr and 600 W in the same RIE reactor. After stripping off the photoresist, a CuOx passivation layer was formed on the Cu surface by exposing the sample to the O2 plasma using the same reactor operated at the plasma etching (PE) mode. The EM stress was carried out under the constant current densities (J) condition at room temperature using the Agilent E3645A meter on a probe station (Signatone S-1160).Figure 1 shows the optical emission spectrum (OES) of the O2 plasma oxidation condition, i.e., 40 sccm, 200 mTorr, 300W at the PE mode. The two large peaks at 777 nm and 845 nm belong to the O radicals that are generated from the dissociative excitation. They correspond to transition states of 3p5P 3s5S and 3p3P 3s3S, respectively [10,11]. The O2 + vibrational state oxygens should show as peaks between 500 and 600 nm, which are very weak in Fig. 1. Therefore, the ion bombardment effect in this Cu oxidation process is much weaker than that of the oxygen radicals. Since the Cu layer was thin, the CuOx passivation layer was probably uniform over the Cu surface.Figure 2 shows the EM lifetimes of the TiW/Cu and TiW/Cu/CuOx lines with various CuOx passivation layer thicknesses. The general trend is that the lifetime is shortened with the increase of the current density. The breakage of the line can be contributed by the mechanism of voids formation and merging, which is accelerated by the increase of the current density [9]. In addition, the unpassivated line has a longer lifetime than the CuOx passivated line, i.e., red (12.5 nm thick CuOx layer) and blue (40 nm thick CuOx layer) lines. The thicker the passivation layer is, the shorter the EM lifetime is, which may be related to the heat dissipation effect. Since CuOx has a low thermal conductivity [12], the Cu line with a thick passivation layer is hotter than that with a thin passivation layer. The high temperature accelerates the voids formation and merging process [9].More detailed characterization of the CuOx passivation layer thickness effect will be presented and discussed.Authors acknowledge the financial support of this work through NSF CMMI project 1633580.1. H. Miyazaki, K. Takeda, N. Sakuma, S. Kondo, Y. Homma and K. Hinode., JVST B, 15(2), 237-240 (1997).2. J. Proost, T. Hirato, T. Furuhara, K. Maex and J.-P. Celis, JAP, 87(6), 2792-2802 (2000).3. Y. Kuo and S. Lee, JJAP, 39(3A), L188 (2000).4. S. Lee and Y. Kuo, JES, 148(9), G524-G529 (2001).5. Y. Kuo, H. Nominanda and G. Liu, JKPS, 48(91), S92-S97 (2006).6. J. Yang, Y. Ahn, J. Bang, W. Ryu, J. Kim, J. Kang, M. S. Yang, I. Kang, I. Cung, ECST, 16(9), 13 (2008).7. J. Q. Su and Y. Kuo, ECST, 98(3), 99-105 (2020).8. G. Liu and Y. Kuo, JES, 156(7), H579-H584 (2009).9. J. Q. Su, M. Li and Y. Kuo, ECS JSS, 9(10), 104009 (2020).10. U. Cvelbar, B. Markoli, I. Poberaj, A. Zalar, L. Kosec and S. Spaic, ASS, 253(4), 1861-1865 (2006).11. A. A. Kudryavtsev and L. D. Tsendin, Tech. Phys. Lett., 26(7), 582-587 (2000).12. M.-S. Liu, M. C.-C. Lin, I.-T. Huang and C.-C. Wang, ChET, 29(1), 72-77 (2006). Figure 1

Fabrication of Top-Gate Self-Aligned Amorphous InGaSnO TFTs with High Mobility

Fabrication of Top-Gate Self-Aligned Amorphous InGaSnO TFTs with High Mobility

Fabrication of Top-Gate Self-Aligned Amorphous InGaSnO TFTs with High Mobility

Fabrication of Top-Gate Self-Aligned Amorphous InGaSnO TFTs with High Mobility

Bendable Single Crystal Silicon Nanomembrane Thin Film Transistors with Improved Low-Temperature Processed Metal/n-Si Ohmic Contact by Inserting TiO2 Interlayer

Bendable single crystal silicon nanomembrane thin film transistors (SiNMs TFTs), employing a simple method which can improve the metal/n-Silicon (Si) contact characteristics by inserting the titanium dioxide (TiO2) interlayer deposited by atomic layer deposition (ALD) at a low temperature (90 °C), are fabricated on ITO/PET flexible substrates. Current-voltage characteristics of titanium (Ti)/insertion layer (IL)/n-Si structures demonstrates that they are typically ohmic contacts. X-ray photoelectron spectroscopy (XPS) results determines that TiO2 is oxygen-vacancies rich, which may dope TiO2 and contribute to a lower resistance. By inserting TiO2 between Ti and n-Si, Ids of bendable single crystal SiNMs TFTs increases 3–10 times than those without the TiO2 insertion layer. The fabricated bendable devices show superior flexible properties. The TFTs, whose electrical properties keeps almost unchanged in 800 cycles bending with a bending radius of 0.75 cm, obtains the durability in bending test. All of the results confirm that it is a promising method to insert the TiO2 interlayer for improving the Metal/n-Si ohmic contact in fabrication of bendable single crystal SiNMs TFTs.

Simple and reliable direct patterning method for carbon-free solution-processed metal oxide TFTs

Metal oxide TFT fabrication based on a solution-processing method is considered a promising alternative to conventional vacuum processing and has a number of advantages such as low cost, large-area fabrication, and process simplicity. A simple and reliable, direct patterning method for obtaining a carbon-free aqueous metal oxide film is presented herein. Patterning, which is achieved by selective photoreaction of water molecules under ultraviolet irradiation and by a safe, environment-friendly chemical etching process using a non-toxic organic acid, is followed by an annealing process at a temperature of 350 °C to obtain carbon-free metal oxide TFTs. In–Ga–Zn oxide (IGZO), TFTs on SiO2 dielectrics that were fabricated with a direct patterning method exhibited an average mobility of 4.3 cm2/V·s with good uniformity, which is comparable to TFTs formed by conventional photolithography. The TFTs exhibited stable performance with small (within 0.5 V) shifts in switch-on voltage under positive and negative bias stress. Fabrication of flexible IGZO TFTs by direct patterning was also achieved.

(Invited) High Density IGZO Film for Highly Reliable TFT By Inductively Coupled Plasma Sputtering Technology in Low Temperature Process

Transparent amorphous oxide semiconductors (TAOS) represented by IGZO have excellent characteristics such as high mobility, and a low off current compared with amorphous Si (a-Si) semiconductor. Furthermore, TAOS can be deposit by standard sputtering systems. Large area fabrication at a lower cost than low temperature polysilicon semiconductor (LTPS) is also possible. Therefore, there is a possibility to manufacture a display with high definition / low power consumption at low cost. However, many studies have shown the insufficient electrical reliability of IGZO TFTs. Although application to flexible displays is expected, in the conventional fabrication of IGZO TFTs, post annealing processes at a high temperature of 300°C is necessary. Therefore, low temperature formation of IGZO TFT is required. The inductively coupled plasma (ICP) sputtering system under development is characterized by its capacity to deposit high density films and high target usage efficiency. Figure 1 shows the schematic of the ICP sputtering system. In this system, the antenna is installed in the chamber, and a high-frequency generator is connected to the antenna. ICP is generated in the chamber by applying high-frequency to the antennas. In this device, since the magnetic field is not arranged on the target, ICP diffuses uniformly into the chamber. In order to perform sputtering, a negative bias voltage is applied to the target, ions are pulled from the ICP, and the target material is deposited on the substrate. The target material was uniformly consumed, and usage efficiency showed a very high value of 85%. In addition, since antennas and targets are connected to independent power supplies, independent control is possible. By increasing the high-frequency power applied to the antennas and controlling the plasma density, deposition is possible without lowering deposition rate even at low target voltage. We considered that independent control of RF power and target voltage is important because both may be related to film density. The density of the IGZO films deposited by changing the RF power and the target voltage was obtained using X-ray reflectivity. The results are shown in figures 2 (a) and (b). The relationship between RF power and film density could not be confirmed. When the target voltage was increased, the film density decreased. Therefore, performing deposition at a lower target voltage yielded a high-density IGZO film. Under all conditions, the IGZO films exhibited a film density of more than 6.0 g/cm3. In this study, the bottom-gate top-contact TFTs were fabricated by low-temperature process using high-density two-layer structure IGZO film deposited by ICP sputtering system, and the transfer characteristics and reliability were examined. Bottom-gate top-contact TFTs structure is shown in figure 3. The two-layer structure IGZO (In:Ga:Zn = 1:1:1) films were deposited by ICP sputtering system with different O2/Ar gas ratio condition at room temperature. The TFTs were subjected to post annealing at 150°C or 200°C or 250°C for 2 h under the O2/N2 mixed gas atmosphere. The passivation of the photosensitive polysilsesquioxane was coated using a straightforward solution process for samples annealed at 250°C, and baked at 250°C. The TFTs were subjected to a positive gate bias stress test (PBS) by applying a gate voltage (V gs) of 20 V, for a total stress time of 10000 s. Figure 4 show transfer characteristics of each post annealing temperature. When no annealing is performed, the TFT shows switching behavior but the threshold voltage (V th) became negative. When post annealing was carried out, V th became positive. Transfer characteristics at annealing temperature of 150°C to 250°C exhibited similar values. The electric field effect mobility of V ds = 0.5 V obtained from the transfer characteristic at post annealing temperature of 150°C was 7.9 to 8.8 cm2/Vs. The results of PBS are shown in figure 5. Threshold voltage shift (ΔV th) was used as an index of reliability. ΔV th of post annealing temperature of 150°C, 200°C and 250°C were 0.73 V, 0.75 V, 0.66 V, respectively. A sample with post annealing temperature at 250°C coated with polysilsesquioxane passivation has a ΔV th = 0.09 V. The reason why TFTs showing comparatively high-mobility can be fabricated even through a low-temperature process is considered to be the deposition of high-density films with low vacancy after deposition by the ICP sputtering system. In addition, it was found that the TFT with the annealing temperature of 150°C has the same reliability as the TFT with the annealing temperature of 250°C. We are set to demonstrate TFTs showing high-reliability at low-temperature process by using passivation that can be coated even at low temperatures. Figure 1

A Ladder-Type Organosilicate Copolymer Gate Dielectric Materials for Organic Thin-Film Transistors

A ladder-type organosilicate copolymer based on trimethoxymethylsilane (MTMS) and 1,2-bis(triethoxysilyl)alkane (BTESn: n = 2–4) were synthesized for use as gate dielectrics in organic thin-film transistors (OTFTs). For the BTESn, the number of carbon chains (2–4) was varied to elucidate the relationship between the chemical structure of the monomer and the resulting dielectric properties. The developed copolymer films require a low curing temperature (≈150 °C) and exhibit good insulating properties (leakage current density of ≈10−8–10−7 A·cm−2 at 1 MV·cm−1). Copolymer films were employed as dielectric materials for use in top-contact/bottom-gate organic thin-film transistors and the resulting devices exhibited decent electrical performance for both p- and n-channel organic semiconductors with mobility as high as 0.15 cm2·V−1·s−1 and an Ion/Ioff of >105. Furthermore, dielectric films were used for the fabrication of TFTs on flexible substrates.

Fully solution-induced high performance indium oxide thin film transistors with ZrO x high-k gate dielectrics.

Solution based deposition has been recently considered as a viable option for low-cost flexible electronics. In this context, research efforts have been increasingly focused on the development of suitable solution-processed materials for oxide based transistors. In this work, we report a fully solution synthesis route, using 2-methoxyethanol as solvent, for the preparation of In2O3 thin films and ZrOx gate dielectrics, as well as the fabrication of In2O3-based TFTs. To verify the possible applications of ZrOx thin films as the gate dielectric in complementary metal oxide semiconductor (CMOS) electronics, fully solution-induced In2O3 TFTs based on ZrO2 dielectrics have been integrated and investigated. The devices, with an optimized annealing temperature of 300 °C, have demonstrated high electrical performance and operational stability at a low voltage of 2 V, including a high μsat of 4.42 cm2 V−1 s−1, low threshold voltage of 0.31 V, threshold voltage shift of 0.15 V under positive bias stress for 7200 s, and large Ion/Ioff of 7.5 × 107, respectively. The as-fabricated In2O3/ZrOx TFTs enable fully solution-derived oxide TFTs for potential application in portable and low-power consumption electronics.

Inert gas annealing effect in solution-processed amorphous indium-gallium-zinc-oxide thin-film transistors

In this paper, the annealing effect of solution-processed amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs), under ambient He (He-device), is systematically analyzed by comparison with those under ambient O2 (O2-device) and N2 (N2-device), respectively. The He-device shows high field-effect mobility and low subthreshold slope owing to the minimization of the ambient effect. The degradation of the O2- and N2-device performances originate from their respective deep acceptor-like and shallow donor-like characteristics, which can be verified by comparison with the He-device. However, the three devices show similar threshold voltage instability under prolonged positive bias stress due to the effect of excess oxygen. Therefore, annealing in ambient He is the most suitable method for the fabrication of reference TFTs to study the various effects of the ambient during the annealing process in solution-processed a-IGZO TFTs.

High-performance solution-processed organic thin-film transistors based on a soluble DNTT derivative

We here report optimization of thin-film fabrication of 2-(4-ethyloctyl)dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (2-EO-DNTT), a soluble DNTT derivative, by spin-coating. The key to fabricate suitable thin films for high-performance TFTs is to control the nucleation and crystallites growth on the substrate during spin-coating; dropwise addition of the solution onto the spinning substrates enabled reproducible fabrication of such thin films, not only on the conventional Si/SiO2 substrate but also glass substrates with the gate dielectric consisting of AlOx/phosphonic acid self-assembled monolayers (SAMs). As a result, the present method realized fabrication of solution-processed TFTs with high mobility (>1.0 cm2 V−1 s−1), good environmental, operational, and thermal stability, and low-voltage operation (<3.0 V), all of which are mostly comparable to those of the vapor-processed parent DNTT-TFTs. These results clearly indicate that 2-EO-DNTT is the solution-processable alternative of DNTT.

Solvent‐Free Printing of Flexible Organic Thin Film Transistors by Ultrasonic Welding

A novel fabrication technique for making plastic electronics has been developed by applying an ultrasonic welding method that is already widely used in cutting, molding, and joining plastic sheets and parts for many industrial products. One major use of ultrasonic welding is the assembly of blood transfusion bags and other medical supplies, because the inert plastic parts can be joined and sealed without any adhesive agent and within a very short processing time. In this study, the same method is applied to make plastic electronics. The successful fabrication of organic TFTs is shown without affecting the gate insulator layer and the self‐assembled monolayer (SAM) of pentafluorobenzenethiol (PFBT). We therefore demonstrate that ultrasonic welding can also be used to fabricate plastic electronics. Using this process, for example, one could add electronic functionality not only on the surface of a blood transfusion bag, but also in or through the welding margin at the fringe of the bag.

Expedient floating process for ultra-thin InGaZnO thin-film-transistors and their high bending performance

Polyvinyl alcohol with low molecular weight exhibited good surface morphology and quick floating time for the fabrication of the top-gate oxide TFTs.

P‐149: Oxide TFTs on Fabric Substrates for Wearable Displays

Transition metal oxide TFTs were fabricated on a fabric substrate for wearable display. Atomic layer deposition (ALD) was employed to reduce process temperature. The gate electrode (Ti/Al/Ti) was deposited by thermal evaporation. The gate insulator and channel layer were Al2O3 and ZnO, respectively. Ti/Al was deposited by thermal evaporation to make the source and drain contacts for ZnO TFTs. The TFT fabricated on the fabric substrate showed TFT driving behavior with the following performances: µFE = 0.6 cm2/V‐s, on off ratio = 9.07×102, Subthreshold Swing = 1.725 decade‐1, Vth = ‐1.57 V. The results confirmed that it may be feasible to apply our low temperature fabrication of TFTs using the ALD process to wearable displays based on fabric substrates.

Impact of Underwater Laser Annealing on Polycrystalline Silicon Thin-Film Transistor for Inactivation of Electrical Defects at Super Low Temperature

We propose underwater laser annealing (WLA) for the inactivation of electrical defects in polycrystalline silicon thin-film transistors (poly-Si TFTs) at super low-temperature. This technique can reduce the temperature of inactivation process drastically, and it requires only UV laser and deionized water. We performed WLA after the fabrication of top-gate type poly-Si TFTs. After WLA, the field-effect mobility of poly-Si TFTs increased from 52 to 72 cm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{2}/{\hbox{V}}\cdot{\hbox{sec}}$</tex> </formula> . The TFT surface was exposed to water vapor which was generated by laser irradiation, resulting that electrical defects were inactivated by active species in water vapor.

46.4: Self‐Aligned Bottom‐Gate Amorphous IGZO Thin Film Transistor using the Back Side Exposure Technique

AbstractIn this work, we proposed new fabrication equipment for using the back side exposure technique in Gen.8 glass size and discussed a self‐alignment technique for fabrication of a‐IGZO TFTs which result in inverted staggered bottom gate devices, to simplify the OLED array processing. The Cgs of a‐IGZO TFTs with back side exposure process was lower about 40% than that of a a‐IGZO TFTs with typical process. The decrease in capacitance value of the back side exposure process a‐IGZO TFTs is because the overlap area between the gate and source/drain electrodes has become decrease. At Vds of 10V, the back side exposure process a‐IGZO TFTs represent μsat of 12.43 cm2/Vs, Vth of 0.75V, on‐current of 74.4uA, S‐Factor of 0.23V/dec.

Trapping Time Characteristics of Carriers in a-InGaZnO Thin-Film Transistors Fabricated at Low Temperatures for Next-Generation Displays

The effect of low-temperature annealing treatment for various durations on the stability of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors was investigated. By this treatment, IGZO TFTs showed enhanced electrical characteristics and better stability under positive gate bias stress with increasing annealing time up to 18,000 s. For all VG stresses at different annealing times, the experimentally measured threshold voltage shift (ΔVth) as a function of stress time was precisely modeled with a stretched-exponential function. ΔVth was generated by carrier trapping, not by defect creation. It was verified that the decrease of interface trap state density (Nit) and free carriers resulted in the decrease of ΔVth with increasing annealing time. However, the characteristic trapping time of the carriers increased up to 5.3 × 103 s with increasing annealing time to 7,200 s and then decreased, implying that the interface quality between active layer/insulator was deteriorated with further annealing. In this study, successful fabrication of IGZO TFTs by post treatment with optimized duration is demonstrated for flexible display applications.

Low-temperature fabrication (

This paper presents a low temperature fabrication of amorphous IGZO TFTs (a-IGZO TFTs) via high density CVD and superimposed rf/dc magnetron sputtering below 150 °C Low temperature processed SiOx films were been prepared in high density plasma chemical vapor deposition with inductively-coupled plasma (ICP) source and their electrical properties of these films have been investigated as a function of an ICP power and an O2 flow rate. Also, we found that a-IGZO semiconductor could be affected by a dc self-bias of a target surface using a superimposed rf/dc magnetron sputtering. Increasing a dc self-bias, higher post-annealing temperature is needed to achieve their electrical characteristics of a-IGZO TFTs. For a low-temperature and high performance a-IGZO TFTs, therefore, it is necessarily considered that a-IGZO semiconductors could be damaged due to accelerated negative oxygen ions during conventional magnetron sputtering.

Characteristics of a-IGZO/ITO Hybrid Layer Deposited by Magnetron Sputtering

Transparent a-IGZO (In-Ga-Zn-O) films have been actively studied for use in the fabrication of high-quality TFTs. In this study, a-IGZO films and a-IGZO/ITO double layers were deposited by DC magnetron sputtering under various oxygen flow rates. The a-IGZO films showed an amorphous structure up to 500 degrees C. The deposition rate of these films decreased with an increase in the amount of oxygen gas. The amount of indium atoms in the film was confirmed to be 11.4% higher than the target. The resistivity of double layer follows the rules for parallel DC circuits The maximum Hall mobility of the a-IGZO/ITO double layers was found to be 37.42 cm2/V x N s. The electrical properties of the double layers were strongly dependent on their thickness ratio. The IGZO/ITO double layer was subjected to compressive stress, while the ITO/IGZO double layer was subjected to tensile stress. The bending tolerance was found to depend on the a-IGZO thickness.