Fabrication Of Nanoelectronic Devices Research Articles

Nanofabrication of surface-enhanced Raman scattering device by an integrated block-copolymer and nanoimprint lithography method

The integration of block-copolymers (BCPs) and nanoimprint lithography (NIL) presents a novel and cost-effective approach to achieving nanoscale patterning capabilities. The authors demonstrate the fabrication of a surface-enhanced Raman scattering device using templates created by the BCP-NIL integrated method. The method utilizes a poly(styrene-block-methyl methacrylate) cylindrical-forming diblock-copolymer as a masking material to create a Si template, which is then used to perform a thermal imprint of a poly(methyl methacrylate) (PMMA) layer on a Si substrate. Au with a Cr adhesion layer was evaporated onto the patterned PMMA and the subsequent lift-off resulted in an array of nanodots. Raman spectra collected for samples of R6G on Si substrates with and without patterned nanodots showed enhancement of peak intensities due to the presence of the nanodot array. The demonstrated BCP-NIL fabrication method shows promise for cost-effective nanoscale fabrication of plasmonic and nanoelectronic devices.

Directed assembly of solution processed single-walled carbon nanotubes via dielectrophoresis: From aligned array to individual nanotube devices

The authors demonstrate directed assembly of high quality solution processed single-walled carbon nanotube (SWNT) devices via ac dielectrophoresis using commercially available SWNT solutions. By controlling the shape of the electrodes, concentration of the solution, and assembly time, the authors are able to control the assembly of SWNTs from dense arrays down to individual SWNT devices. Electronic transport studies of individual SWNT devices show field effect mobilities of up to 1380 cm2/V s for semiconducting SWNTs and saturation currents of up to ∼15 μA for metallic SWNTs. The field effect mobilities are more than an order of magnitude improvement over previous solution processed individual SWNT devices and close to the theoretical limit. Field effect transistors (FET) fabricated from aligned two-dimensional arrays of SWNT show field effect mobility as high as 123 cm2/V s, which is three orders of magnitude higher than the solution processed organic FET devices. This study shows promise for commercially available SWNT solution for the parallel fabrication of high quality nanoelectronic devices.

The fabrication and assembly of nanoelectronic devices

PurposeThe purpose of this paper is to provide a review of recent developments in nanoelectronic devices, with an emphasis on the materials and fabrication technologies employed.Design/methodology/approachThis paper focuses on three critical fields of nanoelectronics: integrated circuits (ICs), sensors and displays. It describes recent developments and considers the materials and techniques used in their fabrication.FindingsThis paper shows that nanoelectronic developments, particularly experimental ICs, are progressing very rapidly but all manner of different materials and non‐standard fabrication processes are involved. Major efforts are underway to develop simple and cost‐effective techniques which will allow the high volume production of suitable nanomaterials and their incorporation into commercial nanoelectronic devices.Originality/valueThe paper provides an up‐to‐date review of nanoelectronic device developments and fabrication technologies.

INFLUENCE OF ROOM HUMIDITY ON THE FORMATION OF NANOSCALE SILICON OXIDE PATTERNED BY AFM LITHOGRAPHY

Nanometer-scale silicon oxide mask was patterned by atomic force microscope (AFM) lithography for fabrication of nanoelectronic devices. The oxide growth mechanism is similar to a well-known local anodic oxidation, which a negative voltage applied to conductive AFM tip in order to grow oxide patterns on silicon layer surface. The surrounding environment is one of the very important parameter on the formation of nanoscale silicon oxide patterns via AFM lithography. Therefore, in this work, the effect of relative humidity (RH) has been studied systematically in the range of 55–72%. Meanwhile, the applied tip voltage, exposure time, and scanning speed were kept constant during lithography process. From AFM topographic analysis on the fabricated nanopatterns found that the oxide width and thickness are significantly depending on the room humidity. These results proved that the room humidity is playing an important role on the fabrication of nanometer-scale oxide patterns by using AFM nanolithography.

Self-catalytic growth of horizontal and straight Si nanowires on Si substrates using a sputter deposition technique

We report on the growth of horizontal and straight Si nanowires (NWs) on Si substrate using sputter deposition of the Si layer followed by thermal annealing at 1000 °C and above. The growth of horizontal NWs was achieved without the use of any metal catalyst. Uniform cylindrical shaped Si NWs with a diameter in the range of 50–60 nm and a length of up to 8 μm were synthesized. The as-synthesized Si NWs have a Si core covered with a thin amorphous native oxide layer, as revealed by high resolution transmission electron microscopy. The aspect ratio of these Si NWs is in the range of 100–160. Micro-Raman studies on the NWs reveal a tensile strain on the Si NW core due to presence of a thin oxide layer. From the Raman shift, we calculate a strain of 1.0% for the catalyst free Si NW. FTIR analysis indicates the presence of interstitial oxygen atoms in the Si NWs, as expected from oxidation of Si NWs. For comparison, metal catalyst (Au) assisted Si NWs have also been grown on Si(100) substrate by a similar process. These NWs have a similar diameter and a marginally higher aspect ratio. A model for the growth mechanism of horizontal NWs is presented. This represents one of the first examples of direct horizontal growth of straight Si NWs on commonly used Si substrates suitable for nanoelectronic device fabrication.

High quality solution processed carbon nanotube transistors assembled by dielectrophoresis

We report on high quality individual solution processed single-walled carbon nanotube (SWNT) field effect transistors assembled from a commercial surfactant free solution via dielectrophoresis. The devices show field effect mobilities up to 1380 cm2/V s and on-state conductance up to 6 μS. The mobility values are an order of magnitude improvement over previous solution processed SWNT devices and close to the theoretical limit. These results demonstrate that high quality SWNT devices can be obtained from solution processing and will have significant impact in high yield fabrication of SWNT nanoelectronic devices.

One-Step Direct Transfer of Pristine Single-Walled Carbon Nanotubes for Functional Nanoelectronics

We report a one-step direct transfer technique for the fabrication of functional nanoelectronic devices using pristine single-walled carbon nanotubes (SWNTs). Suspended SWNTs grown by the chemical vapor deposition (CVD) method are aligned and directly transferred onto prepatterned device electrodes at ambient temperature. Using this technique, we successfully fabricated SWNT electromechanical resonators with gate-tunable resonance frequencies. A fully suspended SWNT p-n diode has also been demonstrated with the diode ideality factor equal to 1. Our method eliminates the organic residues on SWNTs resulting from conventional lithography and solution processing. The results open up opportunities for the fundamental study of electron transport physics in ultraclean SWNTs and for room temperature fabrication of novel functional devices based on pristine SWNTs.

Fabrication of Nano-scale Electronic Devices Based on Single-layer Graphene

We review our recent experiments on the fabrication of nano-electronic devices in single-layer graphene. A graphene nanoribbon device was fabricated by conducting local anodic oxidation lithography using tapping-mode atomic force microcsope. The conductance of the graphene nanoribbon at the charge neutrality point was suppressed at low temperature, which suggests the opening of an energy gap due to the lateral confinement of charge carriers. A single quantum dot was fabricated by using the conventional electron beam lithography combined with plasma etching of the graphene layer. The quantum dot works as a single-electron transistor, which shows Coulomb blockade characteristics. These results suggest possibilities of the future application of the nano-electronic devices based on graphene.

Interstitial-Mediated Diffusion in Germanium under Proton Irradiation

We report experiments on the impact of 2.5 MeV proton irradiation on self-diffusion and dopant diffusion in germanium (Ge). Self-diffusion under irradiation reveals an unusual depth independent broadening of the Ge isotope multilayer structure. This behavior and the observed enhanced diffusion of B and retarded diffusion of P demonstrates that an interstitial-mediated diffusion process dominates in Ge under irradiation. This fundamental finding opens up unique ways to suppress vacancy-mediated diffusion in Ge and to solve the donor deactivation problem that hinders the fabrication of Ge-based nanoelectronic devices.

Adsorption behavior of ferritin and buffer components, buffer agents and salts, onto silane-coupled silicon substrate

Fixation of ferritin using amino-silane modified substrates is effective, but salt and alkali ions of the buffer can contaminate substrates, inhibiting the sensing and fabrication of nano-electronic devices. To avoid adsorption of salts and alkali ions, buffer solutions have been replaced by pure water or alkali-metal-ion-free buffer. However, proteins in such solutions are sometimes denatured. Therefore, we developed a substrate which adsorbs ferritin but does not adsorb contaminants such as salts and alkali metal-ions contained in the buffer. Adsorption of ferritin was achieved by using a buffer with a high ion strength, such as PBS buffer, because the Debye length becomes shorter with increased ion strength due to intermolecular force even when the substrate has no positive charge. The combination of high coverage methyltrimethoxysilane (MTMS)-coupled silicon substrate and PBS buffer solution is effective for adsorption of ferritin while not adsorbing buffer components such as contaminants and/or salts on the silicon substrate.

Directed Assembly of SWNTs by Electrostatic Interactions and its Application for Making Network Transistors

Single-wall carbon nanotubes (SWNTs) are promising building blocks for the fabrication of nanoelectronic devices. However, achieving control over their assembly on substrates has been challenging and is still a bottleneck to their utilization. Herein, we present a general method for directing the chemical assembly of SWNTs on substrates through electrostatic interactions. By covalently functionalizing both the nanotube sidewalls and the SiO(2) substrate with charged groups, dense networks of SWNTs were produced. The method is selective and highly efficient to process network field-effect transistors.

Carbon Nanotubes: State-of-the-art Technology and Safety for Success

Carbon nanotubes, consisting of rolled graphene layer built from <TEX>$sp^2$</TEX> units, have attracted the imagination of scientists as ideal macromolecules and their unusual physical and chemical properties make them useful in the fabrication of nanocomposites, nano-electronic devices and sensors etc. In this account, the current status and prospect of carbon nanotubes is described with a special emphasis on the safety issue of carbon nanotubes. Even though many challenges to be solved remain, extensive and intensive efforts in both academy and industry will clear out those problems soon and finally enable carbon nanotubes to play a key innovative material of 21st century in numerous industrial processes.

Structural Combinatorial Strategy for Advanced Nanotechnology Researches

A new structural combinatorial strategy toward efficient nanoscale structural optimization and direct nanophotonic and nanoelectronic device fabrication is introduced. The strategy was applied to develop a new multi-functional photodetector, which is able to simultaneously detect power, energy, and polarization of an incident UV light. The strategy was also used to study the dielectric behavior of ferroelectric relaxor PMN-PT heterophase superlattices in the terahertz (THz) frequencies in order to investigate their dielectric polariton properties and tunable dielectrics.

Guiding Electrical Current in Nanotube Circuits Using Structural Defects: A Step Forward in Nanoelectronics

Electrical current could be efficiently guided in 2D nanotube networks by introducing specific topological defects within the periodic framework. Using semiempirical transport calculations coupled with Landauer-Buttiker formalism of quantum transport in multiterminal nanoscale systems, we provide a detailed analysis of the processes governing the atomic-scale design of nanotube circuits. We found that when defects are introduced as patches in specific sites, they act as bouncing centers that reinject electrons along specific paths, via a wave reflection process. This type of defects can be incorporated while preserving the 3-fold connectivity of each carbon atom embedded within the graphitic lattice. Our findings open up a new way to explore bottom-up design, at the nanometer scale, of complex nanotube circuits which could be extended to 3D nanosystems and applied in the fabrication of nanoelectronic devices.

Transport properties of three-terminal ballistic junctions realized by focused ion beam enhanced etching in InGaAs/InP

Three-terminal junction devices are realized in an InGaAs/InP quantum well by focused ion beam (FIB) implantation and selective wet etching. Room temperature electrical measurements show that the fabricated devices exhibit strong nonlinear electrical properties. The results are discussed in terms of ballistic electron transport. It is demonstrated that FIB-enhanced etching processing can be exploited as a maskless, resist-free technique for fabrication of high-quality and functional nanoelectronic devices.

Selective Enzymatic Labeling To Detect Packing-Induced Denaturation of Double-Stranded DNA at Interfaces

The adsorption of DNA on surfaces is a widespread procedure and is a common way for fabrication of biosensors, DNA chips, and nanoelectronic devices. Although the biologically relevant and prevailing in vivo structure of DNA is its double-stranded (dsDNA) conformation, the characterization of DNA on surfaces has mainly focused on single-stranded DNA (ssDNA). Studying the structure of dsDNA on surfaces is of invaluable importance to microarray performance since their effectiveness relies on the ability of two DNA molecules to hybridize and remain stable. In addition, many of the enzymatic transactions performed on DNA require dsDNA, rather than ssDNA, as a substrate. However, it is not established that adsorbed dsDNA remains in its structure and does not denature. Here, two methodologies have been developed for distinguishing between surface-adsorbed single- and double-stranded DNA. We demonstrate that, upon formation of a dense monolayer, the nonthiolated strand comprising the dsDNA is released and the monolayer consists of mostly ssDNA. The fraction of dsDNA within the ssDNA monolayer depends on the length of the oligomers. A likely mechanism leading to this rearrangement is discussed.

Application of Scanning Probe Microscopy Techniques for Structural and Electrical Characterization of Dielectrics, Carbon Nanotubes and Nanoelectronic Devices

The challenges in the metrology of nanoelectronic structures demand for powerful and cost-efficient diagnostic techniques. In recent years, scanning probe microscopy techniques, like atomic force microscopy (AFM), have become indispensable tools for non-destructive characterization at the nanometer scale. More recently, the topographic imaging capabilities of the AFM have been extended by implementing current sensing techniques so that a direct correlation of a feature location with its electrical signature is possible. Several examples on the application of combined AFM and conductive AFM techniques will be presented in order to illustrate the potential of the SPM technique for structural and electrical characterization of semiconductor surfaces, dielectrics, carbon nanotubes as well as fabrication of nanoelectronic devices.

Dielectrophoretic Deposition of Carbon Nanotubes with Controllable Density and Alignment

ABSTRACTControlled deposition of carbon nanotubes (CNTs) across desired electrodes is important for the fabrication of nanoelectronic devices. Dieletrophoresis (DEP) has been recognized as a convenient and affordable technique for the deposition of nanotubes and nanowires on electrodes. Although DEP has been quite well studied for dielectric particles, the application for depositing nanotubes is still at the early stage of development. Here, we show that multi-walled CNTs can be deposited by DEP with controllable density and degree of alignment.

A Horizontally Aligned One-Dimensional Carbon Nanotube Array on a Si Substrate

A one-dimensional array of carbon nanotubes horizontally aligned on silicon substrates was successfully grown using a flame synthesis method based on the template of a one-dimensional anodic aluminum oxide nanopore array. The diameter and length of nanotubes are controlled by the geometry of nanopores of the aluminum oxide template. This one-dimensional carbon nanotube array may have great potential for fabrication of nanoelectronic devices and nanoelectromechanic systems (NEMS) compatible with the planar processing technology.

Ultra-shallow junction by laser annealing: Integration issues and modelling

A revolutionary approach to the technology design is required for the integration of the laser annealing process in nano-electronic device fabrication. The list of the integration issues includes: the patterning effect, the extreme non-equilibrium kinetics of dopant and defects, the material modification due to the melting-regrowth phenomena (in the melting regime) and the residual damage problem. The intense research effort required surely benefits from an adequate development of dedicated technology computer aided design tools. We present the computational apparatus needed for the simulation of the laser annealing process in Si-based devices. The tools aim at the simulation at a different resolution (from the atomic to the continuum level) of the phenomena occurring inside the specimen during the irradiation. The usage impact of such simulation tools on the process integration is conclusively crucial for a reliable device design and the final optimisation of fabricated MOS transistors.