Threshold Voltage Extraction Research Articles

Threshold Voltage Extraction of nMOSFET Devices in Photovoltaic Inverters

Abstract In this paper, the electrical characteristics of nMOSFET devices at room temperature are measured, and the threshold voltage is extracted by three different methods according to the I-V transfer characteristic curve of the nMOSFTE devices. The applicability of the three methods and the extraction results are analyzed and compared. The conclusions indicate that: (1) the maximum transconductance extraction method is similar to the tangential extrapolation extraction method, both of which eliminate the influence of mobility degradation and parasitic capacitance effect. The second order derivative extraction methods include the fluctuation factors in the measured results, and has a larger error on the extracted threshold voltage; (2) Compared with the maximum transconductance extraction method, the errors of extracting threshold voltage using tangential extrapolation method is larger because mobility attenuation, sourcing-drain series resistance and tangential point is difficult to determine accurately are ignored. (3) In comparison, the threshold voltage extracted by the maximum transconductance method is more accurate and easy to achieve.

Dynamic Bias-Temperature Instability Testing in SiC MOSFETs

For power converter development in mission critical applications, the attractive performances of SiC power MOSFETs are shadowed by reliability concerns, particularly those induced by the defects at the gate dielectric. Charge trapping at the oxide-semiconductor interface can lead to threshold voltage drift, degrading the power converter efficiency and lifetime. The scope of this contribution is to show a testing methodology under development to understand SiC power MOSFET threshold voltage stability under dynamic and accelerated operating conditions. The presented testing methodology relies on switching the device under test at high-voltage and current, simultaneously applying a gate stress and extracting threshold voltage from switching transients. The paper outlines the setup description, its operating modes and intended design of experiment to assess SiC MOSFET threshold voltage stability.

DC and RF performance analysis of enhancement mode fin-shaped tri-gate AlGaN/GaN HEMT and MOSHEMT with ultra-thin barrier layer

The DC and RF assessment of critical barrier-AlGaN/GaN nano channel tri-gate fin-shaped High Electron Mobility Transistor (FinHEMT) is investigated for Enhancement-mode (E-mode) operation. We propose and analyze critical barrier layer (CBL) and critical-strained barrier layer (CSBL) FinHEMT for a fixed fin-shaped channel width (W fin = 160 nm) and height (H fin = 70 nm). The CBL FinHEMT ensures an E-mode operation by depleting two-dimensional electron gas (2DEG) near the channel region between AlGaN and GaN hetero-junction. The extracted threshold voltage (V T ) in CBL FinHEMT is 0.4 V as compared to −0.2 V obtained in CSBL FinHEMT. However, increased gate leakage current density and poor gate voltage swing in CBL FinHEMT is improved through a metal-oxide-semiconductor FinHEMT (FinMOSHEMT) structure by the incorporation of Al2O3 gate oxide layer between the tri-gate and CBL AlGaN layer. It results in a stable positive VT of 0.5 V due to the negatively charged Al2O3/barrier interface fixed charge density ( NAl2O3 ). The proposed CBL FinMOSHEMT has also been studied for different atomic layer deposition Al2O3 process-dependent variations in NAl2O3. The maximum on-state drain current and transconductance of 1.01 A mm−1 and 430 mS/mm have been extracted respectively with NAl2O3 of −9.2 × 1012 cm−2. Further, the RF analysis of the proposed CBL FinMOSHEMT structure with the same dimension exhibits improved f T and f max responses with 27 GHz and 90 GHz respectively over CBL FinHEMT. The results of the frequency responses obtained for the proposed design make it suitable for power electronics applications.

Threshold Voltage Extraction Using Conductance–Voltage Method for Nano‐Organic/Oxide Thin‐Film Transistors: Comparative Study of P‐ and N‐Type Devices

Threshold voltage is an essential component for a transistor to operate properly. In this work, an alternate technique for obtaining the threshold voltage, which is referred to as the conductance–voltage method, is suggested. In this technique, the threshold voltage is estimated by measuring the change in drain current with an applied gate voltage when the device transits from the weak accumulation to the strong accumulation mode of operation. The 2D simulations are then used to apply this strategy to pentacene‐based and amorphous indium‐gallium‐zinc‐oxide‐based thin‐film transistors (TFTs) in their linear region of operation. These seem promising, and the technique offers a useful tool for enhancing the functionality of complementary organic/oxide TFTs in the future.

Detailed comparison of threshold voltage extraction methods in FD-SOI MOSFETs

The threshold voltage in ultrathin FD-SOI MOSFETs is revisited from theoretical definitions to pragmatic extraction techniques, including novel ones. Their respective merits and limitations are underlined.

Simultaneous Extraction of Mobility Enhancement Factor and Threshold Voltage With Parasitic Resistances in Amorphous Oxide Semiconductor Thin-Film Transistors

This study presents a technique for simultaneous and consistent extraction of the mobility enhancement factor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma$</tex-math> </inline-formula> ) and the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\textit{T}}$</tex-math> </inline-formula> ) with parasitic source and drain resistances ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{S}}$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{D}}$</tex-math> </inline-formula> ) in amorphous oxide semiconductor (AOS) thin film transistors (TFTs). This technique allows for the extraction of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{S}}$</tex-math> </inline-formula> from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{D}}$</tex-math> </inline-formula> as well as the accurate extraction of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\textit{T}}$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma $</tex-math> </inline-formula> with only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{I}$</tex-math> </inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}$</tex-math> </inline-formula> characteristics of the saturation operation in a single AOS TFT. The proposed technique was applied to amorphous indium–gallium–zinc-oxide (a-IGZO) TFTs with various structures. For intentional asymmetry, we confirmed the consistency with an external resistor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{ext}} = \text{10}$</tex-math> </inline-formula> , 20, 30 k <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega$</tex-math> </inline-formula> ). Extracted parameters ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{S}}$</tex-math> </inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\textit{D}}$</tex-math> </inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\textit{T}}$</tex-math> </inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma$</tex-math> </inline-formula> ) by the proposed method were compared with parameters extracted by other methods for verification. Furthermore, the drain current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{I}_{\textit{D}}$</tex-math> </inline-formula> ) was well reproduced using the extracted parameters regardless of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{ext}}$</tex-math> </inline-formula> .

A Pixel Circuit for Compensating Electrical Characteristics Variation and OLED Degradation

In recent years, the active-matrix organic light-emitting diode (AMOLED) displays have been greatly required. A voltage compensation pixel circuit based on an amorphous indium gallium zinc oxide thin-film transistor is presented for AMOLED displays. The circuit is composed of five transistors–two capacitors (5T2C) in combination with an OLED. In the circuit, the threshold voltages of both the transistor and the OLED are extracted simultaneously in the threshold voltage extraction stage, and the mobility-related discharge voltage is generated in the data input stage. The circuit not only can compensate the electrical characteristics variation, i.e., the threshold voltage variation and mobility variation, but also can compensate the OLED degradation. Furthermore, the circuit can prevent the OLED flicker, and can achieve the wide data voltage range. The circuit simulation results show that the OLED current error rates (CERs) are lower than 3.89% when the transistor’s threshold voltage variation is ±0.5V, lower than 3.49% when the mobility variation is ±30%.

Threshold-Voltage Extraction Methods for Atomically Deposited Disordered ZnO Thin-Film Transistors.

In this paper, we present a threshold-voltage extraction method for zinc oxide (ZnO) thin-film transistors (TFTs). Bottom-gate atomic-layer-deposited ZnO TFTs exhibit typical n-type enhancement-mode transfer characteristics but a gate-voltage-dependent, unreliable threshold voltage. We posit that this obscure threshold voltage is attributed to the localized trap states of ZnO TFTs, of which the field-effect mobility can be expressed as a gate-bias-dependent power law. Hence, we derived the current-voltage relationship by dividing the drain current with the transconductance to rule out the gate-bias-dependent factors and successfully extract the reliable threshold voltage. Furthermore, we investigated the temperature-dependent characteristics of the ZnO TFTs to validate that the observed threshold voltage was genuine. Notably, the required activation energies from the low-temperature measurements displayed an abrupt decrease at the threshold voltage, which was attributed to the conduction route change from diffusion to drift. Thus, we conclude that the reliable threshold voltage of accumulation-mode ZnO TFTs can be determined using a gate-bias-dependent factor-removed current-voltage relationship with a low-temperature analysis.

Automatic Prediction of Metal–Oxide–Semiconductor Field‐Effect Transistor Threshold Voltage Using Machine Learning Algorithm

A fast and precise threshold voltage (Vth) extraction method is required for the process design of electronic systems using metal–oxide–semiconductor field‐effect transistors (MOSFETs) and its immediate on‐site analysis during fabrication. The selection of a suitableVthextraction method is a complicated task because it involves a trade‐off between accuracy and simplicity according to the device scheme. Herein, an automatic‐prediction method of the MOSFETVthusing machine learning (ML) is proposed. The ML model is trained withVth, extracted using different methods (2nd derivative, constant current, andY‐function) and from various kinds of FETs (finFET, 2D FET, and metal–oxide thin‐film transistors). The concept of threshold ratio (Rth) for universalVthprediction, which considers the normalizedVthwithin certainVGranges, is suggested. The precision and accuracy of ML models are statistically verified by calculating the root mean square error (RMSE), mean absolute error, and mean coefficients of determination (R2) values. The universal ML model (k‐nearest neighbor (kNN)) achieves 1.35% of RMSE and 0.98 ofR2for the best score. The ML model eliminates the ambiguity inVthextraction and provides objectiveVthprediction for most FET schemes used in the semiconductor industry and research field.

Extraction of Dynamic Threshold Voltage in Resistive Load Hard Switching Operation of Schottky-Type p-GaN Gate HEMT

Threshold voltage (VTh) drift of Schottky-type p-GaN gate high-electron mobility transistor (HEMT) was analyzed under high-voltage and hard switching conditions with a resistive load (R-Load). To overcome the distortion in the drain current (ID) – gate voltage (VG) curve caused by the internal drain capacitance (IDisp) charging current during the switching transients, a method is presented to accurately measure dynamic VTh through appropriate correction of IDisp. The dynamic variation of VTh was tracked with a gate-drive rise/fall times of 200 ns. During the switching operation, VTh increases rapidly at the beginning and then saturates at a stable value. This is attributed to the gate forward current during turn-on that increases the hole depletion of the p-GaN gate through the AlGaN barrier. The dynamic VTh increases linearly at a rate of 40% with the increase of gate turn-on voltage. VTh is independent of duty cycle but minorly increases with frequency at high voltages, suggesting that channel hot electrons be injected into the AlGaN barrier and p-GaN.

12.2: High Performance AMOLED Pixel Circuit Using Interleaved Emit Signals Based on Low‐Temperature Poly‐Si and Oxide (LTPO) TFTs

A concise pixel circuit with interleaved Emit signals is proposed for active matrix organic light‐emitting diode (AMOLED) displays, on the basis of low‐temperature polycrystalline silicon oxide (LTPO) TFTs. The oxide TFT can be re‐used for both initialization and threshold voltage extraction periods, using interleaved Emit signals of adjacent lines with overlapped waveforms. The proposed pixel circuit consists of 1 oxide TFT and 5 p‐type LTPS TFTs, while only 2~3 types of line‐by‐line scanning driving signals, i.e. the Emit signal and the Scan signal, are required. Implementation of the proposed pixel circuit shows that the occupation can be reduced to 40 μm × 56.7 μm. Furthermore, optimization of the pixel circuit shows the emission current error is less than 2.3% with threshold voltage variation of ± 0.5 V, while refresh rate from 1 to 120 Hz can achieved.

Temperature-Dependent Threshold Voltage Extraction of FinFETs Using Noise Measurements

In this article, a temperature-dependent threshold voltage extraction method based on noise measurement is proposed. This method induces a mathematical solution for acquiring channel temperatures ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T$ </tex-math></inline-formula> ) of transistors in the saturation region to extract threshold voltages. In order to gain accurate channel temperature, a small-signal equivalent circuit model was established to determine transconductance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> ). Then, the extracted transconductance and measured noise power spectral density (NPSD) were used to obtain channel temperatures. On this basis, the temperature-dependent threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {th}}$ </tex-math></inline-formula> ) was derived. To validate the reliability of this method, a four-Fin six-finger N-FinFET and a four-Fin eight-finger N-FinFET were fabricated using the 14-nm bulk FinFET technology. In this study, the scattering parameters were obtained from 0.2 to 40.2 GHz. Also, the NPSDs were measured from 1 to 500 Hz, while gate voltage and drain voltage were set as 0.3, 0.49, and 0.75 V. Besides, the transistor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {ds}}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {ds}}$ </tex-math></inline-formula> characteristics was also investigated when drain–source bias voltage changed from 0.05 to 0.9 V. Compared with the measurement results, the calculation results of drain–source current model using temperature-dependent threshold voltage achieved higher accuracy. Also, the root mean square errors (RMSEs) were less than 0.60% for four-Fin six-finger N-FinFET and less than 0.51% for four-Fin eight-finger N-FinFET. Therefore, the proposed extraction method can be applied to accurately predict transistor temperature-dependent threshold voltage.

Study of threshold voltage extraction from room temperature down to 4.2 K on 28 nm FD-SOI CMOS technology

This paper aims to benchmark the threshold voltage extraction at cryogenic temperature. It presents two DC and for the first time one RF methods to extract the threshold voltage down to 4.2 K for channel lengths down to 28 nm. Measurements are performed on CMOS transistors integrated in 28 nm Fully Depleted Silicon-On-Insulator (FDSOI). First, two methods based on DC measurement are explained: the constant-current and the second derivative technique. Besides, the gate-channel capacitance derivative method based on RF measurements is presented. Finally, we discuss and compare the advantages and limits of these different methods.

Three-point I–V spectroscopy deconvolves region-specific degradations in LDMOS transistors

Unlike traditional logic transistors, hot carrier degradation (HCD) in power transistors involves simultaneous and potentially correlated degradation in multiple regions. One must deconvolve and characterize the voltage- and temperature-dependence of these region-specific degradations to develop a predictive HCD model of power transistors. Unfortunately, power transistors' doping and geometrical complexities make it challenging to use traditional defect-profiling techniques, such as charge-pumping or gated-diode methods. This Letter uses a physics-based tandem-FET model of an Laterally Diffused MOS (LDMOS) transistor to develop a “three-point I–V spectroscopy” technique that uses the time-evolution of three critical points of the measured I–V characteristics to extract mobility and threshold voltage degradations in the channel and drift regions. This innovative approach should generalize to other configurations of the LDMOS transistor as well.

Current-to-transconductance ratio technique for simultaneous extraction of threshold voltage and parasitic resistances in MOSFETs

In this work, a current-to-transconductance ratio technique is proposed for simultaneous extraction of the threshold voltage (VT) and parasitic source (RS) and drain (RD) resistances in short channel metal–oxide–semiconductor field-effect transistors (MOSFETs). The proposed technique allows simultaneous extraction of RS, RD, and VT in any single MOSFET with the channel length modulation (CLM) and the structural asymmetry. The proposed method is experimentally verified through Si MOSFETs with intentional asymmetry by connecting an external resistor (Rext) to the source terminal. We experimentally confirmed that extracted RS, RD, and VT are independent of the drain bias (VDS) and intentional Rext employed for the asymmetry. We also compared the results with previously reported techniques.

Does the Threshold Voltage Extraction Method Affect Device Variability?

The gate-all-around nanowire FET (GAA NW FET) is one of the most promising architectures for the next generation of transistors as it provides better performance than current mass-produced FinFETs, but it has been proven to be strongly affected by variability. For this reason, it is essential to be able to characterize device performance which is done by extracting the figures of merit (FoM) using data from the IV curve. In this work, we use numerical simulations to evaluate the effect of the threshold voltage ( $\mathrm {V_{TH}}$ ) extraction method on the variability estimation for a gate-all-around nanowire FET. For that, we analyse the impact of four sources of variability: gate edge roughness (GER), line edge roughness (LER), metal grain granularity (MGG) and random discrete dopants (RDD). We have considered five different extraction methods: the second derivative (SD), constant current (CC), linear extrapolation (LE), third derivative (TD) and transconductance-to-current-ratio (TCR). For the ideal non-deformed device at high drain bias, the effect of the extraction technique can lead to a 137 mV difference in $\mathrm {V_{TH}}$ and an 89 mV/V difference in the drain-induced-barrier-lowering (DIBL), and when considering GER and LER variability, the influence of the extraction method leads to differences in the standard deviation values of the $\mathrm {V_{TH}}$ distribution ( $\sigma \mathrm {V_{TH}}$ ) of up to 2.3 and 3.7 mV respectively, values comparable to intrinsic parameter variations. Therefore, the $\mathrm {V_{TH}}$ extraction technique presents itself as an additional parameter that should be included in performance comparisons as it can heavily impact the results.

Generalized Constant Current Method for Determining MOSFET Threshold Voltage

A novel method for extracting threshold voltage and substrate effect parameters of MOSFETs with constant current bias at all levels of inversion is presented. This generalized constant-current (GCC) method exploits the charge-based model of MOSFETs to extract threshold voltage and other substrate-effect related parameters. The method is applicable over a wide range of current throughout weak and moderate inversion and to some extent in strong inversion. This method is particularly useful when applied for MOSFETs presenting edge conduction effect (subthreshold hump) in CMOS processes using Shallow Trench Isolation (STI).

Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs

In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method for MOSFETs, is developed. The same method is then extended to cover also the case when series resistance is present, while series resistance itself may be determined from the measurement from two FETs with different channel lengths. The key technological and design parameter is the threshold voltage, which may be unambiguously determined from the transconductance-to-current ratio with a constant-current method. The new methods are shown to be effective over a wide range of technical parameters, using technology computer-aided design simulations.

Online Junction Temperature Measurement for SiC MOSFET Based on Dynamic Threshold Voltage Extraction

The online junction temperature monitoring of power devices is a viable technique to ensure the reliable operation of mission-critical power electronic converters. This article provides a potential approach for the junction temperature estimation of SiC MOSFETs based on the dynamic threshold voltage. The proposed method is independent of load current variation, which eliminates the complicated calibration procedure with load current. First, the physical mechanism and the temperature dependence of the dynamic threshold voltage are analyzed. An analytical model for the dynamic threshold voltage is built to investigate the effects of gate loop parameters on the temperature sensitivity and measurement accuracy. Then, the principle of the dynamic threshold voltage measurement circuit is introduced. Finally, the proposed dynamic threshold voltage measurement circuit is experimentally evaluated through the double-pulse tests. The experimental results show that the dynamic threshold voltage of SiC MOSFET has a good linear relationship with junction temperature. The temperature sensitivity of the dynamic threshold voltage of two SiC MOSFETs is approximately 5.2 mV/°C and 19.6 mV/°C, respectively.

An energy-efficient threshold voltage extractor with the burst-mode operation and extended long-term variations using FVF

There are various circuits for extracting threshold voltage (Vth) of CMOS transistors. In this work, we have introduced an energy-efficient threshold voltage extractor with high precision and extended long-term variations. Considering fabrication prohibits, a switched capacitor (SC) has been used instead of a high resistive poly resistor. In order to reduce the power consumption of the Vth extractor, the circuit operates in the burst-mode (energy-efficient). Also, to reduce the glitches in the structure of the SC, a 3rd-order low-pass filter and a replica branch are used. Furthermore, the flipped voltage follower (FVF) structure extends threshold voltage variations over time to measure Vth aging via reasonable resolution data converters. The circuit has been evaluated using 65nm standard CMOS model. The range of Vth variations over 180 months is between 239.4mV and 278.9mV, which is equivalent to a 16.5% change. The power consumption of the entire circuit is less than 11 nW. This circuit is a good candidate to function as a benchmark for the efficiency of high-reliability circuits and aging sensors.