European Solid-State Device Research Conference Research Articles

(Invited) Non Quasi Static Modeling of Printed Organic Thin Film Transistors in Large Signal and Small Signal Operation

As one of the main expected advantages of organic electronics is the low cost, printing technologies are actively investigated for the fabrication of OTFTs.Techniques such as ink-jet or gravure printing frequently results in organic semiconductor (OSC) layers with low crystallinity and relatively low carrier mobility. Moreover, the minimal feature sizes attainable are often in the range of the tens of microns. Hence, the resulting carrier transit time (τ) in the channel of OTFTs can be of the order of tenth of milliseconds with associated cut off frequencies in AC regime in the range of few kilohertz [1].Due to the large tolerances associated to printing processes, the layout of printed OTFTs often includes semiconductor regions whose dimensions are chosen prudently larger than the spacing existing between the source and drain contacts. The presence of the parasitic regions, that is negligible in DC operation, must be accounted in order to accurately reproduce the dynamic operation of these devices.Due to the relatively high value of τ, it is very likely that in practical applications organic circuits are operated with signals varying on a time scale of the same order or shorter than τ. Hence, the carriers in the device don’t have enough time to reach the distribution associated to stationary conditions and the OTFTs enter in non quasi static (NQS) regime of operation. The device response to large variation of its polarization (large signal, LS) becomes dependent on the delay times associated with the high value of τ. Moreover, in NQS regime the device effective admittance in small signal (SS) AC operation is found to be dependent upon the small signal frequency [2][3].Hence, to successfully design electrical circuits employing printed OTFTs, it is necessary to develop compact models that are able to precisely reproduce not only the DC operation but also the LS and SS AC behavior of these devices.In this work, a large signal non quasi static (LS-NQS) compact model has been developed: the model is based on the current continuity equation that, in the case of a MOSFET transistor channel, can be cast as a partial differential equation (PDE) governing the carrier density distribution during time, Q(x,t), in a distributed RC transmission line. In order to solve this PDE, the space variable x is discretized by using a spline collocation approach: the PDE is transformed in a set of ordinary differential equations (ODE) in the time variable t, that can be solved numerically in a “SPICE-like” circuit simulation environment [4], [5].The spline collocation approach allows to choose the number of splines (N) in which the device channels and the parasitic regions are split: by choosing an appropriate value for N it is possible to find the best compromise between computation accuracy and performance.NQS models have been already investigated and developed for crystalline silicon MOSFETs. The model presented in this work differs from the crystalline silicon counterparts in two major aspects:1 – the equations accounting for the charge and current densities are based upon the variable range hopping (VRH) theory that is well suited for amorphous organic semiconductors[6].2 – the model takes into account the presence of parasitic regions by imposing appropriate boundary conditions on their extremities.The LS-NQS model has been implemented in Verilog-A and validated by simulating the electrical behavior of multi-fingered OTFTs, with staggered top-gate configuration, fabricated on PEN substrates by means of a fully printed process. The devices were characterized and simulated in DC, and SS AC operation. A common source amplifier circuit has been realized and measured in LS operation. As can be seen from fig. 1, the model reproduce perfectly the device behavior in LS operation. Moreover, the use of the model has permitted to gain several physical insights concerning the device operation.[1] J. S. Chang et al., IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 7, no. 1, pp. 7–26, Mar. 2017, doi: 10.1109/JETCAS.2017.2673863.[2] A. Valletta et al., IEEE Trans. Electron Devices, vol. 61, no. 12, pp. 4120–4127, Dec. 2014, doi: 10.1109/TED.2014.2364451.[3] J. Leise et al., IEEE Trans. Electron Devices, vol. 67, no. 11, pp. 4672–4676, Nov. 2020, doi: 10.1109/TED.2020.3018094[4] A. Valletta et al. in 2016 46th European Solid-State Device Research Conference (ESSDERC), Lausanne, Switzerland, Sep. 2016, pp. 460–463, doi: 10.1109/ESSDERC.2016.7599685.[5] A. Valletta et al. in 2017 European Conference on Circuit Theory and Design (ECCTD), Catania, Sep. 2017, pp. 1–4, doi: 10.1109/ECCTD.2017.8093225.[6] F. Torricelli et al., IEEE Trans. Electron Devices, vol. 56, no. 1, pp. 20–30, Jan. 2009, doi: 10.1109/TED.2008.2007717. Figure 1

Editorial

Mid-September 2020, we were supposed to hold in Grenoble, France, the 46th edition of the European Solid-State Circuits Conference jointly with the European Solid-State Device Research Conference (ESSDERC-ESSCIRC), which constitute the most important European academic and industrial research meeting dedicated to solid-state circuits and devices.

Editorial

The European Solid-State Device Research Conference (ESSDERC) and its sister conference the European Solid-State Circuit Conference (ESSCIRC) have been organized jointly for more than 40 years in order to provide an annual forum for presenting novel and groundbreaking results, for intense discussion of current hot and emerging topics. Both conferences are widely considered to be Europe’s flagship conferences in microelectronics bringing together device physics experts, semiconductor technologists as well as IC designers from academia and industry. To foster discussions and knowledge exchange between scientists and engineers across the communities, the conferences feature joint sessions as well as plenary presentations.

Editorial to J-EDS ESSDERC 2017 Special Issue

The increasing level of integration for system-on-chip design made available by advances in semiconductor technology is, more than ever before, calling for a deeper interaction among technologists, device experts, IC designers and system designers. With this in mind, the annual conferences European Solid-State Device Research Conference (ESSDERC) and the European Solid-State Circuits Conference (ESSCIRC) have been organized jointly during more than 40 years. Their aim is to provide a forum for the presentation and discussion of recent advances in solid-state devices and circuits. While keeping separate Technical Program Committees (TPC), ESSDERC and ESSCIRC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities.

Historic Memorandum of Understanding Signing at ESSCIRC [Society News

At the European Solid-State Circuits Conference (ESSCIRC) which was held 12-15 September 2016 in Lausanne, Switzerland, a historic memorandum of understanding (MOU) was signed by the ESSCIRC Steering Committee and the IEEE Solid-State Circuits Society (SSCS). This partnership represents a historical union of the Society in alignment with the leading circuit design conference event in Europe. For the past 45 years, the ESSCIRC and the European Solid-State Device Research Conference (ESSDERC) have provided an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. Elaborates on the specifics of the MOU.

Introduction to the Special Issue on the 36th European Solid-State Circuits Conference (ESSCIRC)

The 22 papers in this special issue were originally presented at the 2010 European Solid-State Circuits Conference (ESSCIRC). The conference was jointly organized with the European Solid-State Device Research Conference and held September 14-16 in Seville, Spain. Papers cover the traditional ESSCIRC topics of analog circuits, digital circuits, data converters, sensors and imagers, and communications and RF circuits. Energy harvesting and biomedical circuits were also within ESSCIRC 2010 topics and are represented in this issue.

40th European Solid-State Device Research Conference (ESSDERC)

40th European Solid-State Device Research Conference (ESSDERC)

An EKV-based high voltage MOSFET model with improved mobility and drift model

An EKV-based high voltage MOSFET model is presented. The intrinsic channel model is derived based on the charge based EKV-formalism. An improved mobility model is used for the modeling of the intrinsic channel to improve the DC characteristics. The model uses second order dependence on the gate bias and an extra parameter for the smoothening of the saturation voltage of the intrinsic drain. An improved drift model [Chauhan YS, Anghel C, Krummenacher F, Ionescu AM, Declercq M, Gillon R, et al. A highly scalable high voltage MOSFET model. In: IEEE European solid-state device research conference (ESSDERC), September 2006. p. 270–3; Chauhan YS, Anghel C, Krummenacher F, Maier C, Gillon R, Bakeroot B, et al. Scalable general high voltage MOSFET model including quasi-saturation and self-heating effect. Solid State Electron 2006;50(11–12):1801–13] is used for the modeling of the drift region, which gives smoother transition on output characteristics and also models well the quasi-saturation region of high voltage MOSFETs. First, the model is validated on the numerical device simulation of the VDMOS transistor and then, on the measured characteristics of the SOI-LDMOS transistor. The accuracy of the model is better than our previous model [Chauhan YS, Anghel C, Krummenacher F, Maier C, Gillon R, Bakeroot B, et al. Scalable general high voltage MOSFET model including quasi-saturation and self-heating effect. Solid State Electron 2006;50(11–12):1801–13] especially in the quasi-saturation region of output characteristics.

A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS NAND flash application

A novel channel-program and erase method is presented to replace the FN tunneling operation for SONOS cells in NAND architecture for the first time [Hsu TH, Wu JY, King YC, Lue HT, Shih YH, Lai EK, et al. A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS memory application. In: Tech digest 2006 European solid-state device research conference (ESSDERC); 2006. p. 222–5], [1]. The proposed operation utilizes substrate transient hot electron (STHE) injection and substrate transient hot-hole (STHH) injection for programming and erasing, respectively. Gate bias polarity serves to control whether hot electrons or hot holes are injected into the nitride storage layer. More efficient program and erase operations are achieved compared to the conventional Fowler–Nordheim (FN) tunneling method. The new technique operates at lower programming voltages and with shorter duration pulses, thus increases the programming throughput. Moreover, good program/erase disturb immunity, cycling endurance and data retention are demonstrated.

32nd European Solid-State Circuits Conference (ESSCIRC) and 36th European Solid-State Device Research Conference (ESSDERC)

32nd European Solid-State Circuits Conference (ESSCIRC) and 36th European Solid-State Device Research Conference (ESSDERC)

32nd European Solid-State Circuits Conference (ESSCIRC) and 36th European Solid-State Device Research Conference (ESSDERC)

32nd European Solid-State Circuits Conference (ESSCIRC) and 36th European Solid-State Device Research Conference (ESSDERC)

32nd European Solid-State Circuits Conference (ESSCIRC) and 36th European Solid-State Device Research Conference (ESSDERC)

32nd European Solid-State Circuits Conference (ESSCIRC) and 36th European Solid-State Device Research Conference (ESSDERC)

32nd European Solid-State Circuits Conference (ESSCIRC) and 36th European Solid-State Device Research Conference (ESSDERC)

32nd European Solid-State Circuits Conference (ESSCIRC) and 36th European Solid-State Device Research Conference (ESSDERC)

The European Solid-State Device Research Conference (ESSDERC) and the European Solid-State Circuits Conference (ESSCIRC) 2005

The European Solid-State Device Research Conference (ESSDERC) and the European Solid-State Circuits Conference (ESSCIRC) 2005

The European Solid-State Device Research Conference (ESSDERC) and the European Solid-State Circuits Conference (ESSCIRC) 2005

The European Solid-State Device Research Conference (ESSDERC) and the European Solid-State Circuits Conference (ESSCIRC) 2005

Call for papers for the European Solid-State Device Research Conference and the European Solid-State Circuits Conference (ESSDERC/ESSCIRC'05)

Call for papers for the European Solid-State Device Research Conference and the European Solid-State Circuits Conference (ESSDERC/ESSCIRC'05)

Special section featuring selected papers from the 2000 european solid-state device research conference (ESSDERC)

Special section featuring selected papers from the 2000 european solid-state device research conference (ESSDERC)

Expanded papers from the 1999 European solid-state device research conference

Expanded papers from the 1999 European solid-state device research conference

Solid-state devices

Report on 14th European solid-state device research conference (ESSDERC 84), European Physical Society, 10-13 September, Lille, France.

Solid State Devices, 1976: Invited Papers presented at the Sixth European Solid State Device Research Conference (ESSDERC) held at Technische Universitat, Munich, 13–16 September 1976 (Conference Series No 32)

R Muller and E Lange (eds) London and Bristol: The Institute of Physics 1977 pp 140 price £13, £6.50 (IoP members) The European Solid State Devices Conference is now firmly established as a major forum for the presentation of research work in this field and this volume collects the seven invited papers presented at the meeting held in Munich in 1976. Most of the contributions rightly reflect the pervasive influence of silicon planar technology.