Error Floors Of Low-density Parity-check Research Articles

Doped low-density parity-check codes

In this paper, we propose a doping approach to lower the error floor of Low-Density Parity-Check (LDPC) codes. The doping component is a short block code in which the information bits are selected from the coded bits of the dominant trapping sets of the LDPC code. Accordingly, an algorithm for selecting the information bits of the short code is proposed, and a specific two-stage decoding algorithm is presented. Simulation results demonstrate that the proposed doped LDPC code achieves up to 2.0 ​dB gain compared with the original LDPC code at a frame error rate of 10−6. Furthermore, the proposed design can lower the error floor of original LDPC codes.

A Sub-Graph Expansion-Contraction Method for Error Floor Computation

In this paper, we present a computationally efficient method for estimating error floors of low-density parity-check (LDPC) codes over the binary symmetric channel (BSC) without any prior knowledge of its trapping sets (TSs). Given the Tanner graph $G$ of a code, and the decoding algorithm $\mathcal {D}$ , the method starts from a list of short cycles in $G$ , and expands each cycle by including its sufficiently large neighborhood in $G$ . Variable nodes of the expanded sub-graphs $\mathcal {G}_{\text{EXP}}$ are then corrupted exhaustively by all possible error patterns, and decoded by $\mathcal {D}$ operating on $\mathcal {G}_{\text{EXP}}$ . Union of support of the error patterns for which $\mathcal {D}$ fails on each $\mathcal {G}_{\text{EXP}}$ defines a subset of variable nodes that is a TS. The knowledge of the minimal error patterns and their strengths in each TSs is used to compute an estimation of the frame error rate. This estimation represents the contribution of error events localized on TSs, and therefore serves as an accurate estimation of the error floor performance of $\mathcal {D}$ at low BSC cross-over probabilities. We also discuss trade-offs between accuracy and computational complexity. Our analysis shows that in some cases the proposed method provides a million-fold improvement in computational complexity over standard Monte-Carlo simulation.

Error Floor Estimation of LDPC Decoders — A Code Independent Approach to Measuring the Harmfulness of Trapping Sets

The linear state-space model is a well-known code-independent method to estimate the contribution of a trapping set (TS) structure to the error floor of low-density parity-check (LDPC) codes. In this paper, we provide an in-depth analysis of this method by incorporating a more accurate model for the incoming messages to the TS structure that takes into account the randomness and the correlation among such messages. Based on this analysis, we demonstrate that both randomness and correlation result in the over-estimation of the failure probability of the TS. We then propose an alternate code-independent technique for the error floor estimation of iterative LDPC decoders that can accurately estimate the contribution of different TS structures in the error floor. Compared to the linear state-space model, the proposed method is not only more accurate, but also more general, in that, it is applicable to any saturating iterative message-passing decoder, symmetrically quantized or unquantized, over any memoryless binary-input output-symmetric channel. The proposed technique can be viewed as the local application of importance sampling (IS) to the message-passing algorithm over the subgraph induced by the TS in the code’s Tanner graph. In the message-passing process, to account for the effect of the rest of the Tanner graph, density evolution along with a simple correlation model is used to generate the messages coming into the TS from the rest of the Tanner graph. Extensive simulations demonstrate that the proposed technique can accurately estimate the error floor of LDPC codes over both additive white Gaussian noise (AWGN) channel and binary symmetric channel (BSC), for a variety of iterative decoding algorithms and quantization schemes.

From Cages to Trapping Sets and Codewords: A Technique to Derive Tight Upper Bounds on the Minimum Size of Trapping Sets and Minimum Distance of LDPC Codes

Cages, defined as regular graphs with minimum number of nodes for a given girth, are well-studied in graph theory. Trapping sets are graphical structures responsible for error floor of low-density parity-check (LDPC) codes, and are well investigated in coding theory. In this paper, we make connections between cages and trapping sets. In particular, starting from a cage (or a modified cage), we construct a trapping set in multiple steps. Based on the connection between cages and trapping sets, we then use the available results in graph theory on cages and derive tight upper bounds on the size of the smallest trapping sets for variable-regular LDPC codes with a given variable degree and girth. The derived upper bounds in many cases meet the best known lower bounds and thus provide the actual size of the smallest trapping sets. Considering that non-zero codewords are a special case of trapping sets, we also derive tight upper bounds on the minimum weight of such codewords, i.e., the minimum distance, of variable-regular LDPC codes as a function of variable degree and girth.

Lower Bounds on the Size of Smallest Elementary and Non-Elementary Trapping Sets in Variable-Regular LDPC Codes

Trapping sets are known to be the main cause for the error floor of low-density parity-check (LDPC) codes. They are often classified by their size $a$ and the number of unsatisfied check nodes $b$ in their subgraph. Trapping sets can be partitioned into two categories of elementary and non-elementary , where the first category are those whose subgraph only contains degree-1 and degree-2 check nodes. Empirical results have shown that often the most harmful trapping sets are elementary. In this letter, we derive a lower bound on the size of the smallest non-elementary trapping sets for a given $b$ in variable-regular LDPC codes. The derived lower bound demonstrates that the size of the smallest possible non-elementary trapping set is, in general, larger than that of an elementary trapping set with the same $b$ value. This provides a theoretical justification as to why non-elementary trapping sets are often not among the most harmful trapping sets.

Low Error Floor Concatenated LDPC for MIMO Systems

Multiple-Input and Multiple-Output, or MIMO is the use of multiple antennas at both the transmitter and receiver to improve communication performance. MIMO technology has attracted attention in wireless communications; because it offers significant increases in data throughput and spectral efficiency without additional bandwidth or increased transmit power. To achieve the mentioned above performance Bit Error Rates (BER) should be low. For this reason efficient encoding and decoding algorithms should be used. MIMO systems rely on error-control coding to ensure reliable communication in the presence of noise. Forward Error Correction Codes (FEC) such as convolutional and block codes were investigated for MIMO systems. Low Density Parity Check (LDPC) shows good performance except that an error floor may appear at high Signal to Noise Ratio (SNR). In this work we propose a concatenated error control code that reduces the error floor of LDPC codes suffering from error floor. The proposed scheme is a good candidate for high rates real time communication since it reduces the decoding latency as well.

Lowering the error floor of ADMM penalized decoder for LDPC codes

Decoding by alternating direction method of multipliers (ADMM) is a promising linear programming decoder for low-density parity-check (LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of LDPC codes with ADMM penalized decoder. For the undetected errors that cannot be avoided at the decoder side, we modify the code structure slightly to eliminate low-weight code words. For the detected errors induced by small error-prone structures, we propose a post-processing method for the ADMM penalized decoder. Simulation results show that the error floor can be reduced significantly over three illustrated LDPC codes by the proposed two-step scheme.

A Two-Stage Decoding Algorithm to Lower the Error-Floors for LDPC Codes

A two-stage decoding algorithm to lower the error-floor for low-density parity-check (LDPC) codes is presented. An efficient stopping criterion is proposed to avoid unnecessary iterations in the first stage. If the stopping criterion is reached, the first stage decoding will be terminated and the second stage decoding will be started, where the unsuccessfully decoded words are re-decoded by manipulating the log-likelihood ratio (LLR) of two types of specifically selected variable nodes. Simulation results show that the proposed algorithm can effectively lower the error floor of LDPC codes while maintaining a low decoding complexity.

Error Floor Approximation for LDPC Codes in the AWGN Channel

This paper addresses the prediction of error floors of low-density parity-check codes transmitted over the additive white Gaussian noise channel. Using a linear state-space model to estimate the behavior of the sum-product algorithm (SPA) decoder in the vicinity of trapping sets (TSs), we study the performance of the SPA decoder in the log-likelihood ratio (LLR) domain as a function of the LLR saturation level. When applied to several widely studied codes, the model accurately predicts a significant decrease in the error floor as the saturation level is allowed to increase. For nonsaturating decoders, however, we find that the state-space model breaks down after a small number of iterations due to the strong correlation of LLR messages. We then revisit Richardson's importance-sampling methodology for estimating error floors due to TSs when those floors are too low for Monte Carlo simulation. We propose modifications that account for the behavior of a nonsaturating decoder and present the resulting error floor estimates for the Margulis code. These estimates are much lower, significantly steeper, and more sensitive to iteration count than those previously reported.

Lowering the Error Floor of LDPC Codes Using Cyclic Liftings

Cyclic liftings are proposed to lower the error floor of low-density parity-check (LDPC) codes. The liftings are designed to eliminate dominant trapping sets of the base code by removing the short cycles which are part of the trapping sets. We derive a necessary and sufficient condition for the cyclic permutations assigned to the edges of a cycle ξ of length <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">l</i> (ξ) in the base graph such that the inverse image of ξ in the lifted graph consists of only cycles of length strictly larger than <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">l</i> (ξ). The proposed method is universal in the sense that it can be applied to any LDPC code over any channel and for any iterative decoding algorithm. It also preserves important properties of the base code such as degree distributions, and in some cases, the code rate. The constructed codes are quasi-cyclic and thus attractive from a practical point of view. The proposed method is applied to both structured and random codes over the binary symmetric channel (BSC). The error floor improves consistently by increasing the lifting degree, and the results show significant improvements in the error floor compared to the base code, a random code of the same degree distribution and block length, and a random lifting of the same degree. Similar improvements are also observed when the codes designed for the BSC are applied to the additive white Gaussian noise (AWGN) channel.

Parity-Check Matrix Extension to Lower the Error Floors of Irregular LDPC Codes

Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.

Instanton-based techniques for analysis and reduction of error floors of LDPC codes

We describe a family of instanton-based optimization methods developed recently for the analysis of the error floors of low-density parity-check (LDPC) codes. Instantons are the most probable configurations of the channel noise which result in decoding failures. We show that the general idea and the respective optimization technique are applicable broadly to a variety of channels, discrete or continuous, and variety of sub-optimal decoders. Specifically, we consider: iterative belief propagation (BP) decoders, Gallager type decoders, and linear programming (LP) decoders performing over the additive white Gaussian noise channel (AWGNC) and the binary symmetric channel (BSC). The instanton analysis suggests that the underlying topological structures of the most probable instanton of the same code but different channels and decoders are related to each other. Armed with this understanding of the graphical structure of the instanton and its relation to the decoding failures, we suggest a method to construct codes whose Tanner graphs are free of these structures, and thus have less significant error floors.