Equivalent Gate Oxide Thickness Research Articles

CMOS Scaling Challenges for High Performance and Low Power applications facing Reliability Criteria towards the Decananometer range

The huge improvements in integrated circuits manufacturing has faced great challenges between process optimization, performance requirements and the trade-off between low power operation and reliability for long term use. Both the variability at time zero and the time variability due to external constraints and aging phenomena make mandatory the validation of the CMOS technology nodes from device to circuits and products under operation. While High-K Metal-Gate (HKMG) offered good compromises down to 28nm gate-length, the move to Fully Depleted Silicon on Insulator (FDSOI) allows to further scale the dimension down to 14nm effective gate-length with ultra-thin equivalent gate-oxide thickness (EOT) of 1.35 nm. This has been obtained guarantying a small subthreshold slope for switching, small drain-induced barrier lowering (DIBL) for limited short-channel effect (SCE) and excellent current drivability thanks to a proper gate-stack with HfO2/SiON optimization and adapted rapid thermal processing and annealing. We give new insights to determine first the performance with temperature, the process variability impact at time zero and the robustness of CMOS nodes submitted to interface traps, oxide charge and recoverable traps. Their role is analysed using accelerated DC and AC experiments in devices to SRAM cell and array, focusing on the balance between hot-carrier and bias temperature damage. This allows to guaranty the technology robustness, speed performance and limited power consumption for product qualification.

14‐3: Extremely Short‐Channel LTPS TFT Technologies for High‐Performance Low‐Power, and Reliable AMOLED displays

This paper presents recent progress to scale down low‐temperature polysilicon (LTPS) TFT technologies in the extremely short‐channel length regime for AMOLED displays. Process integration of short‐channel gate and narrow‐width polysilicon into scaled equivalent gate‐oxide thickness (EOT), is explored, in conjunction with enhanced poly crystallization by reducing defect density‐of‐state (DOS) especially in the grain boundaries of the channel region. We obtain more than twice higher current drive (Ion) with significantly‐reduced parasitic gate capacitance, thereby enabling high‐performance high‐frequency panel operations. In addition to superior panel performance in scaled LTPS TFTs, reliable devices are attained, demonstrating robust device characteristics for negative‐bias instability (NBTI) and hot carrier injection (HCI) effects. Physics‐based analysis, based on experimental data and numerical device simulations, is performed to gain more insight in the TFT technologies.

Marine predators algorithm for performance optimization of nanoscale FinFET

Fin-shaped Field Effect Transistors (FinFETs) have proved to be an effective solution when transistors are downscaled and conventional MOSFETs do not perform appreciably well in nanoscale regime. The current work emphasizes on the optimization of Rectzoidal FinFET design at shorter gate length and evaluates short channel effects for 20 nm gate length. Various device dimensions like fin width, fin height, equivalent gate oxide thickness, gate material work-function decide the device performance which is, in fact, measured by leakage current, on-current and short channel effects such as Subthreshold swing. Design and simulations for device have been executed in TCAD tool. After simulations, the performance of designed FinFET structure is optimized with the use of marine predators algorithm (MPA), which is an effective optimization technique inspired from foraging strategy opted by ocean predators. A dataset of fin height and fin width acts as input to artificial neural network, which outputs a trained network. Trained network along with the fitness function is inputted to MPA, and optimized output when verified with TCAD results, produces acceptable results. Fitness function tends to reduce the short channel effects and enhance on-current of device. Approximate optimized fin width and fin height values of designed FinFET are 5 nm and 24 nm respectively. This optimized miniaturized device design is appropriate for transistors which are further employed in numerous nanoscale applications.

Modeling of TID-induced leakage current in ultra-deep submicron SOI NMOSFETs

In order to study the total ionizing dose effects (TID)-induced degradation mechanism of 130 ​nm partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs, a SPICE model including the TID effects was established with Verilog-A.The total ionizing dose effects will lead to the threshold-voltage shift and the leakage current increase of SOI NMOSFETs. The increase of leakage current in the STI region is the main factor leading to degradation of characteristics of devices, which will form a parasitic transistor. Based on the standard BSIM SOI process model, the SPICE model of leakage current of the STI parasitic transistor is added, and the variation of equivalent gate width and gate oxide thickness caused by radiation-induced trapped charges are considered.The devices with different width-length-ratios and different bias conditions are considered in our experiments, and the model can effectively reflect the variation of current characteristics before and after radiation, and provide a reference to develop a radiation-hardening technology.

Influence of the Biomaterial Thickness in a Dielectrically Charged Modulated Fringing Field Bio-Tunnel-FET Device

The biosensor market is expected to increase more than 40% in 5 years ( 2019 to 2024) due to the versatile of these devices (1). Many research groups are studying new types and optimizations of these devices and the tunnel field-effect transistors (TFET) have attracted the interest due to the many advantages of these devices (2).Figure 1 shows the Bio-TFET cross section which has been simulated with TCAD Sentaurus (3). The proposed device has a gate length (LG), equivalent gate oxide thickness (tox) and channel silicon thickness (tSi) of 40 nm, 1 nm and 10 nm. The drain underlap (LUD) is variable in the range of 1 to 100 nm. The uniform doping profile of the device consists of a source and drain doping concentration of 1020 atom/cm3 of boron and arsenic, respectively. An intrinsic channel with 1015 atom/cm3 of boron. The gate electrode has a workfunction of 4.7 eV. The main models incorporated in the simulation were the bandgap narrowing (BGN), Shockley Read Hall recombination (SRH) and the nonlocal band-to-band tunneling (BTBT). In the drain underlap region is deposited a biomaterial for biosensing purposes. This material has a dielectric constant (k, where ε=k*ε0) of 1 (air), 2.1 (Streptavidin), 3.57 (APTES), 8 (Anti-Iris antibody) and 10 (Isoquinoline) (4).Figure 2 shows the Bio-TFET transfer characteristics. The ambipolar region is a parasitic tunneling current that occurs for negative gate bias (VG) for nTFET at drain to channel region. In order to decrease this effect a drain underlap (LUD) is performed at the device (5). However, when the biomaterial dielectric constant (k) increases, the ambipolar current also increases orders of magnitude, meaning that the device is very susceptible to k variation in the biomaterial region and can be used for biosensing of different types of biomolecules with a distinct k. In order to quantify the influence of change in k in the biomaterial region the equation in terms of ID: Sensitivity = ΔID/ID(Ref.) was used. Where ΔID represents the difference between the drain current of biosensing (output), e.g., the drain current with the presence of biomaterial ID(Bio) and the drain current of reference ID (Ref.) (input), e.g., drain current without biomaterial ID (k=1) . Both for a fixed value of gate voltage (VG = -2 V) in the ambipolar region. Fig.3 shows the sensitivity of the device as a function of LUD for different k values. The maximum sensitivity occurs for a LUD = 30 nm for all range of k values. The sensitivity increases for higher k as reported in (6). Another parameter that is important for sensing is the dimension of the target. Many biomolecules have different types, e.g., spherical, ellipsoidal or elongated (7). Therefore, the study of the parameter is fundamental for the functional operation of the device. In Fig.4 the sensitivity is analyzed as a function of biomaterial thickness (tBio) for a fixed value of LUD=30nm. With the rising of tBio and k the sensitivity increases, i.e., exceeding 2 orders of magnitude comparing tBio = 10nm and tBio = 30 nm for k = 10. This increment on sensitivity is due to the tunneling length lowering, as can be noticed in Fig.5. The tunneling length decrease from 5.7 nm (tBio= 10 nm) to 9.5 nm (tBio = 30 nm), both for k = 10 and fixed energy of - 1 eV. The lowering of the tunneling length increases the ambipolar current ID(Bio) that enhances the sensitivity of the device. An important consideration for the biosensing process is the charge on the biomaterial that affect the tunneling current and therefore affect the sensitivity of the device. In Fig. 6, the sensitivity is studied as in the function of positive fixed charges in the range of 1010 to 1012 cm-2. The sensitivity increases for thicker values of tBio. This is due to the higher effect of the fringing field in the region. As tBio increase the effect of fringing field increases in the biomaterial region and as consequence, the device becomes more sensible with the presence of charges.The study of charges and biomaterial thickness in a dielectrically modulated fringing field Bio-TFET was performed in this work. The device shows high sensitivity with the increase of tBio in the range studied in this work. Although, the effect of fixed charges is more notable for thicker tBio. Then, the tBio thickness shows a high impact in the sensing of the device. Figure 1

(Invited) Massively Parallel, Aligned Arrays of Semiconducting Carbon Nanotubes for Realizing Field Effect Transistors with Current Density Exceeding Silicon and Gallium Arsenide

Calculations have indicated that aligned arrays of semiconducting carbon nanotubes (CNTs) promise to outperform conventional semiconducting materials in short-channel, aggressively scaled field effect transistors (FETs) like those used in semiconductor logic and high frequency amplifier technologies. These calculations have been based on extrapolation of measurements of FETs based on one CNT, in which ballistic transport approaching the quantum conductance limit of 2Go =4e2/h has been achieved. However, constraints in CNT sorting, processing, alignment, and contacts give rise to non-idealities when CNTs are implemented in densely-packed parallel arrays, which has resulted in a conductance per CNT far from 2Go . The consequence has been that it has been very difficult to create high performance CNT array FETs, and CNT array FETs have not outperformed but rather underperformed channel materials such as Si by 6x or more. Here, we report nearly ballistic CNT array FETs at a density of 50 CNTs um-1, created via CNT sorting, wafer-scale alignment and assembly, and treatment. The on-state conductance in the arrays is as high as 0.46 Go per CNT, and the conductance of the arrays reaches 1.7 mS um-1, which is 7x higher than previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density reaches 900 uA um-1 and is similar to or exceeds that of Si FETs when compared at equivalent gate oxide thickness, off-state current density, and channel length. The on-state current density exceeds that of GaAs FETs, as well. This leap in CNT FET array performance is a significant advance towards the exploitation of CNTs in high-performance semiconductor electronics technologies. *Brady GJ, Way AJ, Safron NS, Evensen HT, Gopalan P, Arnold MS, Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs, SCIENCE ADVANCES, 2 (9), e1601240 (2016)

Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm2 @ (V fb − 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of −0.5 to −2 V. Under the same physical thickness and process flow, lower EOT and higher I on/I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO2. With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on, I on/I off ratio in the magnitude of 105, and peak transconductance, as well as suitable threshold voltage (−0.3~−0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

Superior Reliability of Gate-All-Around Polycrystalline Silicon Thin-Film Transistors with Vacuum Cavities Next to Gate Oxide Edges

The electrical characteristics and reliability of n-type gate-all-around (GAA) polycrystalline silicon thin-film transistors (poly-Si TFTs) with vacuum cavities next to the gate oxide edges are investigated. This novel structure is successfully fabricated by spacer formation, partial wet etching of a gate oxide, and in situ vacuum encapsulation. The electrical characteristics of the GAA poly-Si TFTs with vacuum cavities are superior to those of traditional GAA poly-Si TFTs because the vacuum cavity serves as an offset region to decrease the leakage current in the OFF state and as a field-induced drain (FID) to sustain the on-current in the ON state. In addition, regardless of whether static or dynamic electrical stress is imposed on these devices, the GAA poly-Si TFTs with vacuum cavities exhibit superior reliability to traditional ones owing to the simultaneous reduction of vertical and lateral electric fields near the drain junction during bias stressing due to the greater equivalent gate oxide thickness on the gate electrode edges.

Temperature Coefficient of Threshold Voltage in High-k Metal Gate Transistors with Various TiN and Capping Layer Thicknesses

The temperature coefficient of Vth (=dVth/dT), which is commonly utilized for circuit design, was systematically obtained against various TiN and capping layer thicknesses in high-k/metal gate field-effect transistors (FETs). It is known that the magnitude of |dVth/dT| for such FETs is larger than that of polycrystalline silicon (poly-Si) gate FETs. The origins of the dVth/dT difference among high-k/metal gate FETs were attributed to differences in the temperature coefficient of flat band voltage (=dVFB/dT) and the equivalent gate oxide thickness (EOT). Thicker TiN layers reduced dVFB/dT, which enlarged the magnitude of |dVth/dT|. The EOT increased as the TiN metal layer or Al2O3 capping layer increased in thickness. The large EOT led to an increase in |dVth/dT|, since dVth/dT is a function of the inverse of gate capacitance. In contrast, La2O3 capping hardly affected dVth/dT. This is because La2O3 capping did not affect EOT differently from Al2O3 capping. The relationship between dVth/dT and EOT implies that EOT scaling relieves the issue of large |dVth/dT| for high-k/metal gate FETs.

Numerical Study on a Lateral Double-Gate Tunnelling Field EffectTransistor

A novel lateral double-gate tunnelling field effecttransistor (DG-TFET) is studied and its performance is presented by atwo-dimensional device simulation with code ISE. The result demonstrates that thisnew tunnelling transistor allows for the steeper sub-threshold swing below60 mV/dec, the super low supply voltage (operable at VDD<0.3 V) and therail-to-rail logic (significant on-state current at the drain-source voltage VDS = 50 mV) for the aggressive technology assumptions of the availability ofhigh-k/metal stack with equivalent gate oxide thickness EOT = 0.24 nm andthe work function difference 4.5 eV of materials.

Application of high-K gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology

High-k gate dielectrics and metal gate electrodes are required for enabling continued equivalent gate oxide thickness scaling, and hence high performance, and for controlling gate oxide leakage for...

Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology

High-κ gate dielectrics and metal gate electrodes are required for enabling continued equivalent gate oxide thickness scaling, and hence high performance, and for controlling gate oxide leakage for both future silicon and emerging non-silicon nanoelectronic transistors. In addition, high-κ gate dielectrics and metal gates are required for the successful demonstration of high performance logic transistors on high-mobility non-silicon substrates with high ION/IOFF ratios.

Scaling considerations for high performance 25 nm metal–oxide–semiconductor field effect transistors

This article presents a systematic simulation-based study on scaling gate oxide thickness and the source–drain extension junction depth to achieve high performance 25 nm metal–oxide–semiconductor field effect transistor devices for low power operation. In order to obtain the target 25 nm devices, complementary metal–oxide–semiconductor (CMOS) technologies were designed by scaling source–drain extension junction depths to 14, 20, and 26 nm and the corresponding gate lengths to 40, 50, and 60 nm, respectively. Each technology was separately optimized for each value of the equivalent gate oxide thickness 1, 1.5, and 2 nm to achieve the target value of off-state leakage current of about 10 nA/μm for 25 nm devices. The simulation results show that for a low voltage operation of 25 nm devices with a fixed off-state leakage current, the magnitude of threshold voltage, subthreshold slope, and the drain-induced barrier lowering is too high while the magnitude of drive current is too low for gate oxide thickness ⩾1.5 nm. However, the variation in the magnitude of threshold voltage, subthreshold slope, drain-induced barrier lowering, and the drive current for the similar devices is insignificant within the range of source–drain extension junction depth between 14 and 26 nm. It is also found that the increase in the gate delay is ⩾12% for 25 nm devices with the source–drain extension junction depth ⩾20 nm compared to the similar devices with a source–drain extension junction depth of about 14 nm. This article demonstrates that the continuous scaling of gate oxide thickness below 1.5 nm and the source–drain extension junction depth below 20 nm is essential for achieving high performance CMOS technologies with 25 nm nominal devices for low power application.

Design considerations for 25 nm MOSFET devices

This paper presents the results of a systematic theoretical investigation on scaling gate oxide thickness and the source-drain extension (SDE) junction depth to design high performance MOSFET devices with effective channel lengths near 25 nm. In order to obtain 25 nm MOSFETs, CMOS technologies with 40, 50, and 60 nm gate lengths were designed by scaling SDE junction depth to 14, 20, and 26 nm, respectively. Each technology with the target gate oxide thickness was optimized for an off-state leakage current ∼10 nA/μm for 25 nm devices and the device characteristics were obtained for an equivalent gate oxide thickness of 1, 1.5, and 2 nm. The results show that for a target off-state leakage current of 25 nm devices the magnitude of threshold voltage, sub-threshold slope, and drain-induced barrier lowering increases while the magnitude of drive current decreases with the increase of gate oxide thickness. On the other hand, the variation in the magnitude of threshold voltage, sub-threshold slope, drain-induced barrier lowering, and the drive current for the similar devices is insignificant within the range of SDE junction depth 14–26 nm. It is, also, found that the gate delay for 25 nm devices increases with the increase of SDE junction depth. This study, clearly, demonstrates the importance of scaling gate oxide thickness and the SDE junction depth below the presently reported limits to design high performance 25 nm MOSFET devices for low voltage application.