Energy Overhead Research Articles

Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication

Stream processing, which involves real-time computation of data as it is created or received, is vital for various applications, specifically wireless communication. The evolving protocols, the requirement for high-throughput, and the challenges of handling diverse processing patterns make it demanding. Traditional platforms grapple with meeting real-time throughput and latency requirements due to large data volume, sequential and indeterministic data arrival, and variable data rates, leading to inefficiencies in memory access and parallel processing. We present Canalis, a throughput-optimized framework designed to address these challenges, ensuring high-performance while achieving low energy consumption. Canalis is a hardware-software co-designed system. It includes a programmable spatial architecture, FluxSPU (Flux Stream Processing Unit), proposed by this work to enhance data throughput and energy efficiency. FluxSPU is accompanied by a software stack that eases the programming process. We evaluated Canalis with eight distinct benchmarks. When compared to CPU and GPU in mobile SoC to demonstrate the effectiveness of domain specialization, Canalis achieves an average speedup of 13.4× and 6.6×, and energy savings of 189.8× and 283.9×, respectively. In contrast to equivalent ASICs of the benchmarks, the average energy overhead of Canalis is within 2.4×, successfully maintaining generalizations without incurring significant overhead.

Energy-Efficient Routing Approach Based on Free Hold Participation and Acquisition Hierarchical Network of Forwarder Nodes in WSNs.

Wireless sensor network (WSNs) is one of the emerging technologies which has found widespread applications in nearly all spheres of our lives and its deployment and span of functionality is increasing day by day. Ongoing research in Wireless Sensor Networks (WSN) focuses on achieving maximum energy efficiency during the operational lifetime of its constituent nodes. A major challenge for manufacturers lies in producing tiny low-cost sensor nodes. Inherent to sensor network adoption is the use of very low power methods for radio communication and data acquisition. WSNs use Multiple-hop communication through single next-hop node, which may suffer from hold ups or bottlenecks. Resultant collisions and retransmissions impose an Energy Overhead. Low throughput caused due to retransmission/collisions affects the performance quotient of a WSN. It has emerged over the course of study and observations that Overhearing nodes are always ignored (Ignored free hold participation).

Random memristor-based dynamic graph CNN for efficient point cloud learning at the edge

The broad integration of 3D sensors into devices like smartphones and AR/VR headsets has led to a surge in 3D data, with point clouds becoming a mainstream representation method. Efficient real-time learning of point cloud data on edge devices is crucial for applications such as autonomous vehicles and embodied AI. Traditional machine learning models on digital processors face limitations, with software challenges like high training complexity, and hardware challenges such as large time and energy overheads due to von Neumann bottleneck. To address this, we propose a software-hardware co-designed random memristor-based dynamic graph CNN (RDGCNN). Software-wise, we transform point cloud into graph, and propose random EdgeConv for efficient hierarchical and topological features extraction. Hardware-wise, leveraging memristor’s intrinsic stochasticity and in-memory computing capability, we achieve significant reductions in training complexity and energy consumption. RDGCNN demonstrates high accuracy and efficiency across various point cloud tasks, paving the way for future edge 3D vision.

Kaizen: A Street Smart Low Latency-Aware Resource Choreography Scheme for Decentralized Autonomous Organization (DAO) and Non-DAO Based Application Execution Over Blockchain and MEC Empowered 6 G Network

Decentralized autonomous organization (DAO)-based applications can revolutionize traditional centralized decision-making procedures and services by enabling scalable, decentralized, autonomous, and democratized decision-making processes. Unlike traditional applications, DAO-based decentralized applications use Ethereum blockchain-based smart contract programs to execute policies or make automated decisions. To that end, 6 G technologies can improve the latency and reliability of many existing blockchain-based DAOs. Previous research did not investigate the execution of DAO and non-DAO-based applications, as well as an adaptive resource choreography scheme, while accounting for various 6 G technologies, blockchain, and mobile-edge cloud (MEC). To prevail over the previous shortcomings, this article supplies a street smart multi-platform coordination, application scheduling, and low-latency-aware resource choreography scheme for both DAO and non-DAO-based application execution over blockchain and MEC-enabled 6 G networks by taking heterogenous DAO and non-DAO application count, application requirements, physical worker, virtual worker, and communication resource status into account. The results verified that the proposed kaizen scheme delivers at least 11.26% app work completion delay gain, 7.2% user energy overhead gain, 6.55% user economic charge gain, and 21% service provider profit than the compared schemes.

Room Temperature Single Photon Detection at 1550 nm Using van der Waals Heterojunction

AbstractSingle‐photon detectors (SPDs) are crucial in applications ranging from space, biological imaging to quantum communication and information processing. The SPDs that operate at room temperature are of particular interest to broader application space as the energy overhead introduced by cryogenic cooling can be avoided. Although silicon‐based single photon avalanche diodes (SPADs) are well‐matured and operate at room temperature, the bandgap limitation restricts their operation at telecommunication wavelength (1550 nm) and beyond. InGaAs‐based SPADs, on the other hand, are sensitive to 1550 nm photons but suffer from relatively lower efficiency, high dark count rate, afterpulsing probability, and pose hazards to the environment from the fabrication process. In this work, the properties of nanomaterials that can be leveraged to address these challenges are demonstrated and a room‐temperature single‐photon detector capable of operating at 1550 nm is realized. This is achieved by coupling a low bandgap (≈ 350 meV) absorber (black phosphorus) to a sensitive van der Waals probe that is capable of detecting discrete electron fluctuation. The device is optimized for operation at 1550 nm and demonstrates an overall quantum efficiency of 21.4% (estimated as 42.8% for polarized light), and a minimum dark count of ≈ 720 Hz at room temperature.

CRPIM: An efficient compute-reuse scheme for ReRAM-based Processing-in-Memory DNN accelerators

Resistive random access memory (ReRAM) is a promising technology for AI Processing-in-Memory (PIM) hardware because of its compatibility with CMOS, small footprint, and ability to complete matrix–vector multiplication workloads inside the memory device itself. However, redundant computations are brought on by duplicate weights and inputs when an MVM has to be split into smaller-granularity sequential sub-works in the real world. Recent studies have proposed repetition-pruning to address this issue, but the buffer allocation strategy for enhancing buffer device utilization remains understudied. In preliminary experiments observing input patterns of neural layers with different datasets, the similarity of repetition allows us to transfer the buffer allocation strategy obtained from a small dataset to the computation with a large dataset. Hence, this paper proposes a practical compute-reuse mechanism for ReRAM-based PIM, called CRPIM, which replaces repetitive computations with buffering and reading. Moreover, the subsequent buffer allocation problem is resolved at both inter-layer and intra-layer levels. Our experimental results demonstrate that CRPIM significantly reduces ReRAM cells and execution time while maintaining adequate buffer and energy overhead.

The Indirect Effect of Lightning Electromagnetic Pulses on Electrostatic, Electromagnetic Fields and Induced Voltages in Overhead Energy Transmission Lines

The impact of a lightning electromagnetic pulse (LEMP) on a power line or power station produces an effect similar to that of switching between a significant power source and a power line circuit. This switch closure causes a sudden change in routing conditions, creating a transient state. This situation has been studied in terms of electrostatic and electromagnetic induction, as well as overvoltage changes. Appropriate mathematical models were used to analyze these changes. While vertical electric field analysis has been carried out in a few studies, magnetic field and horizontal electric field vectors have not been studied. In this study, the Rusck formulation and the Heidler current formulation are combined at the current level, developed and analyzed. This is because the Rusck expression can sometimes give incorrect results at the current level. Also, in the analysis, electromagnetic field formulations based on accelerating charges are used instead of the dipole approximation to eliminate the need for interpolation in the graphical results. In contrast to other studies in the literature, this study proposes the use of moving and accelerating load techniques to better understand the effects of LEMPs on power transmission lines. Also, in this study, the double exponential problem of the current form in Rusck’s formulation is addressed in order to obtain a close approximation of the physical form of the LEMP. Additionally, the field–line (coupling) relationship is studied according to a unique closed formulation, leading to important determinations about the overvoltages generated on a line depending on the propagation speed of the LEMP sprout and the electrical changes in the area where the LEMP first occurs.

A Survey of Emerging Memory in a Microcontroller Unit.

In the era of widespread edge computing, energy conservation modes like complete power shutdown are crucial for battery-powered devices, but they risk data loss in volatile memory. Energy autonomous systems, relying on ambient energy, face operational challenges due to power losses. Recent advancements in emerging nonvolatile memories (NVMs) like FRAM, RRAM, MRAM, and PCM offer mature solutions to sustain work progress with minimal energy overhead during outages. This paper thoroughly reviews utilizing emerging NVMs in microcontroller units (MCUs), comparing their key attributes to describe unique benefits and potential applications. Furthermore, we discuss the intricate details of NVM circuit design and NVM-driven compute-in-memory (CIM) architectures. In summary, integrating emerging NVMs into MCUs showcases promising prospects for next-generation applications such as Internet of Things and neural networks.

Margin Elimination in a 55 nm Near-Threshold Microcontroller with Adaptive Prediction Capability and Voltage Scaling

This paper presents an innovative approach for error prediction (EP) tailored to near-threshold operations, addressing the energy-efficient requirements of digital circuits in applications such as IoT devices and wearables. The novel EP technique combines the benefits of error prediction and detection, effectively addressing critical issues associated with each method by enabling adaptive prediction capability and voltage scaling. More specifically, the presented EP method requires no modifications to the processor pipeline and mitigates the generation of false-positive errors, ensuring stable operation of the system at high-efficiency points. The effectiveness of this strategy is demonstrated through its implementation in a near-threshold 32-bit microprocessor system with a modest 5.82% area overhead. Silicon measurements validate the adaptive EP system from 0.59 to 0.66 V (4–32 MHz) and confirm its removal of all voltage margins. Here, the EP technique reduces the energy consumption by 18.6–25.1% with respect to the signoff margins and it allows the system to operate without energy overhead compared to its ideal non-margined critical operation point, with less than a 5% throughput loss.

LEC-MiCs: Low-Energy Checkpointing in Mixed-Criticality Multi-Core Systems

With the advent of multicore platforms in designing Mixed-Criticality Systems (MCSs), simultaneous management of reliability and energy while guaranteeing an acceptable service level for low-criticality tasks is a crucial challenge. To ensure the reliability of the MCSs against transient faults, fault-tolerant techniques are employed which will increase energy consumption. To mitigate the energy overhead, the Dynamic Voltage and Frequency Scaling (DVFS) technique will be exploited. However, this technique might lead to violating the timing constraints of high-criticality tasks. Therefore, this paper presents, for the first time, the low-energy checkpointing technique to guarantee the reliability of multiple preemptive periodic mixed-criticality tasks in a multicore platform. In contrast to the previous works in checkpointing technique which consider a specific number of faults that all the tasks in the system should tolerate, in this paper, the number of tolerable faults for each execution section of a task, and in each voltage and frequency level is determined through proposed formulas to meet the reliability target based on safety standards. Then, our proposed method determines the number of checkpoints and their non-uniform intervals for the normal and overrun sections of each task to reduce energy consumption, respectively. Moreover, the unified demand bound function (DBF) analysis is proposed for analyzing the schedulability of the task set, where each high-criticality task meets its timing and reliability constraints, and low-criticality tasks execute based on their derived guaranteed periods in each operational mode of the system. Experimental results show that our proposed scheme meets the timing and reliability constraints while at the same time, improving the QoS of low-criticality tasks, and managing energy consumption with an average of 29.49%, and 32.78%, respectively.

Memristor-CMOS Hybrid Circuits Implementing Event-Driven Neural Networks for Dynamic Vision Sensor Camera.

For processing streaming events from a Dynamic Vision Sensor camera, two types of neural networks can be considered. One are spiking neural networks, where simple spike-based computation is suitable for low-power consumption, but the discontinuity in spikes can make the training complicated in terms of hardware. The other one are digital Complementary Metal Oxide Semiconductor (CMOS)-based neural networks that can be trained directly using the normal backpropagation algorithm. However, the hardware and energy overhead can be significantly large, because all streaming events must be accumulated and converted into histogram data, which requires a large amount of memory such as SRAM. In this paper, to combine the spike-based operation with the normal backpropagation algorithm, memristor-CMOS hybrid circuits are proposed for implementing event-driven neural networks in hardware. The proposed hybrid circuits are composed of input neurons, synaptic crossbars, hidden/output neurons, and a neural network's controller. Firstly, the input neurons perform preprocessing for the DVS camera's events. The events are converted to histogram data using very simple memristor-based latches in the input neurons. After preprocessing the events, the converted histogram data are delivered to an ANN implemented using synaptic memristor crossbars. The memristor crossbars can perform low-power Multiply-Accumulate (MAC) calculations according to the memristor's current-voltage relationship. The hidden and output neurons can convert the crossbar's column currents to the output voltages according to the Rectified Linear Unit (ReLU) activation function. The neural network's controller adjusts the MAC calculation frequency according to the workload of the event computation. Moreover, the controller can disable the MAC calculation clock automatically to minimize unnecessary power consumption. The proposed hybrid circuits have been verified by circuit simulation for several event-based datasets such as POKER-DVS and MNIST-DVS. The circuit simulation results indicate that the neural network's performance proposed in this paper is degraded by as low as 0.5% while saving as much as 79% in power consumption for POKER-DVS. The recognition rate of the proposed scheme is lower by 0.75% compared to the conventional one, for the MNIST-DVS dataset. In spite of this little loss, the power consumption can be reduced by as much as 75% for the proposed scheme.

Secure and lightweight message dissemination framework for internet of vehicles

AbstractThe Internet of Vehicles (IoV) revolutionizes vehicle communication in dynamic networks. Message dissemination in IoV involves sharing critical information for the safety and convenience of the IoV network. It is very crucial to secure message dissemination due to potential cyber‐attacks, traffic disruptions, and privacy breaches. Data integrity, authentication, and privacy are vital to maintaining trust and safety in the IoV network. This network consists of resource‐constrained IoV devices with limited resources due to the availability of embedded components in vehicular systems. Therefore, optimizing algorithms and protocols is crucial for efficient vehicle‐to‐everything (V2X) communication, enhancing safety and transportation efficiency. Solutions often include lightweight protocols and secure message exchange. This paper proposes a machine learning (ML) based secure and lightweight message dissemination framework for resource‐constrained IoV. First, we present an ML‐based threat classification model capable of effectively categorizing adversarial and nonadversarial data streams and delivering an optimized model with superior accuracy. Furthermore, we also propose a secure message dissemination scheme using lightweight cryptographic primitives, which significantly reduces computational, communication, and energy overhead. To validate the robustness of our proposed ML‐based secure and lightweight message dissemination framework, we evaluate it using various security parameters and performance measures such as computation cost, communication cost, energy cost, accuracy, precision, recall, and F1‐score. Our contributions promise to significantly enhance the security and efficiency of message dissemination in IoV environments and advance lightweight, secure, and reliable transportation systems for the future.

ApHMM: Accelerating Profile Hidden Markov Models for Fast and Energy-efficient Genome Analysis

Profile hidden Markov models (pHMMs) are widely employed in various bioinformatics applications to identify similarities between biological sequences, such as DNA or protein sequences. In pHMMs, sequences are represented as graph structures, where states and edges capture modifications (i.e., insertions, deletions, and substitutions) by assigning probabilities to them. These probabilities are subsequently used to compute the similarity score between a sequence and a pHMM graph. The Baum-Welch algorithm, a prevalent and highly accurate method, utilizes these probabilities to optimize and compute similarity scores. Accurate computation of these probabilities is essential for the correct identification of sequence similarities. However, the Baum-Welch algorithm is computationally intensive, and existing solutions offer either software-only or hardware-only approaches with fixed pHMM designs. When we analyze state-of-the-art works, we identify an urgent need for a flexible, high-performance, and energy-efficient hardware-software co-design to address the major inefficiencies in the Baum-Welch algorithm for pHMMs. We introduce ApHMM , the first flexible acceleration framework designed to significantly reduce both computational and energy overheads associated with the Baum-Welch algorithm for pHMMs. ApHMM employs hardware-software co-design to tackle the major inefficiencies in the Baum-Welch algorithm by (1) designing flexible hardware to accommodate various pHMM designs, (2) exploiting predictable data dependency patterns through on-chip memory with memoization techniques, (3) rapidly filtering out unnecessary computations using a hardware-based filter, and (4) minimizing redundant computations. ApHMM achieves substantial speedups of 15.55×–260.03×, 1.83×–5.34×, and 27.97× when compared to CPU, GPU, and FPGA implementations of the Baum-Welch algorithm, respectively. ApHMM outperforms state-of-the-art CPU implementations in three key bioinformatics applications: (1) error correction, (2) protein family search, and (3) multiple sequence alignment, by 1.29×–59.94×, 1.03×–1.75×, and 1.03×–1.95×, respectively, while improving their energy efficiency by 64.24×–115.46×, 1.75×, and 1.96×.

Reinforcement learning-based dynamic pruning for distributed inference via explainable AI in healthcare IoT systems

Deep Neural Networks (DNNs) have become the key technique to revolutionize the healthcare sector. However, conducting online remote inference is often impractical due to privacy constraints and latency requirements. To enable local computation, researchers have attempted network pruning with minimal accuracy loss or DNN distribution without affecting the performance. Yet, distributed inference can be inefficient due to the energy overhead and fluctuation of communication channels between participants. On the other hand, given that realistic healthcare systems use pre-trained models, local pruning and retraining relying only on the available scarce data is not possible. Even pre-pruned DNNs are limited in their ability to customize to the local load of data and device dynamics. The online pruning of DNN inferences without retraining is viable; however, it was not considered in the literature as most well-known techniques do not perform well without adjustment. In this paper, we propose a novel pruning strategy using Explainable AI (XAI) to enhance the performance of pruned DNNs without retraining, a necessity due to the scarcity and bias of local healthcare data. We combine distribution and pruning techniques to perform online distributed inference assisted by dynamic pruning when needed for highest accuracy. We use Non-Linear Integer Programming (NLP) to formulate our approach as a trade-off between resources and accuracy, and Reinforcement Learning (RL) to relax the problem and adapt to dynamic requirements. Our pruning criterion shows high performance compared to other reference techniques and ability to assist distribution by reducing resource usage while keeping high accuracy.

Research on Storage Structure Design and Performance Optimization Strategy of Embedded System for Low-Capacity Storage Units

Abstract Embedded systems have attracted great attention with their unique information processing ability and human-computer interaction ability, and how to improve the processing efficiency of embedded systems for low-capacity storage units has become a key topic of current research. Based on the data storage structure characteristics and hardware devices of embedded systems, we complete the task of storage structure design for embedded systems and describe the interaction mechanism of Cache storage mode and low-capacity storage mode. Using the POSE algorithm, we optimize the execution efficiency and module energy overhead in the storage structure of the embedded system and test and optimize the embedded system. The low-capacity storage mode has fewer physical block erasures than the Cache storage mode, and the response time is 15-50 ms less. Similarly, the PEOS algorithm has advantages in the optimization of the energy overhead of the embedded system, which ranges from 0 to 0.23 × 104. This study can effectively improve the execution efficiency and energy overhead of the storage, which is of great significance for its further development.

Application of Artificial Intelligence in Computer Neural Network Algorithm Technology in the Age of Big Data

Abstract The arrival of the big data era makes the amount of data explosive growth, which puts forward new challenges and demands for computer network technology, and the integration of big data and network technology has become an important trend. This paper uses the optimization strategy and the elimination mechanism of the genetic algorithm to optimize the inertia weight and particle position speed updating mechanism of the particle swarm algorithm and combines the searching method of the Tennessee whisker algorithm with the sharing mechanism of the particle swarm algorithm to achieve the optimal data searching ability. Finally, the improved artificial intelligence algorithm and MapReduce are combined to improve the performance of the computer neural network algorithm in big data processing. The average data redundancy rate of this paper’s algorithm for big data processing is only 1.18%, and the resource integration checking rate always exceeds 85%, according to simulation experiments. In addition, the algorithm also shows good performance in practical applications, and it can achieve accurate classification of big data labels in big data label classification tasks while maintaining a low energy overhead. Meanwhile, it can accurately recognize electronic medical record data in large medical databases. Big data processing can benefit greatly from the proposed neural network algorithm in this paper.

A hybrid model for energy-efficient Green Internet of Things enabled intelligent transportation systems using federated learning

In the rapidly evolving Internet of Things domain, managing voluminous data streams while ensuring energy efficiency remains a cardinal challenge. Our research introduces a hybrid model designed specifically for an IoT system. This paper sheds light on our unique framework that emphasizes efficient communication and prioritizes energy conservation. The innovative model architecture is lightweight, fostering compatibility with resource-constrained devices and paving the way for personalized federated averaging during training. A crucial highlight of our methodology includes local training using lightweight optimization instead of traditional data transmission, reducing energy overheads considerably. Furthermore, we propose a novel approach for model aggregation using personalized energy-aware averaging. This process iteratively refines a global model by aggregating received updates, drastically reducing the data transfer compared to conventional methods. Lastly, we integrate an energy-aware updates management system, continually monitoring device energy metrics and making adaptive data transmission and model update decisions. The model ensures optimal participation in global updates by consistently monitoring devices’ energy metrics and setting adaptive thresholds. This study leverages the richly annotated Udacity Self-Driving Car Dataset provided by Roboflow to evaluate a novel federated learning model to optimize energy consumption for IoT systems. Our experiments simulate real-world collaborative learning scenarios using the TensorFlow Federated (TFF). Our focus on energy consumption evaluation revealed that our proposed model offers significant energy savings when analyzed based on data communication round time and individual node training duration. A comparative analysis between the proposed and traditional models uncovers substantial improvements in energy efficiency. In our experiments, the proposed approach demonstrated a commendable accuracy of 93.27%. Notably, the local communication time was streamlined to 1.21 s, while the global communication was efficiently clocked at 4.76 s. When compared to traditional methods, these results not only underscore the effectiveness and efficiency of our methodology in the context of IoT systems but also highlight its superior performance.

Efficient Low-Power Timing-Error Control in Digital Integrated Circuits Using Timing Error-Tolerant Circuits and Time-Borrowing Techniques

In modern digital systems, real-time operation of integrated circuits is of paramount importance. Presently, a significant portion of energy consumption is attributed to the overhead incurred by accommodating worst-case scenarios. This research proposes an energy-efficient timing-error control method employing a circuit designed to tolerate timing errors. The critical path is adept at identifying and correcting timing errors, particularly those causing irregular data transitions following the rising edge of the clock. Management of the transparent window of the clock is instrumental in swiftly addressing timing faults using minimal logic. A novel time-borrowing technique is introduced to account for future errors, applicable to locations with a short flip-flop setup time. The timing mistake occurs in two stages, and during second stage, an organized clock ensures a sufficiently extended transparent window, allowing for preservation of regular data without necessitating alterations to system clock. The study utilizes Razor Flip-flop and Adaptive Hold Logic to detect and recover from timing issues. This low-power timing-error control method provides an efficient means of mitigating the energy overhead associated with worst-case scenario margins in real-time digital systems.

ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories

Ferroelectric Field Effect Transistors (FeFETs) have spurred increasing interest in both memories and computing applications, thanks to their CMOS compatibility, low-power operation, and high scalability. However, new security threats to the FeFET-based memories also arise. A major threat is the power analysis side-channel attack (P-SCA), which exploits the power traces of the memory access to obtain data information. There have been several effective efforts on resistive nonvolatile memories (NVMs), but they fail to meet the requirements for secure FeFET-based memories due to the different capacitive FeFETs load. Directly applying these existing countermeasures to the P-SCA protection for FeFETs induces huge challenges, especially for the balance between power side-channel resistance and corresponding overheads. To address this issue, we leverage the unique features of FeFETs and propose ProtFe , namely the protection methods for FeFET-based memories, including the pipelined multi-step write strategy ( PiMWrite ) and the split array design ( SpA ). PiMWrite is proposed for general FeFET-based memories, and inserts specially designed intermediate states to mitigate information leakage with pipelined steps to reduce overheads. SpA is proposed for custom FeFET-based memories, and simultaneously writes two split portions of the array with shared minimized peripherals to go beyond the balance between security and overheads. Simulation results show that PiMWrite expands the search space of a single power trace to 21× and involves nearly zero hardware penalties. SpA presents 33× search space improvement with negligible latency, 0.6% area, and only 7.1% energy overhead. ProtFe achieves improved balance between security and overheads, compared with the state-of-the-art works.

Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel Closure

Modern high-performance and high-bandwidth three-dimensional (3D) memories are characterized by frequent heating. Prior art suggests turning off hot channels and migrating data to the background DDR memory, incurring significant performance and energy overheads. We propose three Dynamic Thermal Management (DTM) approaches for 3D memories, reducing these overheads. The first approach, Rotating-channel Low-power-state-based DTM (RL-DTM) , minimizes the energy overheads by avoiding data migration. RL-DTM places 3D memory channels into low power states instead of turning them off. Since data accesses are disallowed during low power state, RL-DTM balances each channel’s low-power-state duration. The second approach, Masked rotating-channel Low-power-state-based DTM (ML-DTM) , is a fine-grained policy that minimizes the energy-delay product (EDP) and improves the performance of RL-DTM by considering the channel access rate. The third strategy, Partial channel closure and ML-DTM , minimizes performance overheads of existing channel-level turn-off-based policies by closing a channel only partially and integrating ML-DTM, reducing the number of channels being turned off. We evaluate the proposed DTM policies using various mixes of SPEC benchmarks and multi-threaded workloads and observe them to significantly improve performance, energy, and EDP over state-of-the-art approaches for different 3D memory architectures.