Energy-efficient Level Shifter Research Articles

An Ultra Low Voltage Energy Efficient Level Shifter With Current Limiter and Improved Split-Controlled Inverter

An Ultra Low Voltage Energy Efficient Level Shifter With Current Limiter and Improved Split-Controlled Inverter

A 0.166 pJ/b/pF, 3.5–5 Gb/s TSV I/O Interface With V OH Drift Control

A voltage-mode transmitter (TX) with a predriver and a receiver (RX) with an energy-efficient level shifter (LS) is proposed to reduce power consumption in the heavy load of a through-silicon via (TSV) input–output (I/O) interface. An N-over-N (NN) driver with the proposed predriver reduces <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{OH}$ </tex-math></inline-formula> drift to enhance jitter characteristics. In addition, the swing level of the transmitted signal can be lowered to 600 mV with a single supply voltage at the TX. To recover the swing level, the RX is designed with the proposed LS that can operate with a data rate of 5 Gb/s. An 8-stacked TSV is emulated in the 65 nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency is 0.166 pJ/b/pF with a pseudorandom binary sequence (PRBS)-7 at 5 Gb/s and 0.205 pJ/b/pF with a PRBS-31 at 3.5 Gb/s.

A 6.9-μm2 3.26-ns 31.25-fj Robust Level Shifter With Wide Voltage and Frequency Ranges

This brief presents an area- and energy-efficient level shifter (LS) with wide voltage and frequency ranges. The proposed LS removes the static current with a cut-off head PMOS. The LS also provides a robust internal node compared to other state-of-the-art LSs, where the internal node is floated. To reduce the delay and energy consumption in the proposed LS, the contention between the pull-up and pull-down networks at the internal node is reduced by using a `low' to `high' transition error correction circuit (LtH ECC), which also enables high frequency operation at near- and sub-threshold voltages. The proposed LS is implemented in 65 nm CMOS technology, having the smallest area of 6.90 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sup> among state-of-art LSs. The measurement results demonstrate that the minimum low-level supply voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> DDL,MIN</sub> ) values are 120 mV and 300 mV with input frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> IN</sub> ) of 1 MHz and 100 MHz, respectively, at a high-level supply voltage of 1.2 V. The delay and energy consumption at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDL</sub> of 120 mV and 300 mV are 207 ns and 1040 fJ, and 3.26 ns and 31.25 fJ, respectively. The static power consumption is less than 3 nW at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDL</sub> ranging from 120 mV to 700 mV.

An Energy-Efficient Level Shifter for Ultra Low-Voltage Digital LSIs

This brief presents a fast and energy-efficient level shifter with wide conversion range. To achieve both energy-efficient and high-speed voltage level conversion, a novel architecture combined with multi-threshold CMOS technique is employed in the proposed circuit. A mixed-threshold current mirror circuit is proposed to solve the reduced swing issue in the prior arts. Moreover, auxiliary bias circuits are inserted to guarantee that the low-threshold pull down networks could be strongly cut off while in leaking state. As a result, the power consumption would be reduced to a great extent. Measurement results based on SMIC 55-nm MTCMOS process demonstrate that the proposed level shifter could provide robust voltage conversion from 0.12V to 1.2V. At the target voltage of 0.3V, the proposed level shifter shows a propagation delay of 17.86ns, a static power of 73.95pW, and an energy per transition of 26.59fJ for input frequency of 1MHz.

An ultra-low leakage energy efficient level shifter with wide conversion range

An ultra-low leakage energy efficient level shifter with wide conversion range

A Compact 31.47 fJ/Conversion Subthreshold Level Shifter With Wide Conversion Range in 65 nm MTCMOS

This paper presents an energy-efficient level shifter design that is capable of converting an extremely low input voltage to the supply voltage level. Featuring a core area as compact as $32.99~\mu \text{m}^{2}$ , the proposed design comprises a front-end current mirror and an output cross-coupled structure. Concretely, the current mirror is used to boost the complementary input signals to a proper level, with the operations of pull-up and pull-down networks well-balanced. The cross-coupled structure is used at the second stage to achieve a full-swing output. In addition, multi-threshold CMOS transistors are employed and optimized to elevate the circuit performance. The prototype was fabricated using a commercial 65-nm CMOS process. Experiments show that a 90-mV low input voltage can be successfully converted to 1.2 V. The energy consumed per conversion is reported to be 31.47 fJ for converting a 0.2-V input to 1.2 V at 10 MHz, and the corresponding propagation delay is measured to be 23.98 ns.

An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror

This brief presents an energy-efficient level shifter (LS) to convert a subthreshold input signal to an above-threshold output signal. In order to achieve a wide range of conversion, a dual current mirror (CM) structure consisting of a virtual CM and an auxiliary CM is proposed. The circuit has been implemented and optimized in SMIC 40-nm technology. The postlayout simulation demonstrates that the new LS can achieve voltage conversion from 0.2 to 1.1 V. Moreover, at the target voltage of 0.3 V, the proposed LS exhibits an average propagation delay of 66.48 ns, a total energy per transition of 72.31 fJ, and a static power consumption of 88.4 pW, demonstrating an improvement of $6.0\times $ , $13.1\times $ , and $89.0\times $ , respectively, when compared with Wilson CM-based LS.

An Ultralow-Voltage Energy-Efficient Level Shifter

This brief presents an energy-efficient level shifter (LS) able to convert extremely low level input voltages to the nominal voltage domain. To obtain low static power consumption, the proposed architecture is based on the single-stage differential-cascode-voltage-switch scheme. Moreover, it exploits self-adapting pull-up networks to increase the switching speed and to reduce the dynamic energy consumption, while a split input inverting buffer is used as the output stage to further improve energy efficiency. When implemented in a commercial 180-nm CMOS process, the proposed design can up-convert from the deep subthreshold regime (sub-100 mV) to the nominal supply voltage (1.8 V). For the target voltage level conversion from 0.4 to 1.8 V, our LS exhibits an average propagation delay of 31.7 ns, an average static power of less than 60 pW, and an energy per transition of 173 fJ, as experimentally measured across the test chips.

An energy efficient sub-threshold to above-threshold level shifter using a modified Wilson current mirror

ABSTRACTIn this article, a new energy efficient level shifter circuit is described for robust sub-threshold to above-threshold voltage conversion. The design is based on a modification of the Wilson current mirror that minimizes the static current and improves the energy efficiency. The proposed level shifter is capable of converting a 200 mV signal into a 1 V signal and operates correctly across process corners. At the design target ( 200 mV, input signal frequency = 1 MHz), the proposed level shifter exhibits a propagation delay of 20.17 ns, a static power dissipation of 11.07 nW, and the total energy per transition of 113.2 fJ. We compare our results with the design proposed by Lutkemeier and Ruckert (2010). At the design target, the energy delay product of our design is 81.53% that of the reference design and, over all the voltage range of from 160 mV to 1 V, the proposed circuit shows an average energy reduction of 14.71% compared to the reference design. Thorough variability analysis was performed using HSPICE Monte Carlo simulations for different values of , which reveals the robustness of the proposed design.