Abstract The continued scaling of 3D NAND flash memory presents significant challenges due to process-induced variations such as channel thickness, trap density, grain size, and interface traps/defects at gate stack interfaces (Filler Oxide/Channel/O/N/O). This study systematically analyzes their impact on string current and overall device performance. Increased channel thickness and trap density, coupled with reduced grain size, exacerbate charge scattering and degrade carrier mobility, leading to threshold voltage (Vth) shifts and a reduction in drive current (Ion). Additionally, interface traps within the gate stack introduce excess charge-trapping states, impairing carrier transport, causing Vth drift, reducing Ion, increasing leakage current, and slowing P/E speed. Furthermore, cumulative P/E cycling accelerates interface trap formation and charge trapping, narrowing the program/erase (P/E) memory window, leading to endurance degradation. This study highlights the critical role of fabrication processes (channel thickness, channel trap density, grain size) and the control of interface gate traps/defects for improving the performance and reliability of next-generation 3D NAND flash memory technologies.

Research on the repeated folding mechanism of membrane antennas based on crease endurance degradation

The inherent bottleneck of the von Neumann architecture and the limited power budget of edge devices necessitate energy-efficient hardware solutions for artificial intelligence. Memristor-based In-Memory Computing (IMC) has emerged as a promising candidate; however, the high-power consumption of peripheral circuits, particularly Analog-to-Digital Converters (ADCs), and the reliability issues of memristive devices remain significant challenges. In this paper, we propose a hybrid Convolutional Spiking Neural Network (CSNN) architecture designed for resource-constrained edge computing. Our approach integrates digital Non-Leaky Integrate-and-Fire (NLIF) neurons with Knowm Self-Directed Channel (SDC) memristor-based synapses in a 1T1R crossbar array. To maximize power efficiency, we replace conventional high-resolution ADCs with a streamlined readout circuit utilizing a Current Sense Amplifier (CSA) and a 1-bit comparator. Furthermore, we employ an intensity-to-latency temporal coding scheme to minimize spike activity and mitigate device endurance degradation. We validated the proposed system using the MNIST dataset, achieving a classification accuracy of 97.8%, which is comparable to state-of-the-art floating-point SNNs using supervised learning methods. Power analysis confirms that our 1-bit readout method consumes only 18.4% of the energy required by an 8-bit ADC-based approach while maintaining negligible accuracy loss. Additionally, the deterministic single-spike nature of our temporal coding significantly reduces write stress on memristors compared to rate coding. These results demonstrate that the proposed hybrid CSNN offers a robust and energy-efficient solution for neuromorphic edge intelligence.

The development of next-generation memory architectures is essential to overcoming limitations of conventional architectures, notably the von Neumann bottleneck. Among emerging technologies, memristors have attracted considerable attention due to their scalability, low power consumption, and neuromorphic potential. However, limited endurance and retention, as well as process-integration constraints, continue to impede practical deployment. HfO 2 -based memristors are promising due to silicon compatibility and thermal stability, yet switching stability remains a key challenge. Here, we systematically investigate the structural role of the orthorhombic phase in Hf 0.5 Zr 0.5 O 2 (HZO)-based memristors during the degradation process. Using in situ synchrotron X-ray diffraction (XRD) under an applied electric field, we tracked the field-driven structural evolution over repeated SET/RESET cycles. The orthorhombic phase diffraction intensity progressively decreases and peak broadening increases with cycling, while no distinct shift indicative of a macroscopic phase transition is observed within the experimental resolution. This degradation of crystallinity correlates with the rupture of conductive filaments and eventual device breakdown. These findings highlight the critical role of the orthorhombic phase in both switching behavior and device failure, providing insight into phase-engineered stability in memristive devices. • In-situ biased XRD captures field-driven structural changes in HZO memristors. • Vacancy-rich orthorhombic phase stabilizes filaments and resistive switching. • Cycling drives vacancy migration to LSMO, rupturing filaments and degrading crystallinity. • Transport shifts from TFL/SCLC to Ohmic, evidencing trap depletion and endurance limits.

We demonstrate reliable triple-level cell operation in HfZrO2-based ferroelectric memristors by precisely modulating partial-switching voltages to define eight distinct polarization states. Although stable multi-bit storage is achieved, endurance degradation arising from polarization fatigue remains a major limitation. To mitigate this issue, we introduce a domain-recovery strategy that employs interleaved high-voltage pulses combined with electrically quiescent break intervals. This approach restores polarization states by alleviating domain-wall pinning, enabling endurance exceeding 106 cycles. Notably, we find that spontaneous domain relaxation during short idle periods further contributes to fatigue recovery, whereas excessively long breaks induce domain disorientation. These findings reveal the critical roles of both electrical and time-controlled recovery in stabilizing ferroelectric switching behavior. Our results provide a practical route to enhancing the reliability of high-density ferroelectric memory and yield new physical insights into fatigue dynamics under multi-level operation.

Plasma-based interfacial treatments have previously enhanced the performance of filamentary-conductive resistive switching memories (RSMs). Still, strategies for improving bulk-conductive RSMs remain limited. While the bulk-conductive RSM has been explored for neuromorphic computing due to its gradual and analog switching behavior that allows for linear conductance change, it suffers from endurance degradation under repeated cycling. This study introduces a cyclic plasma treatment (CPT) method, employing periodic Ar plasma exposure during the deposition of an HfO2 switching layer via plasma-enhanced atomic layer deposition. The performances of W/HfO2/TiN (WHT) bulk-conductive RSMs with and without CPT were compared to evaluate the influence of CPT. The CPT effectively decreased switching degradation by introducing additional oxygen vacancies into the switching layer, compensating for the loss of trap sites caused by oxygen recombination. Device endurance improved from 104 to 106 cycles, and cycle-to-cycle and device-to-device variations improved by 77% and 78%, respectively. The MNIST classification simulation was performed by using cyclic plasma-treated WHT RSMs, achieving a high accuracy of 91.4%. This result demonstrates CPT as a promising solution for enhancing bulk-conductive resistive switching in neuromorphic computing.

Lead-free Cs3Bi2Br9 perovskite memristors have emerged as promising candidates for nonvolatile memory and neuromorphic computing due to their environmental friendliness and stability. However, their practical applications are hindered by severe endurance degradation during repetitive resistive switching (RS) cycles, attributed to incomplete RESET of conductive filaments (CFs) at grain boundaries (GBs). Herein, we systematically investigate this degradation mechanism and propose two innovative strategies to enhance device endurance: (1) grain engineering via thermal annealing to reduce GB density and (2) GB passivation using polyethylene glycol (PEG) additives. By optimizing annealing temperatures (100–250 °C), Cs3Bi2Br9 films exhibit progressively larger grain sizes (158.6–295.2 nm), which delays high resistance state degradation by minimizing CF nucleation sites. However, residual GBs still permit partial Ag accumulation. To address this, PEG incorporation chemically passivates GBs, effectively blocking ion migration and trapping. The optimized PEG-passivated Ag/Cs3Bi2Br9:PEG/ITO memristor achieves remarkable improvements: endurance is extended from 100 to 1000 cycles, and the switching window expands from 6 to 176 times. Furthermore, the optimized device demonstrates continuous conductance modulation for multilevel storage and synaptic function emulation, enabling a 784–100–10 fully connected neural network to achieve 92.2% recognition accuracy on the MNIST dataset after 100 training epochs. This study elucidates the GB-mediated degradation mechanism and demonstrates that combining grain size optimization with GB passivation provides a universal framework for high-performance RS devices in neuromorphic computing and nonvolatile memory.

The Spin-Transfer-Torque Magnetic-Random-Access-Memory (STT-MRAM) has inherent advantages as a One-Time-Programmable (OTP) memory. The Magnetic Tunnel Junction (MTJ) are particularly susceptible to breakdown effect. We also need to reduce the endurance degradation effects during normal write process of MRAM. In this paper, we propose twin progressive models of MTJ breakdown. The endurance degradation model evaluates the trade-off between MTJ endurance and write error rate (WER), while the breakdown time distribution model corrects theoretical MTJ hard breakdown probabilities. The twin models leverage MTJ Time-Dependent-Dielectric-Breakdown (TDDB) and hard breakdown measurement data. The 4-Mb STT-MRAM sub-system was successfully demonstrated using our twin progressive models for reliability-aware design.

We experimentally analyze the incremental step pulse programming (ISPP) characteristics of gate-side injection type MIFIS FeFETs, which feature a metal – gate interlayer (G.IL) – ferroelectrics – channel interlayer (Ch.IL) – Si stack, with a focus on the role of the G.IL. We also propose a mathematical model considering ferroelectric (FE) switching behavior. MIFIS FeFETs have recently garnered attention due to their ability to achieve lower program (PGM) voltages and wider memory windows (MWs) compared to typical channel-side injection type charge trap flash (CTF) devices, thanks to the injection of charges (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>it</roman></sub>') from the gate and polarization switching dynamics. However, guidelines on the influence of the G.IL on ISPP characteristics and endurance, critical for NAND cell, are lacking. Here, we experimentally investigate the impact of the G.IL on the ISPP slope of MIFIS FeFETs and, through mathematical modeling, propose a G.IL design to optimize MIFIS FeFET performance. Furthermore, we analyze the degradation of endurance characteristics depending on the type of G.IL, suggesting that the excessive <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>it</roman></sub> injected from the Ch.IL, together with polarization pinning, contributes to overall endurance degradation. Lastly, we demonstrate that by utilizing a low-κ SiO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub> G.IL (6 nm), a MW of 6.5 V and an ISPP slope greater than 3 can be achieved. Our MIFIS FeFET also exhibits disturbance immunity even at voltages exceeding 14 V, which is critical in preventing <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub> shifts during various disturbances. Our research and model can provide valuable guidelines for the study of gate-injection type FeFET, which are actively being explored as next-generation NAND Flash memory technologies.

Statistical Investigation of Al$_{2}$O$_{3}$ Insertion Layer on the Endurance of Hf$_{0.5}$Zr$_{0.5}$O$_{2}$ Films: Abrupt Endurance Degradation and Mechanism

We report the use of a low-thermal-budget annealing technique; flash lamp annealing (FLA), which provides an extremely short annealing time in the millisecond range, on the ferroelectric properties of Al-doped HfO2 (HAO) films. HAO annealed at 1000 °C with 5 ms shows a higher remanent polarization value of 24.9 μC cm−2 compared to rapid thermal annealing (RTA), without degradation of endurance. GIXRD shows a stronger peak intensity originating from the orthorhombic (o-) phase and is observed when using FLA, indicating the formation of a larger amount of the o-phase. We believe that this is a consequence of the low thermal budget of FLA, and that specifically FLA can minimize the relaxation of the compressive stress in the TiN electrodes, inducing a high tensile stress to the HAO films and therefore an enhancement of o-phase formation. These results indicate that FLA is a promising annealing method for HAO crystallization due to the enhancement of o-phase formation.

In this letter, the ferroelectric capacitors featuring Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> films with different oxygen dose have been constructed. It is found that the sample grown at oxygen-deficient condition exhibits a smaller remanent polarization (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> ), a larger dielectric constant (ε <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> ), a faster switching and better cycle reliability (over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> @ 4 MV/cm). The connection between its better reliability and polarization switching speed with its dielectric and ferroelectric properties is established with the switching-induced charge-injection model. The larger interfacial depolarization field ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dep</sub> ) impedes the domain switching at the early nucleation process and wears out the metal/ferroelectric interface, leading to the endurance degradation. Our work reveals that the oxygen-deficient sample with a smaller <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> and a large ε <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> shows a smaller <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dep</sub> near the interface, tend to switch faster, thus also benefits the reliability. It provides better understanding of process modulating domain switch kinetics and reliability in HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> based ferroelectric devices from both theoretical and experiment perspective.

Interplay between oxygen vacancies and the stabilization of the ferroelectric orthorhombic phase in doped HfO2, as well as the resulting impact on endurance and retention, is far from being well understood. In Hf0.5Zr0.5O2 (HZO) thin films, it is commonly found that high polarization occurs usually at the the expense of robustness upon cycling due to the polarization–endurance dilemma. It has been reported that HZO thin films grown by pulsed laser deposition under the mixed Ar and O2 atmosphere exhibit a high polarization. Here, we show that this strategy enables functional properties tuning, allowing to obtain HZO films with high polarization at low oxidation conditions without degradation of endurance and retention.

Hybrid flash-based storage constructed with high-density and low-cost flash memory has become increasingly popular in consumer devices in the last decade due to its low cost. However, its poor reliability is one of the major concerns. To protect critical data for guaranteeing user experience, some methods are proposed to improve the reliability of consumer devices with non-hybrid flash storage. However, with the widespread use of hybrid storage, these methods will result in severe problems, including significant performance and endurance degradation. This is caused by the fact that the different characteristics of flash memory in hybrid storage are not considered, e.g., performance, endurance, and access granularity. To address these problems, a critical data backup (CDB) design is proposed to ensure critical data reliability at a low cost. The basic idea is to accumulate two copies of critical data in the fast memory first to make full use of its performance and endurance. Then, one copy will be migrated to the slow memory in the stripe to avoid the write amplification caused by different access granularity between them. By respecting the different characteristics of flash memory in hybrid storage, CDB can achieve encouraging performance and endurance improvement compared with the state-of-the-art. Furthermore, to avoid performance and lifetime degradation caused by the backup data occupying too much space of fast memory, CDB Pro is designed. Two advanced schemes are integrated. One is making use of the pseudo-single-level-cell (pSLC) technique to make a part of slow memory become high-performance. By supplying some high-performance space, data will be fully updated before being evicted to slow memory. More invalid data are generated which reduces eviction costs. Another is to categorize data into three types according to their different life cycles. By putting the same type of data in a block, the eviction efficiency is improved. Therefore, both can improve device performance and lifetime based on CDB. Experiments are conducted to prove the efficiency of CDB and CDB Pro. Experimental results show that compared with the state-of-the-arts, CDB can ensure critical data reliability with lower device performance and lifetime loss whereas CDB Pro can diminish the loss further.

NbOx-based devices exhibit intriguing promise for beyond-CMOS applications due to their dynamic threshold switching (TS) and negative differential resistance (NDR) behaviors. However, an in-depth study on the degradation scheme of such a device is absent. In this work, we investigate the degradation behavior, i.e., the shift of switching voltages ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {hold}}$ </tex-math></inline-formula> ) and the shrink of voltage window (VW), of a nanoscale forming-free TiN/NbOx/TiN memristor. Through electrical tests and random telegraph noise (RTN)-based defect tracking, we proved that the shrink of the VW and the increase of switching voltages originate from the increase of electrode resistance due to the oxygen vacancy accumulation. According to the elucidated degradation mechanisms, we propose a reverse refresh strategy to extend the endurance and delay VW degradation. This work provides a possible view of NbOx devices’ degradation and may promote the applications.

We propose an in situ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> measurement method to investigate the endurance fatigue mechanism of Si ferroelectric field-effect transistor (FeFET) with HfZrO ferroelectric. The in situ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> measurement method means that a pulsed current-voltage measurement is embedded during the quasi-static capacitance-voltage (QSCV) measurement. Based on this method, the trapped charges can be extracted as a function of the gate voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{g}{)}$ </tex-math></inline-formula> . We find that: First, the trapped electrons and holes show asymmetric de-trapping dynamics. Excess electrons continuously de-trap within the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{g}$ </tex-math></inline-formula> ranging from the maximum positive value to ferroelectric reverse switching. However, the trapped holes do not de-trap when the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{g}$ </tex-math></inline-formula> changes from the minimum negative value to 0 V. Second, the increase of donor trap density is the key to endurance fatigue. During endurance fatigue, the total amounts of trapped electrons are unchanged near the maximum positive voltage, but the amounts of de-trapped electrons decrease when the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{g}$ </tex-math></inline-formula> returns to 0 V due to donor trap density increases. In addition, we apply our method in the scaled FeFET to overcome the measurement limitation of gate charges ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}_{m}{)}$ </tex-math></inline-formula> by the nowadays equipment.

In this work, we analyze a resistive switching random access memory (RRAM) device with the metal–insulator–metal structure of Al/αTiOx/Al. The transport mechanism of our RRAM device is trap-controlled space-charge limited conduction, which does not change during the endurance test. As the number of resistive switching (RS) cycles increases, the current in the low-resistance state (LRS) does not change significantly. In contrast, degradation in the high-resistance state (HRS) is noticeably evident. According to the RS cycle, the current shift fits well with the stretched-exponential equation. The normalized noise power spectral density (Si/I2) measured in the HRS is an order of magnitude higher than that in the LRS owing to the difference in the degree of trap occupancy, which is responsible for the transition of resistance states. During the consecutive RS, the Si/I2 in the HRS rapidly decreases for approximately 100 cycles and then saturates. In contrast, in the LRS, the Si/I2 does not change significantly. Here we propose a model associated with the endurance degradation of the experimental device, and the model is verified with a noise measurement.

The endurance degradation of HfO2-based ferroelectric films limits their development toward practical applications. In this work, we systematically investigate the ferroelectric endurance properties of Hf0.5Zr0.5O2 (HZO) film under various pulse voltages and pulse widths, and it is found that the fatigue severity increases first and then decreases with increasing pulse voltage or width. The nonmonotonic fatigue trend explains the controversial results in the literature that both faster and slower fatigues with increasing voltage were observed in HZO. Accordingly, low voltages of ±1.6 V/100 ns are applied for cycling the HZO device to achieve weaker fatigue and a sufficiently switched ferroelectric polarization (7–12 μC cm−2), and a recovery method by introducing wake-up effect is utilized to realize an enhanced endurance &amp;gt;1.01 × 1012 (&amp;gt;5.0 × 1013 in expectation). Our work provides a universal way to weaken fatigue and improve endurance performance of HfO2-based ferroelectric random access memory devices.

The effect of oxygen affinity electrode Ti on the performance of vanadium oxide-based valence change resistive random access memory

In 3-D charge trap (CT) NAND flash memory, program/erase (P/E) cycling tests are performed, and the degradation of cell characteristics is investigated. The mechanism of mid-gap voltage (Vmg) shift difference between erased state and programmed state is presented and it is verified by technology computer-aided design (TCAD) simulation configured identically to the real device. TCAD simulation also makes it possible to extract the trap density through the current fitting. Generation of interface traps (Nit) and bulk traps in the tunneling oxide (Not) has the form of a power-law of the number of P/E cycles. Furthermore, it is experimentally found that the degradation of cell characteristics is mainly caused by hole tunneling current from the poly-silicon channel during erase operation.